mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-19 09:38:32 -04:00
Normalize line endings and whitespace in source files
This commit is contained in:
Paul Bartell
Paul Bartell
parent
151fb04ad1
commit
01820d3ed9
574 changed files with 162626 additions and 172362 deletions
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@ -44,83 +44,83 @@ void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_
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{
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r1, [r2] \n"/* Read pxCurrentTCB. */
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" ldr r0, [r1] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
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" \n"
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" .syntax unified \n"
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" \n"
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" ldr r2, pxCurrentTCBConst2 \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r1, [r2] \n"/* Read pxCurrentTCB. */
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" ldr r0, [r1] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
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" \n"
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#if ( configENABLE_MPU == 1 )
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" dmb \n"/* Complete outstanding transfers before disabling MPU. */
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" ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
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" bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
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" str r4, [r2] \n"/* Disable MPU. */
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" \n"
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" adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
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" ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */
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" ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
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" str r3, [r2] \n"/* Program MAIR0. */
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" ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
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" movs r3, #4 \n"/* r3 = 4. */
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" str r3, [r2] \n"/* Program RNR = 4. */
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" adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
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" ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
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" ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
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" stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
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" \n"
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" dmb \n"/* Complete outstanding transfers before disabling MPU. */
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" ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
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" bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
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" str r4, [r2] \n"/* Disable MPU. */
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" \n"
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" adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
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" ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */
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" ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
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" str r3, [r2] \n"/* Program MAIR0. */
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" ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
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" movs r3, #4 \n"/* r3 = 4. */
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" str r3, [r2] \n"/* Program RNR = 4. */
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" adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
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" ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
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" ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
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" stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
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" \n"
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#if ( configTOTAL_MPU_REGIONS == 16 )
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" ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
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" movs r3, #8 \n"/* r3 = 8. */
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" str r3, [r2] \n"/* Program RNR = 8. */
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" ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
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" ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
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" stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
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" ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
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" movs r3, #12 \n"/* r3 = 12. */
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" str r3, [r2] \n"/* Program RNR = 12. */
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" ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
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" ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
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" stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
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" ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
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" movs r3, #8 \n"/* r3 = 8. */
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" str r3, [r2] \n"/* Program RNR = 8. */
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" ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
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" ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
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" stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
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" ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
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" movs r3, #12 \n"/* r3 = 12. */
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" str r3, [r2] \n"/* Program RNR = 12. */
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" ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
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" ldmia r1!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
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" stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
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#endif /* configTOTAL_MPU_REGIONS == 16 */
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" \n"
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" ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
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" orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
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" str r4, [r2] \n"/* Enable MPU. */
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" dsb \n"/* Force memory writes before continuing. */
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" \n"
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" ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
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" orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
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" str r4, [r2] \n"/* Enable MPU. */
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" dsb \n"/* Force memory writes before continuing. */
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#endif /* configENABLE_MPU */
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" \n"
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" \n"
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#if ( configENABLE_MPU == 1 )
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" ldm r0!, {r1-r3} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
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" msr psplim, r1 \n"/* Set this task's PSPLIM value. */
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" msr control, r2 \n"/* Set this task's CONTROL value. */
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" adds r0, #32 \n"/* Discard everything up to r0. */
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" msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
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" isb \n"
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" mov r0, #0 \n"
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" msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
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" bx r3 \n"/* Finally, branch to EXC_RETURN. */
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" ldm r0!, {r1-r3} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
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" msr psplim, r1 \n"/* Set this task's PSPLIM value. */
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" msr control, r2 \n"/* Set this task's CONTROL value. */
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" adds r0, #32 \n"/* Discard everything up to r0. */
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" msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
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" isb \n"
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" mov r0, #0 \n"
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" msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
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" bx r3 \n"/* Finally, branch to EXC_RETURN. */
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#else /* configENABLE_MPU */
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" ldm r0!, {r1-r2} \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
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" msr psplim, r1 \n"/* Set this task's PSPLIM value. */
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" movs r1, #2 \n"/* r1 = 2. */
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" msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
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" adds r0, #32 \n"/* Discard everything up to r0. */
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" msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
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" isb \n"
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" mov r0, #0 \n"
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" msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
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" bx r2 \n"/* Finally, branch to EXC_RETURN. */
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" ldm r0!, {r1-r2} \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
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" msr psplim, r1 \n"/* Set this task's PSPLIM value. */
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" movs r1, #2 \n"/* r1 = 2. */
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" msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
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" adds r0, #32 \n"/* Discard everything up to r0. */
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" msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
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" isb \n"
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" mov r0, #0 \n"
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" msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
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" bx r2 \n"/* Finally, branch to EXC_RETURN. */
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#endif /* configENABLE_MPU */
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" \n"
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" .align 4 \n"
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"pxCurrentTCBConst2: .word pxCurrentTCB \n"
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" \n"
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" .align 4 \n"
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"pxCurrentTCBConst2: .word pxCurrentTCB \n"
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#if ( configENABLE_MPU == 1 )
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"xMPUCTRLConst2: .word 0xe000ed94 \n"
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"xMAIR0Const2: .word 0xe000edc0 \n"
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"xRNRConst2: .word 0xe000ed98 \n"
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"xRBARConst2: .word 0xe000ed9c \n"
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"xMPUCTRLConst2: .word 0xe000ed94 \n"
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"xMAIR0Const2: .word 0xe000edc0 \n"
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"xRNRConst2: .word 0xe000ed98 \n"
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"xRBARConst2: .word 0xe000ed9c \n"
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#endif /* configENABLE_MPU */
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);
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}
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@ -130,16 +130,16 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
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{
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" mrs r0, control \n"/* r0 = CONTROL. */
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" tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
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" ite ne \n"
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" movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
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" moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
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" bx lr \n"/* Return. */
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" \n"
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" .align 4 \n"
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" .syntax unified \n"
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" \n"
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" mrs r0, control \n"/* r0 = CONTROL. */
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" tst r0, #1 \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
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" ite ne \n"
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" movne r0, #0 \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
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" moveq r0, #1 \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
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" bx lr \n"/* Return. */
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" \n"
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" .align 4 \n"
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::: "r0", "memory"
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);
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}
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@ -149,12 +149,12 @@ void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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{
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" mrs r0, control \n"/* Read the CONTROL register. */
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" bic r0, #1 \n"/* Clear the bit 0. */
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" msr control, r0 \n"/* Write back the new CONTROL value. */
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" bx lr \n"/* Return to the caller. */
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" .syntax unified \n"
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" \n"
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" mrs r0, control \n"/* Read the CONTROL register. */
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" bic r0, #1 \n"/* Clear the bit 0. */
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" msr control, r0 \n"/* Write back the new CONTROL value. */
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" bx lr \n"/* Return to the caller. */
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::: "r0", "memory"
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);
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}
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@ -164,12 +164,12 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
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{
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" mrs r0, control \n"/* r0 = CONTROL. */
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" orr r0, #1 \n"/* r0 = r0 | 1. */
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" msr control, r0 \n"/* CONTROL = r0. */
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" bx lr \n"/* Return to the caller. */
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" .syntax unified \n"
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" \n"
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" mrs r0, control \n"/* r0 = CONTROL. */
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" orr r0, #1 \n"/* r0 = r0 | 1. */
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" msr control, r0 \n"/* CONTROL = r0. */
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" bx lr \n"/* Return to the caller. */
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::: "r0", "memory"
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);
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}
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@ -179,21 +179,21 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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{
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
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" ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
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" ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
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" msr msp, r0 \n"/* Set the MSP back to the start of the stack. */
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" cpsie i \n"/* Globally enable interrupts. */
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" cpsie f \n"
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" dsb \n"
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" isb \n"
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" svc %0 \n"/* System call to start the first task. */
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" nop \n"
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" \n"
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" .align 4 \n"
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"xVTORConst: .word 0xe000ed08 \n"
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" .syntax unified \n"
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" \n"
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" ldr r0, xVTORConst \n"/* Use the NVIC offset register to locate the stack. */
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" ldr r0, [r0] \n"/* Read the VTOR register which gives the address of vector table. */
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" ldr r0, [r0] \n"/* The first entry in vector table is stack pointer. */
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" msr msp, r0 \n"/* Set the MSP back to the start of the stack. */
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" cpsie i \n"/* Globally enable interrupts. */
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" cpsie f \n"
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" dsb \n"
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" isb \n"
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" svc %0 \n"/* System call to start the first task. */
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" nop \n"
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" \n"
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" .align 4 \n"
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"xVTORConst: .word 0xe000ed08 \n"
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::"i" ( portSVC_START_SCHEDULER ) : "memory"
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);
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}
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@ -203,14 +203,14 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
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{
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */
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" mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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" msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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" dsb \n"
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" isb \n"
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" bx lr \n"/* Return. */
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" .syntax unified \n"
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" \n"
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" mrs r0, basepri \n"/* r0 = basepri. Return original basepri value. */
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" mov r1, %0 \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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" msr basepri, r1 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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" dsb \n"
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" isb \n"
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" bx lr \n"/* Return. */
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::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
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);
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}
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@ -220,12 +220,12 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
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{
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" msr basepri, r0 \n"/* basepri = ulMask. */
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" dsb \n"
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" isb \n"
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" bx lr \n"/* Return. */
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" .syntax unified \n"
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" \n"
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" msr basepri, r0 \n"/* basepri = ulMask. */
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" dsb \n"
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" isb \n"
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" bx lr \n"/* Return. */
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::: "memory"
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);
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}
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@ -235,110 +235,110 @@ void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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{
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" mrs r0, psp \n"/* Read PSP in r0. */
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" .syntax unified \n"
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" \n"
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" mrs r0, psp \n"/* Read PSP in r0. */
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#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
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" tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
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" it eq \n"
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" vstmdbeq r0!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */
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" tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
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" it eq \n"
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" vstmdbeq r0!, {s16-s31} \n"/* Store the additional FP context registers which are not saved automatically. */
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#endif /* configENABLE_FPU || configENABLE_MVE */
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#if ( configENABLE_MPU == 1 )
|
||||
" mrs r1, psplim \n"/* r1 = PSPLIM. */
|
||||
" mrs r2, control \n"/* r2 = CONTROL. */
|
||||
" mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
|
||||
" stmdb r0!, {r1-r11} \n"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
|
||||
" mrs r1, psplim \n"/* r1 = PSPLIM. */
|
||||
" mrs r2, control \n"/* r2 = CONTROL. */
|
||||
" mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
|
||||
" stmdb r0!, {r1-r11} \n"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
|
||||
#else /* configENABLE_MPU */
|
||||
" mrs r2, psplim \n"/* r2 = PSPLIM. */
|
||||
" mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
|
||||
" stmdb r0!, {r2-r11} \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
|
||||
" mrs r2, psplim \n"/* r2 = PSPLIM. */
|
||||
" mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
|
||||
" stmdb r0!, {r2-r11} \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
|
||||
#endif /* configENABLE_MPU */
|
||||
" \n"
|
||||
" ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
||||
" ldr r1, [r2] \n"/* Read pxCurrentTCB. */
|
||||
" str r0, [r1] \n"/* Save the new top of stack in TCB. */
|
||||
" \n"
|
||||
" mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
|
||||
" msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
|
||||
" dsb \n"
|
||||
" isb \n"
|
||||
" bl vTaskSwitchContext \n"
|
||||
" mov r0, #0 \n"/* r0 = 0. */
|
||||
" msr basepri, r0 \n"/* Enable interrupts. */
|
||||
" \n"
|
||||
" ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
||||
" ldr r1, [r2] \n"/* Read pxCurrentTCB. */
|
||||
" ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
|
||||
" \n"
|
||||
" \n"
|
||||
" ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
||||
" ldr r1, [r2] \n"/* Read pxCurrentTCB. */
|
||||
" str r0, [r1] \n"/* Save the new top of stack in TCB. */
|
||||
" \n"
|
||||
" mov r0, %0 \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
|
||||
" msr basepri, r0 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
|
||||
" dsb \n"
|
||||
" isb \n"
|
||||
" bl vTaskSwitchContext \n"
|
||||
" mov r0, #0 \n"/* r0 = 0. */
|
||||
" msr basepri, r0 \n"/* Enable interrupts. */
|
||||
" \n"
|
||||
" ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
||||
" ldr r1, [r2] \n"/* Read pxCurrentTCB. */
|
||||
" ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
|
||||
" \n"
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
" dmb \n"/* Complete outstanding transfers before disabling MPU. */
|
||||
" ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
|
||||
" ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
|
||||
" bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
|
||||
" str r4, [r2] \n"/* Disable MPU. */
|
||||
" \n"
|
||||
" adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
|
||||
" ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */
|
||||
" ldr r2, xMAIR0Const \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
|
||||
" str r3, [r2] \n"/* Program MAIR0. */
|
||||
" ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
|
||||
" movs r3, #4 \n"/* r3 = 4. */
|
||||
" str r3, [r2] \n"/* Program RNR = 4. */
|
||||
" adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
|
||||
" ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
|
||||
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
|
||||
" stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
|
||||
" \n"
|
||||
" dmb \n"/* Complete outstanding transfers before disabling MPU. */
|
||||
" ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
|
||||
" ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
|
||||
" bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
|
||||
" str r4, [r2] \n"/* Disable MPU. */
|
||||
" \n"
|
||||
" adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
|
||||
" ldr r3, [r1] \n"/* r3 = *r1 i.e. r3 = MAIR0. */
|
||||
" ldr r2, xMAIR0Const \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
|
||||
" str r3, [r2] \n"/* Program MAIR0. */
|
||||
" ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
|
||||
" movs r3, #4 \n"/* r3 = 4. */
|
||||
" str r3, [r2] \n"/* Program RNR = 4. */
|
||||
" adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
|
||||
" ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
|
||||
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
|
||||
" stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
|
||||
" \n"
|
||||
#if ( configTOTAL_MPU_REGIONS == 16 )
|
||||
" ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
|
||||
" movs r3, #8 \n"/* r3 = 8. */
|
||||
" str r3, [r2] \n"/* Program RNR = 8. */
|
||||
" ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
|
||||
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
|
||||
" stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
|
||||
" ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
|
||||
" movs r3, #12 \n"/* r3 = 12. */
|
||||
" str r3, [r2] \n"/* Program RNR = 12. */
|
||||
" ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
|
||||
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
|
||||
" stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
|
||||
" ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
|
||||
" movs r3, #8 \n"/* r3 = 8. */
|
||||
" str r3, [r2] \n"/* Program RNR = 8. */
|
||||
" ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
|
||||
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
|
||||
" stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
|
||||
" ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
|
||||
" movs r3, #12 \n"/* r3 = 12. */
|
||||
" str r3, [r2] \n"/* Program RNR = 12. */
|
||||
" ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
|
||||
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
|
||||
" stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
|
||||
#endif /* configTOTAL_MPU_REGIONS == 16 */
|
||||
" \n"
|
||||
" ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
|
||||
" ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
|
||||
" orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
|
||||
" str r4, [r2] \n"/* Enable MPU. */
|
||||
" dsb \n"/* Force memory writes before continuing. */
|
||||
" \n"
|
||||
" ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
|
||||
" ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
|
||||
" orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
|
||||
" str r4, [r2] \n"/* Enable MPU. */
|
||||
" dsb \n"/* Force memory writes before continuing. */
|
||||
#endif /* configENABLE_MPU */
|
||||
" \n"
|
||||
" \n"
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
" ldmia r0!, {r1-r11} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
|
||||
" ldmia r0!, {r1-r11} \n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
|
||||
#else /* configENABLE_MPU */
|
||||
" ldmia r0!, {r2-r11} \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
|
||||
" ldmia r0!, {r2-r11} \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
|
||||
#endif /* configENABLE_MPU */
|
||||
" \n"
|
||||
" \n"
|
||||
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
|
||||
" tst r3, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
|
||||
" it eq \n"
|
||||
" vldmiaeq r0!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */
|
||||
" tst r3, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
|
||||
" it eq \n"
|
||||
" vldmiaeq r0!, {s16-s31} \n"/* Restore the additional FP context registers which are not restored automatically. */
|
||||
#endif /* configENABLE_FPU || configENABLE_MVE */
|
||||
" \n"
|
||||
" \n"
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
" msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
|
||||
" msr control, r2 \n"/* Restore the CONTROL register value for the task. */
|
||||
" msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
|
||||
" msr control, r2 \n"/* Restore the CONTROL register value for the task. */
|
||||
#else /* configENABLE_MPU */
|
||||
" msr psplim, r2 \n"/* Restore the PSPLIM register value for the task. */
|
||||
" msr psplim, r2 \n"/* Restore the PSPLIM register value for the task. */
|
||||
#endif /* configENABLE_MPU */
|
||||
" msr psp, r0 \n"/* Remember the new top of stack for the task. */
|
||||
" bx r3 \n"
|
||||
" \n"
|
||||
" .align 4 \n"
|
||||
"pxCurrentTCBConst: .word pxCurrentTCB \n"
|
||||
" msr psp, r0 \n"/* Remember the new top of stack for the task. */
|
||||
" bx r3 \n"
|
||||
" \n"
|
||||
" .align 4 \n"
|
||||
"pxCurrentTCBConst: .word pxCurrentTCB \n"
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
"xMPUCTRLConst: .word 0xe000ed94 \n"
|
||||
"xMAIR0Const: .word 0xe000edc0 \n"
|
||||
"xRNRConst: .word 0xe000ed98 \n"
|
||||
"xRBARConst: .word 0xe000ed9c \n"
|
||||
"xMPUCTRLConst: .word 0xe000ed94 \n"
|
||||
"xMAIR0Const: .word 0xe000edc0 \n"
|
||||
"xRNRConst: .word 0xe000ed98 \n"
|
||||
"xRBARConst: .word 0xe000ed9c \n"
|
||||
#endif /* configENABLE_MPU */
|
||||
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
|
||||
);
|
||||
|
|
@ -349,17 +349,17 @@ void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
|
|||
{
|
||||
__asm volatile
|
||||
(
|
||||
" .syntax unified \n"
|
||||
" \n"
|
||||
" tst lr, #4 \n"
|
||||
" ite eq \n"
|
||||
" mrseq r0, msp \n"
|
||||
" mrsne r0, psp \n"
|
||||
" ldr r1, svchandler_address_const \n"
|
||||
" bx r1 \n"
|
||||
" \n"
|
||||
" .align 4 \n"
|
||||
"svchandler_address_const: .word vPortSVCHandler_C \n"
|
||||
" .syntax unified \n"
|
||||
" \n"
|
||||
" tst lr, #4 \n"
|
||||
" ite eq \n"
|
||||
" mrseq r0, msp \n"
|
||||
" mrsne r0, psp \n"
|
||||
" ldr r1, svchandler_address_const \n"
|
||||
" bx r1 \n"
|
||||
" \n"
|
||||
" .align 4 \n"
|
||||
"svchandler_address_const: .word vPortSVCHandler_C \n"
|
||||
);
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -155,9 +155,9 @@
|
|||
* 8-bit values encoded as follows:
|
||||
* Bit[7:4] - 0000 - Device Memory
|
||||
* Bit[3:2] - 00 --> Device-nGnRnE
|
||||
* 01 --> Device-nGnRE
|
||||
* 10 --> Device-nGRE
|
||||
* 11 --> Device-GRE
|
||||
* 01 --> Device-nGnRE
|
||||
* 10 --> Device-nGRE
|
||||
* 11 --> Device-GRE
|
||||
* Bit[1:0] - 00, Reserved.
|
||||
*/
|
||||
#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue