mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Normalize line endings and whitespace in source files
This commit is contained in:
Paul Bartell
Paul Bartell
parent
151fb04ad1
commit
01820d3ed9
574 changed files with 162626 additions and 172362 deletions
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@ -1,432 +1,427 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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.text
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/* Variables and functions. */
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.extern ullMaxAPIPriorityMask
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.extern pxCurrentTCB
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.extern vTaskSwitchContext
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.extern vApplicationIRQHandler
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.extern ullPortInterruptNesting
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.extern ullPortTaskHasFPUContext
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.extern ullCriticalNesting
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.extern ullPortYieldRequired
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.extern ullICCEOIR
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.extern ullICCIAR
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.extern _freertos_vector_table
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.global FreeRTOS_IRQ_Handler
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.global FreeRTOS_SWI_Handler
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.global vPortRestoreTaskContext
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.macro portSAVE_CONTEXT
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/* Switch to use the EL0 stack pointer. */
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MSR SPSEL, #0
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/* Save the entire context. */
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STP X0, X1, [SP, #-0x10]!
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STP X2, X3, [SP, #-0x10]!
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STP X4, X5, [SP, #-0x10]!
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STP X6, X7, [SP, #-0x10]!
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STP X8, X9, [SP, #-0x10]!
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STP X10, X11, [SP, #-0x10]!
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STP X12, X13, [SP, #-0x10]!
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STP X14, X15, [SP, #-0x10]!
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STP X16, X17, [SP, #-0x10]!
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STP X18, X19, [SP, #-0x10]!
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STP X20, X21, [SP, #-0x10]!
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STP X22, X23, [SP, #-0x10]!
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STP X24, X25, [SP, #-0x10]!
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STP X26, X27, [SP, #-0x10]!
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STP X28, X29, [SP, #-0x10]!
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STP X30, XZR, [SP, #-0x10]!
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/* Save the SPSR. */
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#if defined( GUEST )
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MRS X3, SPSR_EL1
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MRS X2, ELR_EL1
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#else
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MRS X3, SPSR_EL3
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/* Save the ELR. */
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MRS X2, ELR_EL3
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#endif
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STP X2, X3, [SP, #-0x10]!
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/* Save the critical section nesting depth. */
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LDR X0, ullCriticalNestingConst
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LDR X3, [X0]
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/* Save the FPU context indicator. */
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LDR X0, ullPortTaskHasFPUContextConst
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LDR X2, [X0]
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/* Save the FPU context, if any (32 128-bit registers). */
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CMP X2, #0
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B.EQ 1f
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STP Q0, Q1, [SP,#-0x20]!
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STP Q2, Q3, [SP,#-0x20]!
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STP Q4, Q5, [SP,#-0x20]!
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STP Q6, Q7, [SP,#-0x20]!
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STP Q8, Q9, [SP,#-0x20]!
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STP Q10, Q11, [SP,#-0x20]!
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STP Q12, Q13, [SP,#-0x20]!
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STP Q14, Q15, [SP,#-0x20]!
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STP Q16, Q17, [SP,#-0x20]!
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STP Q18, Q19, [SP,#-0x20]!
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STP Q20, Q21, [SP,#-0x20]!
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STP Q22, Q23, [SP,#-0x20]!
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STP Q24, Q25, [SP,#-0x20]!
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STP Q26, Q27, [SP,#-0x20]!
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STP Q28, Q29, [SP,#-0x20]!
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STP Q30, Q31, [SP,#-0x20]!
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1:
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/* Store the critical nesting count and FPU context indicator. */
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STP X2, X3, [SP, #-0x10]!
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LDR X0, pxCurrentTCBConst
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LDR X1, [X0]
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MOV X0, SP /* Move SP into X0 for saving. */
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STR X0, [X1]
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/* Switch to use the ELx stack pointer. */
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MSR SPSEL, #1
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.endm
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; /**********************************************************************/
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.macro portRESTORE_CONTEXT
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/* Switch to use the EL0 stack pointer. */
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MSR SPSEL, #0
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/* Set the SP to point to the stack of the task being restored. */
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LDR X0, pxCurrentTCBConst
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LDR X1, [X0]
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LDR X0, [X1]
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MOV SP, X0
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LDP X2, X3, [SP], #0x10 /* Critical nesting and FPU context. */
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/* Set the PMR register to be correct for the current critical nesting
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depth. */
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LDR X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */
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MOV X1, #255 /* X1 holds the unmask value. */
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LDR X4, ullICCPMRConst /* X4 holds the address of the ICCPMR constant. */
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CMP X3, #0
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LDR X5, [X4] /* X5 holds the address of the ICCPMR register. */
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B.EQ 1f
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LDR X6, ullMaxAPIPriorityMaskConst
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LDR X1, [X6] /* X1 holds the mask value. */
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1:
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STR W1, [X5] /* Write the mask value to ICCPMR. */
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DSB SY /* _RB_Barriers probably not required here. */
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ISB SY
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STR X3, [X0] /* Restore the task's critical nesting count. */
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/* Restore the FPU context indicator. */
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LDR X0, ullPortTaskHasFPUContextConst
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STR X2, [X0]
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/* Restore the FPU context, if any. */
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CMP X2, #0
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B.EQ 1f
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LDP Q30, Q31, [SP], #0x20
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LDP Q28, Q29, [SP], #0x20
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LDP Q26, Q27, [SP], #0x20
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LDP Q24, Q25, [SP], #0x20
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LDP Q22, Q23, [SP], #0x20
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LDP Q20, Q21, [SP], #0x20
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LDP Q18, Q19, [SP], #0x20
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LDP Q16, Q17, [SP], #0x20
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LDP Q14, Q15, [SP], #0x20
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LDP Q12, Q13, [SP], #0x20
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LDP Q10, Q11, [SP], #0x20
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LDP Q8, Q9, [SP], #0x20
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LDP Q6, Q7, [SP], #0x20
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LDP Q4, Q5, [SP], #0x20
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LDP Q2, Q3, [SP], #0x20
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LDP Q0, Q1, [SP], #0x20
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1:
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LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */
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#if defined( GUEST )
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/* Restore the SPSR. */
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MSR SPSR_EL1, X3
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/* Restore the ELR. */
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MSR ELR_EL1, X2
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#else
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/* Restore the SPSR. */
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MSR SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */
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/* Restore the ELR. */
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MSR ELR_EL3, X2
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#endif
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LDP X30, XZR, [SP], #0x10
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LDP X28, X29, [SP], #0x10
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LDP X26, X27, [SP], #0x10
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LDP X24, X25, [SP], #0x10
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LDP X22, X23, [SP], #0x10
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LDP X20, X21, [SP], #0x10
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LDP X18, X19, [SP], #0x10
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LDP X16, X17, [SP], #0x10
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LDP X14, X15, [SP], #0x10
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LDP X12, X13, [SP], #0x10
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LDP X10, X11, [SP], #0x10
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LDP X8, X9, [SP], #0x10
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LDP X6, X7, [SP], #0x10
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LDP X4, X5, [SP], #0x10
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LDP X2, X3, [SP], #0x10
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LDP X0, X1, [SP], #0x10
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/* Switch to use the ELx stack pointer. _RB_ Might not be required. */
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MSR SPSEL, #1
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ERET
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.endm
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/******************************************************************************
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* FreeRTOS_SWI_Handler handler is used to perform a context switch.
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*****************************************************************************/
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.align 8
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.type FreeRTOS_SWI_Handler, %function
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FreeRTOS_SWI_Handler:
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/* Save the context of the current task and select a new task to run. */
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portSAVE_CONTEXT
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#if defined( GUEST )
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MRS X0, ESR_EL1
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#else
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MRS X0, ESR_EL3
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#endif
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LSR X1, X0, #26
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#if defined( GUEST )
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CMP X1, #0x15 /* 0x15 = SVC instruction. */
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#else
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CMP X1, #0x17 /* 0x17 = SMC instruction. */
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#endif
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B.NE FreeRTOS_Abort
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BL vTaskSwitchContext
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portRESTORE_CONTEXT
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FreeRTOS_Abort:
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/* Full ESR is in X0, exception class code is in X1. */
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B .
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/******************************************************************************
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* vPortRestoreTaskContext is used to start the scheduler.
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*****************************************************************************/
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.align 8
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.type vPortRestoreTaskContext, %function
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vPortRestoreTaskContext:
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.set freertos_vector_base, _freertos_vector_table
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/* Install the FreeRTOS interrupt handlers. */
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LDR X1, =freertos_vector_base
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#if defined( GUEST )
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MSR VBAR_EL1, X1
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#else
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MSR VBAR_EL3, X1
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#endif
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DSB SY
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ISB SY
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/* Start the first task. */
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portRESTORE_CONTEXT
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/******************************************************************************
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* FreeRTOS_IRQ_Handler handles IRQ entry and exit.
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*****************************************************************************/
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.align 8
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.type FreeRTOS_IRQ_Handler, %function
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FreeRTOS_IRQ_Handler:
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/* Save volatile registers. */
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STP X0, X1, [SP, #-0x10]!
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STP X2, X3, [SP, #-0x10]!
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STP X4, X5, [SP, #-0x10]!
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STP X6, X7, [SP, #-0x10]!
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STP X8, X9, [SP, #-0x10]!
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STP X10, X11, [SP, #-0x10]!
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STP X12, X13, [SP, #-0x10]!
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STP X14, X15, [SP, #-0x10]!
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STP X16, X17, [SP, #-0x10]!
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STP X18, X19, [SP, #-0x10]!
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STP X29, X30, [SP, #-0x10]!
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/* Save the SPSR and ELR. */
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#if defined( GUEST )
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MRS X3, SPSR_EL1
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MRS X2, ELR_EL1
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#else
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MRS X3, SPSR_EL3
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MRS X2, ELR_EL3
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#endif
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STP X2, X3, [SP, #-0x10]!
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/* Increment the interrupt nesting counter. */
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LDR X5, ullPortInterruptNestingConst
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LDR X1, [X5] /* Old nesting count in X1. */
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ADD X6, X1, #1
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STR X6, [X5] /* Address of nesting count variable in X5. */
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/* Maintain the interrupt nesting information across the function call. */
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STP X1, X5, [SP, #-0x10]!
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/* Read value from the interrupt acknowledge register, which is stored in W0
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for future parameter and interrupt clearing use. */
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LDR X2, ullICCIARConst
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LDR X3, [X2]
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LDR W0, [X3] /* ICCIAR in W0 as parameter. */
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/* Maintain the ICCIAR value across the function call. */
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STP X0, X1, [SP, #-0x10]!
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/* Call the C handler. */
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BL vApplicationIRQHandler
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/* Disable interrupts. */
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MSR DAIFSET, #2
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DSB SY
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ISB SY
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/* Restore the ICCIAR value. */
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LDP X0, X1, [SP], #0x10
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/* End IRQ processing by writing ICCIAR to the EOI register. */
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LDR X4, ullICCEOIRConst
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LDR X4, [X4]
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STR W0, [X4]
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/* Restore the critical nesting count. */
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LDP X1, X5, [SP], #0x10
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STR X1, [X5]
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/* Has interrupt nesting unwound? */
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CMP X1, #0
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B.NE Exit_IRQ_No_Context_Switch
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/* Is a context switch required? */
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LDR X0, ullPortYieldRequiredConst
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LDR X1, [X0]
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CMP X1, #0
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B.EQ Exit_IRQ_No_Context_Switch
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/* Reset ullPortYieldRequired to 0. */
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MOV X2, #0
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STR X2, [X0]
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/* Restore volatile registers. */
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LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
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#if defined( GUEST )
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MSR SPSR_EL1, X5
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MSR ELR_EL1, X4
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#else
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MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
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MSR ELR_EL3, X4
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#endif
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DSB SY
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ISB SY
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LDP X29, X30, [SP], #0x10
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LDP X18, X19, [SP], #0x10
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LDP X16, X17, [SP], #0x10
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LDP X14, X15, [SP], #0x10
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LDP X12, X13, [SP], #0x10
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LDP X10, X11, [SP], #0x10
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LDP X8, X9, [SP], #0x10
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LDP X6, X7, [SP], #0x10
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LDP X4, X5, [SP], #0x10
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LDP X2, X3, [SP], #0x10
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LDP X0, X1, [SP], #0x10
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/* Save the context of the current task and select a new task to run. */
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portSAVE_CONTEXT
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BL vTaskSwitchContext
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portRESTORE_CONTEXT
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Exit_IRQ_No_Context_Switch:
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/* Restore volatile registers. */
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LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
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#if defined( GUEST )
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MSR SPSR_EL1, X5
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MSR ELR_EL1, X4
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#else
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MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
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MSR ELR_EL3, X4
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#endif
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DSB SY
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ISB SY
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LDP X29, X30, [SP], #0x10
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LDP X18, X19, [SP], #0x10
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LDP X16, X17, [SP], #0x10
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LDP X14, X15, [SP], #0x10
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LDP X12, X13, [SP], #0x10
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LDP X10, X11, [SP], #0x10
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LDP X8, X9, [SP], #0x10
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LDP X6, X7, [SP], #0x10
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LDP X4, X5, [SP], #0x10
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LDP X2, X3, [SP], #0x10
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LDP X0, X1, [SP], #0x10
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ERET
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.align 8
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pxCurrentTCBConst: .dword pxCurrentTCB
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ullCriticalNestingConst: .dword ullCriticalNesting
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ullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext
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ullICCPMRConst: .dword ullICCPMR
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ullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask
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ullPortInterruptNestingConst: .dword ullPortInterruptNesting
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ullPortYieldRequiredConst: .dword ullPortYieldRequired
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ullICCIARConst: .dword ullICCIAR
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ullICCEOIRConst: .dword ullICCEOIR
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vApplicationIRQHandlerConst: .word vApplicationIRQHandler
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.end
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* https://www.FreeRTOS.org
|
||||
* https://github.com/FreeRTOS
|
||||
*
|
||||
*/
|
||||
|
||||
.text
|
||||
|
||||
/* Variables and functions. */
|
||||
.extern ullMaxAPIPriorityMask
|
||||
.extern pxCurrentTCB
|
||||
.extern vTaskSwitchContext
|
||||
.extern vApplicationIRQHandler
|
||||
.extern ullPortInterruptNesting
|
||||
.extern ullPortTaskHasFPUContext
|
||||
.extern ullCriticalNesting
|
||||
.extern ullPortYieldRequired
|
||||
.extern ullICCEOIR
|
||||
.extern ullICCIAR
|
||||
.extern _freertos_vector_table
|
||||
|
||||
.global FreeRTOS_IRQ_Handler
|
||||
.global FreeRTOS_SWI_Handler
|
||||
.global vPortRestoreTaskContext
|
||||
|
||||
|
||||
.macro portSAVE_CONTEXT
|
||||
|
||||
/* Switch to use the EL0 stack pointer. */
|
||||
MSR SPSEL, #0
|
||||
|
||||
/* Save the entire context. */
|
||||
STP X0, X1, [SP, #-0x10]!
|
||||
STP X2, X3, [SP, #-0x10]!
|
||||
STP X4, X5, [SP, #-0x10]!
|
||||
STP X6, X7, [SP, #-0x10]!
|
||||
STP X8, X9, [SP, #-0x10]!
|
||||
STP X10, X11, [SP, #-0x10]!
|
||||
STP X12, X13, [SP, #-0x10]!
|
||||
STP X14, X15, [SP, #-0x10]!
|
||||
STP X16, X17, [SP, #-0x10]!
|
||||
STP X18, X19, [SP, #-0x10]!
|
||||
STP X20, X21, [SP, #-0x10]!
|
||||
STP X22, X23, [SP, #-0x10]!
|
||||
STP X24, X25, [SP, #-0x10]!
|
||||
STP X26, X27, [SP, #-0x10]!
|
||||
STP X28, X29, [SP, #-0x10]!
|
||||
STP X30, XZR, [SP, #-0x10]!
|
||||
|
||||
/* Save the SPSR. */
|
||||
#if defined( GUEST )
|
||||
MRS X3, SPSR_EL1
|
||||
MRS X2, ELR_EL1
|
||||
#else
|
||||
MRS X3, SPSR_EL3
|
||||
/* Save the ELR. */
|
||||
MRS X2, ELR_EL3
|
||||
#endif
|
||||
|
||||
STP X2, X3, [SP, #-0x10]!
|
||||
|
||||
/* Save the critical section nesting depth. */
|
||||
LDR X0, ullCriticalNestingConst
|
||||
LDR X3, [X0]
|
||||
|
||||
/* Save the FPU context indicator. */
|
||||
LDR X0, ullPortTaskHasFPUContextConst
|
||||
LDR X2, [X0]
|
||||
|
||||
/* Save the FPU context, if any (32 128-bit registers). */
|
||||
CMP X2, #0
|
||||
B.EQ 1f
|
||||
STP Q0, Q1, [SP,#-0x20]!
|
||||
STP Q2, Q3, [SP,#-0x20]!
|
||||
STP Q4, Q5, [SP,#-0x20]!
|
||||
STP Q6, Q7, [SP,#-0x20]!
|
||||
STP Q8, Q9, [SP,#-0x20]!
|
||||
STP Q10, Q11, [SP,#-0x20]!
|
||||
STP Q12, Q13, [SP,#-0x20]!
|
||||
STP Q14, Q15, [SP,#-0x20]!
|
||||
STP Q16, Q17, [SP,#-0x20]!
|
||||
STP Q18, Q19, [SP,#-0x20]!
|
||||
STP Q20, Q21, [SP,#-0x20]!
|
||||
STP Q22, Q23, [SP,#-0x20]!
|
||||
STP Q24, Q25, [SP,#-0x20]!
|
||||
STP Q26, Q27, [SP,#-0x20]!
|
||||
STP Q28, Q29, [SP,#-0x20]!
|
||||
STP Q30, Q31, [SP,#-0x20]!
|
||||
|
||||
1:
|
||||
/* Store the critical nesting count and FPU context indicator. */
|
||||
STP X2, X3, [SP, #-0x10]!
|
||||
|
||||
LDR X0, pxCurrentTCBConst
|
||||
LDR X1, [X0]
|
||||
MOV X0, SP /* Move SP into X0 for saving. */
|
||||
STR X0, [X1]
|
||||
|
||||
/* Switch to use the ELx stack pointer. */
|
||||
MSR SPSEL, #1
|
||||
|
||||
.endm
|
||||
|
||||
; /**********************************************************************/
|
||||
|
||||
.macro portRESTORE_CONTEXT
|
||||
|
||||
/* Switch to use the EL0 stack pointer. */
|
||||
MSR SPSEL, #0
|
||||
|
||||
/* Set the SP to point to the stack of the task being restored. */
|
||||
LDR X0, pxCurrentTCBConst
|
||||
LDR X1, [X0]
|
||||
LDR X0, [X1]
|
||||
MOV SP, X0
|
||||
|
||||
LDP X2, X3, [SP], #0x10 /* Critical nesting and FPU context. */
|
||||
|
||||
/* Set the PMR register to be correct for the current critical nesting
|
||||
depth. */
|
||||
LDR X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */
|
||||
MOV X1, #255 /* X1 holds the unmask value. */
|
||||
LDR X4, ullICCPMRConst /* X4 holds the address of the ICCPMR constant. */
|
||||
CMP X3, #0
|
||||
LDR X5, [X4] /* X5 holds the address of the ICCPMR register. */
|
||||
B.EQ 1f
|
||||
LDR X6, ullMaxAPIPriorityMaskConst
|
||||
LDR X1, [X6] /* X1 holds the mask value. */
|
||||
1:
|
||||
STR W1, [X5] /* Write the mask value to ICCPMR. */
|
||||
DSB SY /* _RB_Barriers probably not required here. */
|
||||
ISB SY
|
||||
STR X3, [X0] /* Restore the task's critical nesting count. */
|
||||
|
||||
/* Restore the FPU context indicator. */
|
||||
LDR X0, ullPortTaskHasFPUContextConst
|
||||
STR X2, [X0]
|
||||
|
||||
/* Restore the FPU context, if any. */
|
||||
CMP X2, #0
|
||||
B.EQ 1f
|
||||
LDP Q30, Q31, [SP], #0x20
|
||||
LDP Q28, Q29, [SP], #0x20
|
||||
LDP Q26, Q27, [SP], #0x20
|
||||
LDP Q24, Q25, [SP], #0x20
|
||||
LDP Q22, Q23, [SP], #0x20
|
||||
LDP Q20, Q21, [SP], #0x20
|
||||
LDP Q18, Q19, [SP], #0x20
|
||||
LDP Q16, Q17, [SP], #0x20
|
||||
LDP Q14, Q15, [SP], #0x20
|
||||
LDP Q12, Q13, [SP], #0x20
|
||||
LDP Q10, Q11, [SP], #0x20
|
||||
LDP Q8, Q9, [SP], #0x20
|
||||
LDP Q6, Q7, [SP], #0x20
|
||||
LDP Q4, Q5, [SP], #0x20
|
||||
LDP Q2, Q3, [SP], #0x20
|
||||
LDP Q0, Q1, [SP], #0x20
|
||||
1:
|
||||
LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */
|
||||
|
||||
#if defined( GUEST )
|
||||
/* Restore the SPSR. */
|
||||
MSR SPSR_EL1, X3
|
||||
/* Restore the ELR. */
|
||||
MSR ELR_EL1, X2
|
||||
#else
|
||||
/* Restore the SPSR. */
|
||||
MSR SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */
|
||||
/* Restore the ELR. */
|
||||
MSR ELR_EL3, X2
|
||||
#endif
|
||||
|
||||
LDP X30, XZR, [SP], #0x10
|
||||
LDP X28, X29, [SP], #0x10
|
||||
LDP X26, X27, [SP], #0x10
|
||||
LDP X24, X25, [SP], #0x10
|
||||
LDP X22, X23, [SP], #0x10
|
||||
LDP X20, X21, [SP], #0x10
|
||||
LDP X18, X19, [SP], #0x10
|
||||
LDP X16, X17, [SP], #0x10
|
||||
LDP X14, X15, [SP], #0x10
|
||||
LDP X12, X13, [SP], #0x10
|
||||
LDP X10, X11, [SP], #0x10
|
||||
LDP X8, X9, [SP], #0x10
|
||||
LDP X6, X7, [SP], #0x10
|
||||
LDP X4, X5, [SP], #0x10
|
||||
LDP X2, X3, [SP], #0x10
|
||||
LDP X0, X1, [SP], #0x10
|
||||
|
||||
/* Switch to use the ELx stack pointer. _RB_ Might not be required. */
|
||||
MSR SPSEL, #1
|
||||
|
||||
ERET
|
||||
|
||||
.endm
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* FreeRTOS_SWI_Handler handler is used to perform a context switch.
|
||||
*****************************************************************************/
|
||||
.align 8
|
||||
.type FreeRTOS_SWI_Handler, %function
|
||||
FreeRTOS_SWI_Handler:
|
||||
/* Save the context of the current task and select a new task to run. */
|
||||
portSAVE_CONTEXT
|
||||
#if defined( GUEST )
|
||||
MRS X0, ESR_EL1
|
||||
#else
|
||||
MRS X0, ESR_EL3
|
||||
#endif
|
||||
|
||||
LSR X1, X0, #26
|
||||
|
||||
#if defined( GUEST )
|
||||
CMP X1, #0x15 /* 0x15 = SVC instruction. */
|
||||
#else
|
||||
CMP X1, #0x17 /* 0x17 = SMC instruction. */
|
||||
#endif
|
||||
B.NE FreeRTOS_Abort
|
||||
BL vTaskSwitchContext
|
||||
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
FreeRTOS_Abort:
|
||||
/* Full ESR is in X0, exception class code is in X1. */
|
||||
B .
|
||||
|
||||
/******************************************************************************
|
||||
* vPortRestoreTaskContext is used to start the scheduler.
|
||||
*****************************************************************************/
|
||||
.align 8
|
||||
.type vPortRestoreTaskContext, %function
|
||||
vPortRestoreTaskContext:
|
||||
.set freertos_vector_base, _freertos_vector_table
|
||||
|
||||
/* Install the FreeRTOS interrupt handlers. */
|
||||
LDR X1, =freertos_vector_base
|
||||
#if defined( GUEST )
|
||||
MSR VBAR_EL1, X1
|
||||
#else
|
||||
MSR VBAR_EL3, X1
|
||||
#endif
|
||||
DSB SY
|
||||
ISB SY
|
||||
|
||||
/* Start the first task. */
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* FreeRTOS_IRQ_Handler handles IRQ entry and exit.
|
||||
*****************************************************************************/
|
||||
.align 8
|
||||
.type FreeRTOS_IRQ_Handler, %function
|
||||
FreeRTOS_IRQ_Handler:
|
||||
/* Save volatile registers. */
|
||||
STP X0, X1, [SP, #-0x10]!
|
||||
STP X2, X3, [SP, #-0x10]!
|
||||
STP X4, X5, [SP, #-0x10]!
|
||||
STP X6, X7, [SP, #-0x10]!
|
||||
STP X8, X9, [SP, #-0x10]!
|
||||
STP X10, X11, [SP, #-0x10]!
|
||||
STP X12, X13, [SP, #-0x10]!
|
||||
STP X14, X15, [SP, #-0x10]!
|
||||
STP X16, X17, [SP, #-0x10]!
|
||||
STP X18, X19, [SP, #-0x10]!
|
||||
STP X29, X30, [SP, #-0x10]!
|
||||
|
||||
/* Save the SPSR and ELR. */
|
||||
#if defined( GUEST )
|
||||
MRS X3, SPSR_EL1
|
||||
MRS X2, ELR_EL1
|
||||
#else
|
||||
MRS X3, SPSR_EL3
|
||||
MRS X2, ELR_EL3
|
||||
#endif
|
||||
STP X2, X3, [SP, #-0x10]!
|
||||
|
||||
/* Increment the interrupt nesting counter. */
|
||||
LDR X5, ullPortInterruptNestingConst
|
||||
LDR X1, [X5] /* Old nesting count in X1. */
|
||||
ADD X6, X1, #1
|
||||
STR X6, [X5] /* Address of nesting count variable in X5. */
|
||||
|
||||
/* Maintain the interrupt nesting information across the function call. */
|
||||
STP X1, X5, [SP, #-0x10]!
|
||||
|
||||
/* Read value from the interrupt acknowledge register, which is stored in W0
|
||||
for future parameter and interrupt clearing use. */
|
||||
LDR X2, ullICCIARConst
|
||||
LDR X3, [X2]
|
||||
LDR W0, [X3] /* ICCIAR in W0 as parameter. */
|
||||
|
||||
/* Maintain the ICCIAR value across the function call. */
|
||||
STP X0, X1, [SP, #-0x10]!
|
||||
|
||||
/* Call the C handler. */
|
||||
BL vApplicationIRQHandler
|
||||
|
||||
/* Disable interrupts. */
|
||||
MSR DAIFSET, #2
|
||||
DSB SY
|
||||
ISB SY
|
||||
|
||||
/* Restore the ICCIAR value. */
|
||||
LDP X0, X1, [SP], #0x10
|
||||
|
||||
/* End IRQ processing by writing ICCIAR to the EOI register. */
|
||||
LDR X4, ullICCEOIRConst
|
||||
LDR X4, [X4]
|
||||
STR W0, [X4]
|
||||
|
||||
/* Restore the critical nesting count. */
|
||||
LDP X1, X5, [SP], #0x10
|
||||
STR X1, [X5]
|
||||
|
||||
/* Has interrupt nesting unwound? */
|
||||
CMP X1, #0
|
||||
B.NE Exit_IRQ_No_Context_Switch
|
||||
|
||||
/* Is a context switch required? */
|
||||
LDR X0, ullPortYieldRequiredConst
|
||||
LDR X1, [X0]
|
||||
CMP X1, #0
|
||||
B.EQ Exit_IRQ_No_Context_Switch
|
||||
|
||||
/* Reset ullPortYieldRequired to 0. */
|
||||
MOV X2, #0
|
||||
STR X2, [X0]
|
||||
|
||||
/* Restore volatile registers. */
|
||||
LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
|
||||
#if defined( GUEST )
|
||||
MSR SPSR_EL1, X5
|
||||
MSR ELR_EL1, X4
|
||||
#else
|
||||
MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
|
||||
MSR ELR_EL3, X4
|
||||
#endif
|
||||
DSB SY
|
||||
ISB SY
|
||||
|
||||
LDP X29, X30, [SP], #0x10
|
||||
LDP X18, X19, [SP], #0x10
|
||||
LDP X16, X17, [SP], #0x10
|
||||
LDP X14, X15, [SP], #0x10
|
||||
LDP X12, X13, [SP], #0x10
|
||||
LDP X10, X11, [SP], #0x10
|
||||
LDP X8, X9, [SP], #0x10
|
||||
LDP X6, X7, [SP], #0x10
|
||||
LDP X4, X5, [SP], #0x10
|
||||
LDP X2, X3, [SP], #0x10
|
||||
LDP X0, X1, [SP], #0x10
|
||||
|
||||
/* Save the context of the current task and select a new task to run. */
|
||||
portSAVE_CONTEXT
|
||||
BL vTaskSwitchContext
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
Exit_IRQ_No_Context_Switch:
|
||||
/* Restore volatile registers. */
|
||||
LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
|
||||
#if defined( GUEST )
|
||||
MSR SPSR_EL1, X5
|
||||
MSR ELR_EL1, X4
|
||||
#else
|
||||
MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
|
||||
MSR ELR_EL3, X4
|
||||
#endif
|
||||
DSB SY
|
||||
ISB SY
|
||||
|
||||
LDP X29, X30, [SP], #0x10
|
||||
LDP X18, X19, [SP], #0x10
|
||||
LDP X16, X17, [SP], #0x10
|
||||
LDP X14, X15, [SP], #0x10
|
||||
LDP X12, X13, [SP], #0x10
|
||||
LDP X10, X11, [SP], #0x10
|
||||
LDP X8, X9, [SP], #0x10
|
||||
LDP X6, X7, [SP], #0x10
|
||||
LDP X4, X5, [SP], #0x10
|
||||
LDP X2, X3, [SP], #0x10
|
||||
LDP X0, X1, [SP], #0x10
|
||||
|
||||
ERET
|
||||
|
||||
|
||||
|
||||
|
||||
.align 8
|
||||
pxCurrentTCBConst: .dword pxCurrentTCB
|
||||
ullCriticalNestingConst: .dword ullCriticalNesting
|
||||
ullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext
|
||||
|
||||
ullICCPMRConst: .dword ullICCPMR
|
||||
ullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask
|
||||
ullPortInterruptNestingConst: .dword ullPortInterruptNesting
|
||||
ullPortYieldRequiredConst: .dword ullPortYieldRequired
|
||||
ullICCIARConst: .dword ullICCIAR
|
||||
ullICCEOIRConst: .dword ullICCEOIR
|
||||
vApplicationIRQHandlerConst: .word vApplicationIRQHandler
|
||||
|
||||
|
||||
|
||||
.end
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue