mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-01 08:54:14 -04:00
Normalize line endings and whitespace in source files
This commit is contained in:
Paul Bartell
Paul Bartell
parent
151fb04ad1
commit
01820d3ed9
574 changed files with 162626 additions and 172362 deletions
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@ -1,227 +1,226 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
|
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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||||
*
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||||
* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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#ifndef PORTMACRO_H
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#define PORTMACRO_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*-----------------------------------------------------------
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* Port specific definitions.
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*
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* The settings in this file configure FreeRTOS correctly for the
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||||
* given hardware and compiler.
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*
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* These settings should not be altered.
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*-----------------------------------------------------------
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*/
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/* Type definitions. */
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#define portCHAR char
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#define portFLOAT float
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#define portDOUBLE double
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#define portLONG long
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#define portSHORT short
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#define portSTACK_TYPE uint32_t
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#define portBASE_TYPE portLONG
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typedef portSTACK_TYPE StackType_t;
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typedef long BaseType_t;
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typedef unsigned long UBaseType_t;
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#if( configUSE_16_BIT_TICKS == 1 )
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typedef uint16_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffff
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#else
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typedef uint32_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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#endif
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/*-----------------------------------------------------------*/
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/* Architecture specifics. */
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#define portSTACK_GROWTH ( -1 )
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#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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#define portBYTE_ALIGNMENT 8
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#define portNOP() __asm volatile ( "NOP" );
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/*-----------------------------------------------------------*/
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/* Scheduler utilities. */
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/*
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* portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
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* and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
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* are included here for efficiency. An attempt to call one from
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* THUMB mode code will result in a compile time error.
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*/
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#define portRESTORE_CONTEXT() \
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{ \
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extern volatile void * volatile pxCurrentTCB; \
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extern volatile uint32_t ulCriticalNesting; \
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\
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/* Set the LR to the task stack. */ \
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__asm volatile ( \
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"LDR R0, =pxCurrentTCB \n\t" \
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"LDR R0, [R0] \n\t" \
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"LDR LR, [R0] \n\t" \
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\
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/* The critical nesting depth is the first item on the stack. */ \
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/* Load it into the ulCriticalNesting variable. */ \
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"LDR R0, =ulCriticalNesting \n\t" \
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"LDMFD LR!, {R1} \n\t" \
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"STR R1, [R0] \n\t" \
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\
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/* Get the SPSR from the stack. */ \
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"LDMFD LR!, {R0} \n\t" \
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"MSR SPSR, R0 \n\t" \
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\
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/* Restore all system mode registers for the task. */ \
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"LDMFD LR, {R0-R14}^ \n\t" \
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"NOP \n\t" \
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\
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/* Restore the return address. */ \
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"LDR LR, [LR, #+60] \n\t" \
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\
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/* And return - correcting the offset in the LR to obtain the */ \
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/* correct address. */ \
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"SUBS PC, LR, #4 \n\t" \
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); \
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( void ) ulCriticalNesting; \
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( void ) pxCurrentTCB; \
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}
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/*-----------------------------------------------------------*/
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#define portSAVE_CONTEXT() \
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{ \
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extern volatile void * volatile pxCurrentTCB; \
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extern volatile uint32_t ulCriticalNesting; \
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\
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/* Push R0 as we are going to use the register. */ \
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__asm volatile ( \
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"STMDB SP!, {R0} \n\t" \
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\
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/* Set R0 to point to the task stack pointer. */ \
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"STMDB SP,{SP}^ \n\t" \
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"NOP \n\t" \
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"SUB SP, SP, #4 \n\t" \
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"LDMIA SP!,{R0} \n\t" \
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\
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/* Push the return address onto the stack. */ \
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"STMDB R0!, {LR} \n\t" \
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\
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/* Now we have saved LR we can use it instead of R0. */ \
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"MOV LR, R0 \n\t" \
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\
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/* Pop R0 so we can save it onto the system mode stack. */ \
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"LDMIA SP!, {R0} \n\t" \
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\
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/* Push all the system mode registers onto the task stack. */ \
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"STMDB LR,{R0-LR}^ \n\t" \
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"NOP \n\t" \
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"SUB LR, LR, #60 \n\t" \
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\
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/* Push the SPSR onto the task stack. */ \
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"MRS R0, SPSR \n\t" \
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"STMDB LR!, {R0} \n\t" \
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\
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"LDR R0, =ulCriticalNesting \n\t" \
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"LDR R0, [R0] \n\t" \
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"STMDB LR!, {R0} \n\t" \
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\
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/* Store the new top of stack for the task. */ \
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"LDR R0, =pxCurrentTCB \n\t" \
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"LDR R0, [R0] \n\t" \
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"STR LR, [R0] \n\t" \
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); \
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( void ) ulCriticalNesting; \
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( void ) pxCurrentTCB; \
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}
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extern void vTaskSwitchContext( void );
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#define portYIELD_FROM_ISR() vTaskSwitchContext()
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#define portYIELD() __asm volatile ( "SWI 0" )
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/*-----------------------------------------------------------*/
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/* Critical section management. */
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/*
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* The interrupt management utilities can only be called from ARM mode. When
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* THUMB_INTERWORK is defined the utilities are defined as functions in
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* portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not
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* defined then the utilities are defined as macros here - as per other ports.
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*/
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#ifdef THUMB_INTERWORK
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extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
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extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
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#define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
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#define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
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#else
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#define portDISABLE_INTERRUPTS() \
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__asm volatile ( \
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"STMDB SP!, {R0} \n\t" /* Push R0. */ \
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"MRS R0, CPSR \n\t" /* Get CPSR. */ \
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"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
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"MSR CPSR, R0 \n\t" /* Write back modified value. */ \
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"LDMIA SP!, {R0} " ) /* Pop R0. */
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#define portENABLE_INTERRUPTS() \
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__asm volatile ( \
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"STMDB SP!, {R0} \n\t" /* Push R0. */ \
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"MRS R0, CPSR \n\t" /* Get CPSR. */ \
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"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
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"MSR CPSR, R0 \n\t" /* Write back modified value. */ \
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"LDMIA SP!, {R0} " ) /* Pop R0. */
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#endif /* THUMB_INTERWORK */
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extern void vPortEnterCritical( void );
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extern void vPortExitCritical( void );
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#define portENTER_CRITICAL() vPortEnterCritical();
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#define portEXIT_CRITICAL() vPortExitCritical();
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/*-----------------------------------------------------------*/
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/* Task function macros as described on the FreeRTOS.org WEB site. */
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#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
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#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
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#ifdef __cplusplus
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}
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#endif
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#endif /* PORTMACRO_H */
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
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*
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||||
* SPDX-License-Identifier: MIT
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||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
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||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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#ifndef PORTMACRO_H
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#define PORTMACRO_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*-----------------------------------------------------------
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* Port specific definitions.
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*
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* The settings in this file configure FreeRTOS correctly for the
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* given hardware and compiler.
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*
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* These settings should not be altered.
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*-----------------------------------------------------------
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*/
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/* Type definitions. */
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#define portCHAR char
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#define portFLOAT float
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#define portDOUBLE double
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#define portLONG long
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#define portSHORT short
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#define portSTACK_TYPE uint32_t
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#define portBASE_TYPE portLONG
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typedef portSTACK_TYPE StackType_t;
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typedef long BaseType_t;
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typedef unsigned long UBaseType_t;
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#if( configUSE_16_BIT_TICKS == 1 )
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typedef uint16_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffff
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#else
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typedef uint32_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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#endif
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/*-----------------------------------------------------------*/
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/* Architecture specifics. */
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#define portSTACK_GROWTH ( -1 )
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#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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#define portBYTE_ALIGNMENT 8
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#define portNOP() __asm volatile ( "NOP" );
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/*-----------------------------------------------------------*/
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/* Scheduler utilities. */
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|
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/*
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* portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
|
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* and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
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* are included here for efficiency. An attempt to call one from
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* THUMB mode code will result in a compile time error.
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*/
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#define portRESTORE_CONTEXT() \
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{ \
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extern volatile void * volatile pxCurrentTCB; \
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extern volatile uint32_t ulCriticalNesting; \
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\
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/* Set the LR to the task stack. */ \
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__asm volatile ( \
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"LDR R0, =pxCurrentTCB \n\t" \
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"LDR R0, [R0] \n\t" \
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"LDR LR, [R0] \n\t" \
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\
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/* The critical nesting depth is the first item on the stack. */ \
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/* Load it into the ulCriticalNesting variable. */ \
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"LDR R0, =ulCriticalNesting \n\t" \
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"LDMFD LR!, {R1} \n\t" \
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"STR R1, [R0] \n\t" \
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\
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/* Get the SPSR from the stack. */ \
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"LDMFD LR!, {R0} \n\t" \
|
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"MSR SPSR, R0 \n\t" \
|
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\
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/* Restore all system mode registers for the task. */ \
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"LDMFD LR, {R0-R14}^ \n\t" \
|
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"NOP \n\t" \
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\
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/* Restore the return address. */ \
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"LDR LR, [LR, #+60] \n\t" \
|
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\
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/* And return - correcting the offset in the LR to obtain the */ \
|
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/* correct address. */ \
|
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"SUBS PC, LR, #4 \n\t" \
|
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); \
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( void ) ulCriticalNesting; \
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( void ) pxCurrentTCB; \
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}
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/*-----------------------------------------------------------*/
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#define portSAVE_CONTEXT() \
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{ \
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extern volatile void * volatile pxCurrentTCB; \
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extern volatile uint32_t ulCriticalNesting; \
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\
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/* Push R0 as we are going to use the register. */ \
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__asm volatile ( \
|
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"STMDB SP!, {R0} \n\t" \
|
||||
\
|
||||
/* Set R0 to point to the task stack pointer. */ \
|
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"STMDB SP,{SP}^ \n\t" \
|
||||
"NOP \n\t" \
|
||||
"SUB SP, SP, #4 \n\t" \
|
||||
"LDMIA SP!,{R0} \n\t" \
|
||||
\
|
||||
/* Push the return address onto the stack. */ \
|
||||
"STMDB R0!, {LR} \n\t" \
|
||||
\
|
||||
/* Now we have saved LR we can use it instead of R0. */ \
|
||||
"MOV LR, R0 \n\t" \
|
||||
\
|
||||
/* Pop R0 so we can save it onto the system mode stack. */ \
|
||||
"LDMIA SP!, {R0} \n\t" \
|
||||
\
|
||||
/* Push all the system mode registers onto the task stack. */ \
|
||||
"STMDB LR,{R0-LR}^ \n\t" \
|
||||
"NOP \n\t" \
|
||||
"SUB LR, LR, #60 \n\t" \
|
||||
\
|
||||
/* Push the SPSR onto the task stack. */ \
|
||||
"MRS R0, SPSR \n\t" \
|
||||
"STMDB LR!, {R0} \n\t" \
|
||||
\
|
||||
"LDR R0, =ulCriticalNesting \n\t" \
|
||||
"LDR R0, [R0] \n\t" \
|
||||
"STMDB LR!, {R0} \n\t" \
|
||||
\
|
||||
/* Store the new top of stack for the task. */ \
|
||||
"LDR R0, =pxCurrentTCB \n\t" \
|
||||
"LDR R0, [R0] \n\t" \
|
||||
"STR LR, [R0] \n\t" \
|
||||
); \
|
||||
( void ) ulCriticalNesting; \
|
||||
( void ) pxCurrentTCB; \
|
||||
}
|
||||
|
||||
extern void vTaskSwitchContext( void );
|
||||
#define portYIELD_FROM_ISR() vTaskSwitchContext()
|
||||
#define portYIELD() __asm volatile ( "SWI 0" )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
/* Critical section management. */
|
||||
|
||||
/*
|
||||
* The interrupt management utilities can only be called from ARM mode. When
|
||||
* THUMB_INTERWORK is defined the utilities are defined as functions in
|
||||
* portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not
|
||||
* defined then the utilities are defined as macros here - as per other ports.
|
||||
*/
|
||||
|
||||
#ifdef THUMB_INTERWORK
|
||||
|
||||
extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
|
||||
extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
|
||||
|
||||
#define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
|
||||
#define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
|
||||
|
||||
#else
|
||||
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
__asm volatile ( \
|
||||
"STMDB SP!, {R0} \n\t" /* Push R0. */ \
|
||||
"MRS R0, CPSR \n\t" /* Get CPSR. */ \
|
||||
"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
|
||||
"MSR CPSR, R0 \n\t" /* Write back modified value. */ \
|
||||
"LDMIA SP!, {R0} " ) /* Pop R0. */
|
||||
|
||||
#define portENABLE_INTERRUPTS() \
|
||||
__asm volatile ( \
|
||||
"STMDB SP!, {R0} \n\t" /* Push R0. */ \
|
||||
"MRS R0, CPSR \n\t" /* Get CPSR. */ \
|
||||
"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
|
||||
"MSR CPSR, R0 \n\t" /* Write back modified value. */ \
|
||||
"LDMIA SP!, {R0} " ) /* Pop R0. */
|
||||
|
||||
#endif /* THUMB_INTERWORK */
|
||||
|
||||
extern void vPortEnterCritical( void );
|
||||
extern void vPortExitCritical( void );
|
||||
|
||||
#define portENTER_CRITICAL() vPortEnterCritical();
|
||||
#define portEXIT_CRITICAL() vPortExitCritical();
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue