mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-20 01:58:32 -04:00
Update to V4.3.0 as described in http://www.FreeRTOS.org/History.txt
This commit is contained in:
Richard Barry
parent
67d0d1ec3b
commit
017740b75a
352 changed files with 71690 additions and 71398 deletions
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@ -1,46 +1,46 @@
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/*
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* These files are taken from the MCF523X source code example package
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* which is available on the Freescale website. Freescale explicitly
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* grants the redistribution and modification of these source files.
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* The complete licensing information is available in the file
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* LICENSE_FREESCALE.TXT.
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*
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* File: mcf523x.h
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* Purpose: Register and bit definitions for the MCF523X
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*
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* Notes:
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*
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*/
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#ifndef __MCF523X_H__
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#define __MCF523X_H__
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/*********************************************************************/
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#include "mcf523x/mcf523x_fec.h"
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#include "mcf523x/mcf523x_rng.h"
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#include "mcf523x/mcf523x_fmpll.h"
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#include "mcf523x/mcf523x_cs.h"
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#include "mcf523x/mcf523x_intc0.h"
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#include "mcf523x/mcf523x_intc1.h"
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#include "mcf523x/mcf523x_sdramc.h"
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#include "mcf523x/mcf523x_sram.h"
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#include "mcf523x/mcf523x_uart.h"
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#include "mcf523x/mcf523x_timer.h"
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#include "mcf523x/mcf523x_qspi.h"
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#include "mcf523x/mcf523x_eport.h"
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#include "mcf523x/mcf523x_i2c.h"
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#include "mcf523x/mcf523x_scm.h"
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#include "mcf523x/mcf523x_pit.h"
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#include "mcf523x/mcf523x_can.h"
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#include "mcf523x/mcf523x_wtm.h"
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#include "mcf523x/mcf523x_gpio.h"
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#include "mcf523x/mcf523x_mdha.h"
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#include "mcf523x/mcf523x_ccm.h"
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#include "mcf523x/mcf523x_rcm.h"
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#include "mcf523x/mcf523x_etpu.h"
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/********************************************************************/
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#endif /* __MCF523X_H__ */
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/*
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* These files are taken from the MCF523X source code example package
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* which is available on the Freescale website. Freescale explicitly
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* grants the redistribution and modification of these source files.
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* The complete licensing information is available in the file
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* LICENSE_FREESCALE.TXT.
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*
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* File: mcf523x.h
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* Purpose: Register and bit definitions for the MCF523X
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*
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* Notes:
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*
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*/
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#ifndef __MCF523X_H__
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#define __MCF523X_H__
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/*********************************************************************/
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#include "mcf523x/mcf523x_fec.h"
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#include "mcf523x/mcf523x_rng.h"
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#include "mcf523x/mcf523x_fmpll.h"
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#include "mcf523x/mcf523x_cs.h"
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#include "mcf523x/mcf523x_intc0.h"
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#include "mcf523x/mcf523x_intc1.h"
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#include "mcf523x/mcf523x_sdramc.h"
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#include "mcf523x/mcf523x_sram.h"
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#include "mcf523x/mcf523x_uart.h"
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#include "mcf523x/mcf523x_timer.h"
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#include "mcf523x/mcf523x_qspi.h"
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#include "mcf523x/mcf523x_eport.h"
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#include "mcf523x/mcf523x_i2c.h"
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#include "mcf523x/mcf523x_scm.h"
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#include "mcf523x/mcf523x_pit.h"
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#include "mcf523x/mcf523x_can.h"
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#include "mcf523x/mcf523x_wtm.h"
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#include "mcf523x/mcf523x_gpio.h"
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#include "mcf523x/mcf523x_mdha.h"
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#include "mcf523x/mcf523x_ccm.h"
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#include "mcf523x/mcf523x_rcm.h"
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#include "mcf523x/mcf523x_etpu.h"
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/********************************************************************/
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#endif /* __MCF523X_H__ */
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@ -1,325 +1,325 @@
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/*
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* These files are taken from the MCF523X source code example package
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* which is available on the Freescale website. Freescale explicitly
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* grants the redistribution and modification of these source files.
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* The complete licensing information is available in the file
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* LICENSE_FREESCALE.TXT.
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*
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* File: mcf523x_can.h
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* Purpose: Register and bit definitions for the MCF523X
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*
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* Notes:
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*
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*/
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#ifndef __MCF523X_CAN_H__
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#define __MCF523X_CAN_H__
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/*********************************************************************
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*
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* FlexCAN Module (CAN)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_CAN_CANMCR0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0000]))
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#define MCF_CAN_CANCTRL0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0004]))
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#define MCF_CAN_TIMER0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0008]))
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#define MCF_CAN_RXGMASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0010]))
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#define MCF_CAN_RX14MASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0014]))
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#define MCF_CAN_RX15MASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0018]))
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#define MCF_CAN_ERRCNT0 (*(vuint32*)(void*)(&__IPSBAR[0x1C001C]))
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#define MCF_CAN_ERRSTAT0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0020]))
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#define MCF_CAN_IMASK0 (*(vuint16*)(void*)(&__IPSBAR[0x1C002A]))
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#define MCF_CAN_IFLAG0 (*(vuint16*)(void*)(&__IPSBAR[0x1C0032]))
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#define MCF_CAN_CANMCR1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0000]))
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#define MCF_CAN_CANCTRL1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0004]))
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#define MCF_CAN_TIMER1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0008]))
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#define MCF_CAN_RXGMASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0010]))
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#define MCF_CAN_RX14MASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0014]))
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#define MCF_CAN_RX15MASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0018]))
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#define MCF_CAN_ERRCNT1 (*(vuint32*)(void*)(&__IPSBAR[0x1F001C]))
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#define MCF_CAN_ERRSTAT1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0020]))
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#define MCF_CAN_IMASK1 (*(vuint16*)(void*)(&__IPSBAR[0x1F002A]))
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#define MCF_CAN_IFLAG1 (*(vuint16*)(void*)(&__IPSBAR[0x1F0032]))
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#define MCF_CAN_CANMCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0000+((x)*0x30000)]))
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#define MCF_CAN_CANCTRL(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0004+((x)*0x30000)]))
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#define MCF_CAN_TIMER(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0008+((x)*0x30000)]))
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#define MCF_CAN_RXGMASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0010+((x)*0x30000)]))
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#define MCF_CAN_RX14MASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0014+((x)*0x30000)]))
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#define MCF_CAN_RX15MASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0018+((x)*0x30000)]))
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#define MCF_CAN_ERRCNT(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C001C+((x)*0x30000)]))
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#define MCF_CAN_ERRSTAT(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0020+((x)*0x30000)]))
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#define MCF_CAN_IMASK(x) (*(vuint16*)(void*)(&__IPSBAR[0x1C002A+((x)*0x30000)]))
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#define MCF_CAN_IFLAG(x) (*(vuint16*)(void*)(&__IPSBAR[0x1C0032+((x)*0x30000)]))
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#define MCF_CAN_MBUF0_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0080+((x)*0x30000)]))
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#define MCF_CAN_MBUF0_TMSTP(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0082+((x)*0x30000)]))
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#define MCF_CAN_MBUF0_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0084+((x)*0x30000)]))
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#define MCF_CAN_MBUF0_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)]))
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#define MCF_CAN_MBUF0_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0089+((x)*0x30000)]))
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#define MCF_CAN_MBUF0_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008A+((x)*0x30000)]))
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#define MCF_CAN_MBUF0_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008B+((x)*0x30000)]))
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#define MCF_CAN_MBUF0_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)]))
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#define MCF_CAN_MBUF0_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008D+((x)*0x30000)]))
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#define MCF_CAN_MBUF0_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008E+((x)*0x30000)]))
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#define MCF_CAN_MBUF0_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008F+((x)*0x30000)]))
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#define MCF_CAN_MBUF1_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0090+((x)*0x30000)]))
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#define MCF_CAN_MBUF1_TMSTP(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0092+((x)*0x30000)]))
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#define MCF_CAN_MBUF1_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0094+((x)*0x30000)]))
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#define MCF_CAN_MBUF1_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)]))
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#define MCF_CAN_MBUF1_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0099+((x)*0x30000)]))
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#define MCF_CAN_MBUF1_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009A+((x)*0x30000)]))
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#define MCF_CAN_MBUF1_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009B+((x)*0x30000)]))
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#define MCF_CAN_MBUF1_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)]))
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#define MCF_CAN_MBUF1_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009D+((x)*0x30000)]))
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#define MCF_CAN_MBUF1_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009E+((x)*0x30000)]))
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#define MCF_CAN_MBUF1_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009F+((x)*0x30000)]))
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#define MCF_CAN_MBUF2_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00A0+((x)*0x30000)]))
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#define MCF_CAN_MBUF2_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A4+((x)*0x30000)]))
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#define MCF_CAN_MBUF2_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)]))
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#define MCF_CAN_MBUF2_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00A9+((x)*0x30000)]))
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#define MCF_CAN_MBUF2_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AA+((x)*0x30000)]))
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#define MCF_CAN_MBUF2_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AB+((x)*0x30000)]))
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#define MCF_CAN_MBUF2_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)]))
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#define MCF_CAN_MBUF2_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AD+((x)*0x30000)]))
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#define MCF_CAN_MBUF2_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AE+((x)*0x30000)]))
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#define MCF_CAN_MBUF2_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AF+((x)*0x30000)]))
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#define MCF_CAN_MBUF3_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00B0+((x)*0x30000)]))
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#define MCF_CAN_MBUF3_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00B4+((x)*0x30000)]))
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#define MCF_CAN_MBUF3_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00B8+((x)*0x30000)]))
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#define MCF_CAN_MBUF3_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00B9+((x)*0x30000)]))
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#define MCF_CAN_MBUF3_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BA+((x)*0x30000)]))
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#define MCF_CAN_MBUF3_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BB+((x)*0x30000)]))
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#define MCF_CAN_MBUF3_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BC+((x)*0x30000)]))
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#define MCF_CAN_MBUF3_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BD+((x)*0x30000)]))
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#define MCF_CAN_MBUF3_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BE+((x)*0x30000)]))
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#define MCF_CAN_MBUF3_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BF+((x)*0x30000)]))
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#define MCF_CAN_MBUF4_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00C0+((x)*0x30000)]))
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#define MCF_CAN_MBUF4_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00C4+((x)*0x30000)]))
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#define MCF_CAN_MBUF4_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00C8+((x)*0x30000)]))
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#define MCF_CAN_MBUF4_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00C9+((x)*0x30000)]))
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#define MCF_CAN_MBUF4_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CA+((x)*0x30000)]))
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#define MCF_CAN_MBUF4_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CB+((x)*0x30000)]))
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#define MCF_CAN_MBUF4_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CC+((x)*0x30000)]))
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#define MCF_CAN_MBUF4_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CD+((x)*0x30000)]))
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#define MCF_CAN_MBUF4_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CE+((x)*0x30000)]))
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#define MCF_CAN_MBUF4_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CF+((x)*0x30000)]))
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#define MCF_CAN_MBUF5_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00D0+((x)*0x30000)]))
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#define MCF_CAN_MBUF5_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00D4+((x)*0x30000)]))
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#define MCF_CAN_MBUF5_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00D8+((x)*0x30000)]))
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#define MCF_CAN_MBUF5_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00D9+((x)*0x30000)]))
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#define MCF_CAN_MBUF5_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DA+((x)*0x30000)]))
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#define MCF_CAN_MBUF5_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DB+((x)*0x30000)]))
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#define MCF_CAN_MBUF5_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DC+((x)*0x30000)]))
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#define MCF_CAN_MBUF5_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DD+((x)*0x30000)]))
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#define MCF_CAN_MBUF5_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DE+((x)*0x30000)]))
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#define MCF_CAN_MBUF5_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DF+((x)*0x30000)]))
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#define MCF_CAN_MBUF6_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00E0+((x)*0x30000)]))
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#define MCF_CAN_MBUF6_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00E4+((x)*0x30000)]))
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#define MCF_CAN_MBUF6_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00E8+((x)*0x30000)]))
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#define MCF_CAN_MBUF6_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00E9+((x)*0x30000)]))
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#define MCF_CAN_MBUF6_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EA+((x)*0x30000)]))
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#define MCF_CAN_MBUF6_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EB+((x)*0x30000)]))
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#define MCF_CAN_MBUF6_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EC+((x)*0x30000)]))
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#define MCF_CAN_MBUF6_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00ED+((x)*0x30000)]))
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#define MCF_CAN_MBUF6_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EE+((x)*0x30000)]))
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#define MCF_CAN_MBUF6_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EF+((x)*0x30000)]))
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#define MCF_CAN_MBUF7_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00F0+((x)*0x30000)]))
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#define MCF_CAN_MBUF7_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00F4+((x)*0x30000)]))
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#define MCF_CAN_MBUF7_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00F8+((x)*0x30000)]))
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#define MCF_CAN_MBUF7_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00F9+((x)*0x30000)]))
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#define MCF_CAN_MBUF7_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FA+((x)*0x30000)]))
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#define MCF_CAN_MBUF7_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FB+((x)*0x30000)]))
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#define MCF_CAN_MBUF7_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FC+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FD+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FE+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FF+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0104+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0108+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0109+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0114+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0118+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0119+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0120+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0124+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0128+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0129+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0130+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0134+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0138+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0139+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0140+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0144+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0148+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0149+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0150+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0154+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0158+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0159+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0160+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0164+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0168+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0169+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0170+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0174+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0178+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0179+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017F+((x)*0x30000)]))
|
||||
|
||||
|
||||
#define MCF_CAN_MBUF0_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_CANMCR */
|
||||
#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0)
|
||||
#define MCF_CAN_CANMCR_SUPV (0x00800000)
|
||||
#define MCF_CAN_CANMCR_FRZACK (0x01000000)
|
||||
#define MCF_CAN_CANMCR_SOFTRST (0x02000000)
|
||||
#define MCF_CAN_CANMCR_HALT (0x10000000)
|
||||
#define MCF_CAN_CANMCR_FRZ (0x40000000)
|
||||
#define MCF_CAN_CANMCR_MDIS (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_CANCTRL */
|
||||
#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0)
|
||||
#define MCF_CAN_CANCTRL_LOM (0x00000008)
|
||||
#define MCF_CAN_CANCTRL_LBUF (0x00000010)
|
||||
#define MCF_CAN_CANCTRL_TSYNC (0x00000020)
|
||||
#define MCF_CAN_CANCTRL_BOFFREC (0x00000040)
|
||||
#define MCF_CAN_CANCTRL_SAMP (0x00000080)
|
||||
#define MCF_CAN_CANCTRL_LPB (0x00001000)
|
||||
#define MCF_CAN_CANCTRL_CLKSRC (0x00002000)
|
||||
#define MCF_CAN_CANCTRL_ERRMSK (0x00004000)
|
||||
#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000)
|
||||
#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16)
|
||||
#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19)
|
||||
#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22)
|
||||
#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_TIMER */
|
||||
#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_RXGMASK */
|
||||
#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_RX14MASK */
|
||||
#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_RX15MASK */
|
||||
#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_ERRCNT */
|
||||
#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0)
|
||||
#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_ERRSTAT */
|
||||
#define MCF_CAN_ERRSTAT_WAKINT (0x00000001)
|
||||
#define MCF_CAN_ERRSTAT_ERRINT (0x00000002)
|
||||
#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004)
|
||||
#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4)
|
||||
#define MCF_CAN_ERRSTAT_TXRX (0x00000040)
|
||||
#define MCF_CAN_ERRSTAT_IDLE (0x00000080)
|
||||
#define MCF_CAN_ERRSTAT_RXWRN (0x00000100)
|
||||
#define MCF_CAN_ERRSTAT_TXWRN (0x00000200)
|
||||
#define MCF_CAN_ERRSTAT_STFERR (0x00000400)
|
||||
#define MCF_CAN_ERRSTAT_FRMERR (0x00000800)
|
||||
#define MCF_CAN_ERRSTAT_CRCERR (0x00001000)
|
||||
#define MCF_CAN_ERRSTAT_ACKERR (0x00002000)
|
||||
#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14)
|
||||
#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000)
|
||||
#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010)
|
||||
#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_IMASK */
|
||||
#define MCF_CAN_IMASK_BUF0M (0x0001)
|
||||
#define MCF_CAN_IMASK_BUF1M (0x0002)
|
||||
#define MCF_CAN_IMASK_BUF2M (0x0004)
|
||||
#define MCF_CAN_IMASK_BUF3M (0x0008)
|
||||
#define MCF_CAN_IMASK_BUF4M (0x0010)
|
||||
#define MCF_CAN_IMASK_BUF5M (0x0020)
|
||||
#define MCF_CAN_IMASK_BUF6M (0x0040)
|
||||
#define MCF_CAN_IMASK_BUF7M (0x0080)
|
||||
#define MCF_CAN_IMASK_BUF8M (0x0100)
|
||||
#define MCF_CAN_IMASK_BUF9M (0x0200)
|
||||
#define MCF_CAN_IMASK_BUF10M (0x0400)
|
||||
#define MCF_CAN_IMASK_BUF11M (0x0800)
|
||||
#define MCF_CAN_IMASK_BUF12M (0x1000)
|
||||
#define MCF_CAN_IMASK_BUF13M (0x2000)
|
||||
#define MCF_CAN_IMASK_BUF14M (0x4000)
|
||||
#define MCF_CAN_IMASK_BUF15M (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_IFLAG */
|
||||
#define MCF_CAN_IFLAG_BUF0I (0x0001)
|
||||
#define MCF_CAN_IFLAG_BUF1I (0x0002)
|
||||
#define MCF_CAN_IFLAG_BUF2I (0x0004)
|
||||
#define MCF_CAN_IFLAG_BUF3I (0x0008)
|
||||
#define MCF_CAN_IFLAG_BUF4I (0x0010)
|
||||
#define MCF_CAN_IFLAG_BUF5I (0x0020)
|
||||
#define MCF_CAN_IFLAG_BUF6I (0x0040)
|
||||
#define MCF_CAN_IFLAG_BUF7I (0x0080)
|
||||
#define MCF_CAN_IFLAG_BUF8I (0x0100)
|
||||
#define MCF_CAN_IFLAG_BUF9I (0x0200)
|
||||
#define MCF_CAN_IFLAG_BUF10I (0x0400)
|
||||
#define MCF_CAN_IFLAG_BUF11I (0x0800)
|
||||
#define MCF_CAN_IFLAG_BUF12I (0x1000)
|
||||
#define MCF_CAN_IFLAG_BUF13I (0x2000)
|
||||
#define MCF_CAN_IFLAG_BUF14I (0x4000)
|
||||
#define MCF_CAN_IFLAG_BUF15I (0x8000)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_CAN_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_can.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_CAN_H__
|
||||
#define __MCF523X_CAN_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* FlexCAN Module (CAN)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CAN_CANMCR0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0000]))
|
||||
#define MCF_CAN_CANCTRL0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0004]))
|
||||
#define MCF_CAN_TIMER0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0008]))
|
||||
#define MCF_CAN_RXGMASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0010]))
|
||||
#define MCF_CAN_RX14MASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0014]))
|
||||
#define MCF_CAN_RX15MASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0018]))
|
||||
#define MCF_CAN_ERRCNT0 (*(vuint32*)(void*)(&__IPSBAR[0x1C001C]))
|
||||
#define MCF_CAN_ERRSTAT0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0020]))
|
||||
#define MCF_CAN_IMASK0 (*(vuint16*)(void*)(&__IPSBAR[0x1C002A]))
|
||||
#define MCF_CAN_IFLAG0 (*(vuint16*)(void*)(&__IPSBAR[0x1C0032]))
|
||||
#define MCF_CAN_CANMCR1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0000]))
|
||||
#define MCF_CAN_CANCTRL1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0004]))
|
||||
#define MCF_CAN_TIMER1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0008]))
|
||||
#define MCF_CAN_RXGMASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0010]))
|
||||
#define MCF_CAN_RX14MASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0014]))
|
||||
#define MCF_CAN_RX15MASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0018]))
|
||||
#define MCF_CAN_ERRCNT1 (*(vuint32*)(void*)(&__IPSBAR[0x1F001C]))
|
||||
#define MCF_CAN_ERRSTAT1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0020]))
|
||||
#define MCF_CAN_IMASK1 (*(vuint16*)(void*)(&__IPSBAR[0x1F002A]))
|
||||
#define MCF_CAN_IFLAG1 (*(vuint16*)(void*)(&__IPSBAR[0x1F0032]))
|
||||
#define MCF_CAN_CANMCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0000+((x)*0x30000)]))
|
||||
#define MCF_CAN_CANCTRL(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0004+((x)*0x30000)]))
|
||||
#define MCF_CAN_TIMER(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0008+((x)*0x30000)]))
|
||||
#define MCF_CAN_RXGMASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0010+((x)*0x30000)]))
|
||||
#define MCF_CAN_RX14MASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0014+((x)*0x30000)]))
|
||||
#define MCF_CAN_RX15MASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0018+((x)*0x30000)]))
|
||||
#define MCF_CAN_ERRCNT(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C001C+((x)*0x30000)]))
|
||||
#define MCF_CAN_ERRSTAT(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0020+((x)*0x30000)]))
|
||||
#define MCF_CAN_IMASK(x) (*(vuint16*)(void*)(&__IPSBAR[0x1C002A+((x)*0x30000)]))
|
||||
#define MCF_CAN_IFLAG(x) (*(vuint16*)(void*)(&__IPSBAR[0x1C0032+((x)*0x30000)]))
|
||||
|
||||
#define MCF_CAN_MBUF0_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0080+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_TMSTP(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0082+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0084+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0089+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0090+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_TMSTP(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0092+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0094+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0099+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00A0+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A4+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00A9+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AA+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AB+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AD+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AE+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AF+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00B0+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00B4+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00B8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00B9+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BA+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BB+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BC+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BD+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BE+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF3_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BF+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00C0+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00C4+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00C8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00C9+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CA+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CB+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CC+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CD+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CE+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF4_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CF+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00D0+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00D4+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00D8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00D9+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DA+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DB+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DC+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DD+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DE+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF5_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DF+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00E0+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00E4+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00E8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00E9+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EA+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EB+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EC+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00ED+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EE+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF6_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EF+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00F0+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00F4+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00F8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00F9+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FA+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FB+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FC+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FD+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FE+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF7_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FF+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0104+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0108+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0109+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF8_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0114+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0118+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0119+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF9_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0120+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0124+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0128+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0129+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF10_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0130+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0134+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0138+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0139+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF11_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0140+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0144+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0148+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0149+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF12_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0150+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0154+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0158+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0159+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF13_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0160+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0164+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0168+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0169+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF14_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016F+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0170+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0174+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0178+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0179+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017A+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017B+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017D+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017E+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF15_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017F+((x)*0x30000)]))
|
||||
|
||||
|
||||
#define MCF_CAN_MBUF0_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF0_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF1_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)]))
|
||||
#define MCF_CAN_MBUF2_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_CANMCR */
|
||||
#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0)
|
||||
#define MCF_CAN_CANMCR_SUPV (0x00800000)
|
||||
#define MCF_CAN_CANMCR_FRZACK (0x01000000)
|
||||
#define MCF_CAN_CANMCR_SOFTRST (0x02000000)
|
||||
#define MCF_CAN_CANMCR_HALT (0x10000000)
|
||||
#define MCF_CAN_CANMCR_FRZ (0x40000000)
|
||||
#define MCF_CAN_CANMCR_MDIS (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_CANCTRL */
|
||||
#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0)
|
||||
#define MCF_CAN_CANCTRL_LOM (0x00000008)
|
||||
#define MCF_CAN_CANCTRL_LBUF (0x00000010)
|
||||
#define MCF_CAN_CANCTRL_TSYNC (0x00000020)
|
||||
#define MCF_CAN_CANCTRL_BOFFREC (0x00000040)
|
||||
#define MCF_CAN_CANCTRL_SAMP (0x00000080)
|
||||
#define MCF_CAN_CANCTRL_LPB (0x00001000)
|
||||
#define MCF_CAN_CANCTRL_CLKSRC (0x00002000)
|
||||
#define MCF_CAN_CANCTRL_ERRMSK (0x00004000)
|
||||
#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000)
|
||||
#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16)
|
||||
#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19)
|
||||
#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22)
|
||||
#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_TIMER */
|
||||
#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_RXGMASK */
|
||||
#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_RX14MASK */
|
||||
#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_RX15MASK */
|
||||
#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_ERRCNT */
|
||||
#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0)
|
||||
#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_ERRSTAT */
|
||||
#define MCF_CAN_ERRSTAT_WAKINT (0x00000001)
|
||||
#define MCF_CAN_ERRSTAT_ERRINT (0x00000002)
|
||||
#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004)
|
||||
#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4)
|
||||
#define MCF_CAN_ERRSTAT_TXRX (0x00000040)
|
||||
#define MCF_CAN_ERRSTAT_IDLE (0x00000080)
|
||||
#define MCF_CAN_ERRSTAT_RXWRN (0x00000100)
|
||||
#define MCF_CAN_ERRSTAT_TXWRN (0x00000200)
|
||||
#define MCF_CAN_ERRSTAT_STFERR (0x00000400)
|
||||
#define MCF_CAN_ERRSTAT_FRMERR (0x00000800)
|
||||
#define MCF_CAN_ERRSTAT_CRCERR (0x00001000)
|
||||
#define MCF_CAN_ERRSTAT_ACKERR (0x00002000)
|
||||
#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14)
|
||||
#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000)
|
||||
#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010)
|
||||
#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_IMASK */
|
||||
#define MCF_CAN_IMASK_BUF0M (0x0001)
|
||||
#define MCF_CAN_IMASK_BUF1M (0x0002)
|
||||
#define MCF_CAN_IMASK_BUF2M (0x0004)
|
||||
#define MCF_CAN_IMASK_BUF3M (0x0008)
|
||||
#define MCF_CAN_IMASK_BUF4M (0x0010)
|
||||
#define MCF_CAN_IMASK_BUF5M (0x0020)
|
||||
#define MCF_CAN_IMASK_BUF6M (0x0040)
|
||||
#define MCF_CAN_IMASK_BUF7M (0x0080)
|
||||
#define MCF_CAN_IMASK_BUF8M (0x0100)
|
||||
#define MCF_CAN_IMASK_BUF9M (0x0200)
|
||||
#define MCF_CAN_IMASK_BUF10M (0x0400)
|
||||
#define MCF_CAN_IMASK_BUF11M (0x0800)
|
||||
#define MCF_CAN_IMASK_BUF12M (0x1000)
|
||||
#define MCF_CAN_IMASK_BUF13M (0x2000)
|
||||
#define MCF_CAN_IMASK_BUF14M (0x4000)
|
||||
#define MCF_CAN_IMASK_BUF15M (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CAN_IFLAG */
|
||||
#define MCF_CAN_IFLAG_BUF0I (0x0001)
|
||||
#define MCF_CAN_IFLAG_BUF1I (0x0002)
|
||||
#define MCF_CAN_IFLAG_BUF2I (0x0004)
|
||||
#define MCF_CAN_IFLAG_BUF3I (0x0008)
|
||||
#define MCF_CAN_IFLAG_BUF4I (0x0010)
|
||||
#define MCF_CAN_IFLAG_BUF5I (0x0020)
|
||||
#define MCF_CAN_IFLAG_BUF6I (0x0040)
|
||||
#define MCF_CAN_IFLAG_BUF7I (0x0080)
|
||||
#define MCF_CAN_IFLAG_BUF8I (0x0100)
|
||||
#define MCF_CAN_IFLAG_BUF9I (0x0200)
|
||||
#define MCF_CAN_IFLAG_BUF10I (0x0400)
|
||||
#define MCF_CAN_IFLAG_BUF11I (0x0800)
|
||||
#define MCF_CAN_IFLAG_BUF12I (0x1000)
|
||||
#define MCF_CAN_IFLAG_BUF13I (0x2000)
|
||||
#define MCF_CAN_IFLAG_BUF14I (0x4000)
|
||||
#define MCF_CAN_IFLAG_BUF15I (0x8000)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_CAN_H__ */
|
||||
|
|
|
|||
|
|
@ -1,56 +1,56 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_ccm.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_CCM_H__
|
||||
#define __MCF523X_CCM_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Chip Configuration Module (CCM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CCM_CCR (*(vuint16*)(void*)(&__IPSBAR[0x110004]))
|
||||
#define MCF_CCM_LPCR (*(vuint8 *)(void*)(&__IPSBAR[0x110007]))
|
||||
#define MCF_CCM_CIR (*(vuint16*)(void*)(&__IPSBAR[0x11000A]))
|
||||
#define MCF_CCM_RCON (*(vuint16*)(void*)(&__IPSBAR[0x110008]))
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_CCR */
|
||||
#define MCF_CCM_CCR_BMT(x) (((x)&0x0007)<<0)
|
||||
#define MCF_CCM_CCR_BME (0x0008)
|
||||
#define MCF_CCM_CCR_SZEN (0x0040)
|
||||
#define MCF_CCM_CCR_MODE(x) (((x)&0x0007)<<8)
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_LPCR */
|
||||
#define MCF_CCM_LPCR_STPMD(x) (((x)&0x03)<<3)
|
||||
#define MCF_CCM_LPCR_LPMD(x) (((x)&0x03)<<6)
|
||||
#define MCF_CCM_LPCR_LPMD_STOP (0xC0)
|
||||
#define MCF_CCM_LPCR_LPMD_WAIT (0x80)
|
||||
#define MCF_CCM_LPCR_LPMD_DOZE (0x40)
|
||||
#define MCF_CCM_LPCR_LPMD_RUN (0x00)
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_CIR */
|
||||
#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0)
|
||||
#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_RCON */
|
||||
#define MCF_CCM_RCON_MODE (0x0001)
|
||||
#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3)
|
||||
#define MCF_CCM_RCON_RLOAD (0x0020)
|
||||
#define MCF_CCM_RCON_RCSC(x) (((x)&0x0003)<<8)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_CCM_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_ccm.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_CCM_H__
|
||||
#define __MCF523X_CCM_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Chip Configuration Module (CCM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CCM_CCR (*(vuint16*)(void*)(&__IPSBAR[0x110004]))
|
||||
#define MCF_CCM_LPCR (*(vuint8 *)(void*)(&__IPSBAR[0x110007]))
|
||||
#define MCF_CCM_CIR (*(vuint16*)(void*)(&__IPSBAR[0x11000A]))
|
||||
#define MCF_CCM_RCON (*(vuint16*)(void*)(&__IPSBAR[0x110008]))
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_CCR */
|
||||
#define MCF_CCM_CCR_BMT(x) (((x)&0x0007)<<0)
|
||||
#define MCF_CCM_CCR_BME (0x0008)
|
||||
#define MCF_CCM_CCR_SZEN (0x0040)
|
||||
#define MCF_CCM_CCR_MODE(x) (((x)&0x0007)<<8)
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_LPCR */
|
||||
#define MCF_CCM_LPCR_STPMD(x) (((x)&0x03)<<3)
|
||||
#define MCF_CCM_LPCR_LPMD(x) (((x)&0x03)<<6)
|
||||
#define MCF_CCM_LPCR_LPMD_STOP (0xC0)
|
||||
#define MCF_CCM_LPCR_LPMD_WAIT (0x80)
|
||||
#define MCF_CCM_LPCR_LPMD_DOZE (0x40)
|
||||
#define MCF_CCM_LPCR_LPMD_RUN (0x00)
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_CIR */
|
||||
#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0)
|
||||
#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_RCON */
|
||||
#define MCF_CCM_RCON_MODE (0x0001)
|
||||
#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3)
|
||||
#define MCF_CCM_RCON_RLOAD (0x0020)
|
||||
#define MCF_CCM_RCON_RCSC(x) (((x)&0x0003)<<8)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_CCM_H__ */
|
||||
|
|
|
|||
|
|
@ -1,101 +1,101 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_cs.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_CS_H__
|
||||
#define __MCF523X_CS_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Chip Selects (CS)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CS_CSAR0 (*(vuint16*)(void*)(&__IPSBAR[0x000080]))
|
||||
#define MCF_CS_CSMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000084]))
|
||||
#define MCF_CS_CSCR0 (*(vuint16*)(void*)(&__IPSBAR[0x00008A]))
|
||||
#define MCF_CS_CSAR1 (*(vuint16*)(void*)(&__IPSBAR[0x00008C]))
|
||||
#define MCF_CS_CSMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000090]))
|
||||
#define MCF_CS_CSCR1 (*(vuint16*)(void*)(&__IPSBAR[0x000096]))
|
||||
#define MCF_CS_CSAR2 (*(vuint16*)(void*)(&__IPSBAR[0x000098]))
|
||||
#define MCF_CS_CSMR2 (*(vuint32*)(void*)(&__IPSBAR[0x00009C]))
|
||||
#define MCF_CS_CSCR2 (*(vuint16*)(void*)(&__IPSBAR[0x0000A2]))
|
||||
#define MCF_CS_CSAR3 (*(vuint16*)(void*)(&__IPSBAR[0x0000A4]))
|
||||
#define MCF_CS_CSMR3 (*(vuint32*)(void*)(&__IPSBAR[0x0000A8]))
|
||||
#define MCF_CS_CSCR3 (*(vuint16*)(void*)(&__IPSBAR[0x0000AE]))
|
||||
#define MCF_CS_CSAR4 (*(vuint16*)(void*)(&__IPSBAR[0x0000B0]))
|
||||
#define MCF_CS_CSMR4 (*(vuint32*)(void*)(&__IPSBAR[0x0000B4]))
|
||||
#define MCF_CS_CSCR4 (*(vuint16*)(void*)(&__IPSBAR[0x0000BA]))
|
||||
#define MCF_CS_CSAR5 (*(vuint16*)(void*)(&__IPSBAR[0x0000BC]))
|
||||
#define MCF_CS_CSMR5 (*(vuint32*)(void*)(&__IPSBAR[0x0000C0]))
|
||||
#define MCF_CS_CSCR5 (*(vuint16*)(void*)(&__IPSBAR[0x0000C6]))
|
||||
#define MCF_CS_CSAR6 (*(vuint16*)(void*)(&__IPSBAR[0x0000C8]))
|
||||
#define MCF_CS_CSMR6 (*(vuint32*)(void*)(&__IPSBAR[0x0000CC]))
|
||||
#define MCF_CS_CSCR6 (*(vuint16*)(void*)(&__IPSBAR[0x0000D2]))
|
||||
#define MCF_CS_CSAR7 (*(vuint16*)(void*)(&__IPSBAR[0x0000D4]))
|
||||
#define MCF_CS_CSMR7 (*(vuint32*)(void*)(&__IPSBAR[0x0000D8]))
|
||||
#define MCF_CS_CSCR7 (*(vuint16*)(void*)(&__IPSBAR[0x0000DE]))
|
||||
#define MCF_CS_CSAR(x) (*(vuint16*)(void*)(&__IPSBAR[0x000080+((x)*0x00C)]))
|
||||
#define MCF_CS_CSMR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000084+((x)*0x00C)]))
|
||||
#define MCF_CS_CSCR(x) (*(vuint16*)(void*)(&__IPSBAR[0x00008A+((x)*0x00C)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_CS_CSAR */
|
||||
#define MCF_CS_CSAR_BA(x) ((uint16)(((x)&0xFFFF0000)>>16))
|
||||
|
||||
/* Bit definitions and macros for MCF_CS_CSMR */
|
||||
#define MCF_CS_CSMR_V (0x00000001)
|
||||
#define MCF_CS_CSMR_UD (0x00000002)
|
||||
#define MCF_CS_CSMR_UC (0x00000004)
|
||||
#define MCF_CS_CSMR_SD (0x00000008)
|
||||
#define MCF_CS_CSMR_SC (0x00000010)
|
||||
#define MCF_CS_CSMR_CI (0x00000020)
|
||||
#define MCF_CS_CSMR_AM (0x00000040)
|
||||
#define MCF_CS_CSMR_WP (0x00000100)
|
||||
#define MCF_CS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16)
|
||||
#define MCF_CS_CSMR_BAM_4G (0xFFFF0000)
|
||||
#define MCF_CS_CSMR_BAM_2G (0x7FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_1G (0x3FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_1024M (0x3FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_512M (0x1FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_256M (0x0FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_128M (0x07FF0000)
|
||||
#define MCF_CS_CSMR_BAM_64M (0x03FF0000)
|
||||
#define MCF_CS_CSMR_BAM_32M (0x01FF0000)
|
||||
#define MCF_CS_CSMR_BAM_16M (0x00FF0000)
|
||||
#define MCF_CS_CSMR_BAM_8M (0x007F0000)
|
||||
#define MCF_CS_CSMR_BAM_4M (0x003F0000)
|
||||
#define MCF_CS_CSMR_BAM_2M (0x001F0000)
|
||||
#define MCF_CS_CSMR_BAM_1M (0x000F0000)
|
||||
#define MCF_CS_CSMR_BAM_1024K (0x000F0000)
|
||||
#define MCF_CS_CSMR_BAM_512K (0x00070000)
|
||||
#define MCF_CS_CSMR_BAM_256K (0x00030000)
|
||||
#define MCF_CS_CSMR_BAM_128K (0x00010000)
|
||||
#define MCF_CS_CSMR_BAM_64K (0x00000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CS_CSCR */
|
||||
#define MCF_CS_CSCR_SWWS(x) (((x)&0x0007)<<0)
|
||||
#define MCF_CS_CSCR_BSTW (0x0008)
|
||||
#define MCF_CS_CSCR_BSTR (0x0010)
|
||||
#define MCF_CS_CSCR_BEM (0x0020)
|
||||
#define MCF_CS_CSCR_PS(x) (((x)&0x0003)<<6)
|
||||
#define MCF_CS_CSCR_AA (0x0100)
|
||||
#define MCF_CS_CSCR_IWS(x) (((x)&0x000F)<<10)
|
||||
#define MCF_CS_CSCR_SRWS(x) (((x)&0x0003)<<14)
|
||||
#define MCF_CS_CSCR_PS_8 (0x0040)
|
||||
#define MCF_CS_CSCR_PS_16 (0x0080)
|
||||
#define MCF_CS_CSCR_PS_32 (0x0000)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_CS_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_cs.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_CS_H__
|
||||
#define __MCF523X_CS_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Chip Selects (CS)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CS_CSAR0 (*(vuint16*)(void*)(&__IPSBAR[0x000080]))
|
||||
#define MCF_CS_CSMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000084]))
|
||||
#define MCF_CS_CSCR0 (*(vuint16*)(void*)(&__IPSBAR[0x00008A]))
|
||||
#define MCF_CS_CSAR1 (*(vuint16*)(void*)(&__IPSBAR[0x00008C]))
|
||||
#define MCF_CS_CSMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000090]))
|
||||
#define MCF_CS_CSCR1 (*(vuint16*)(void*)(&__IPSBAR[0x000096]))
|
||||
#define MCF_CS_CSAR2 (*(vuint16*)(void*)(&__IPSBAR[0x000098]))
|
||||
#define MCF_CS_CSMR2 (*(vuint32*)(void*)(&__IPSBAR[0x00009C]))
|
||||
#define MCF_CS_CSCR2 (*(vuint16*)(void*)(&__IPSBAR[0x0000A2]))
|
||||
#define MCF_CS_CSAR3 (*(vuint16*)(void*)(&__IPSBAR[0x0000A4]))
|
||||
#define MCF_CS_CSMR3 (*(vuint32*)(void*)(&__IPSBAR[0x0000A8]))
|
||||
#define MCF_CS_CSCR3 (*(vuint16*)(void*)(&__IPSBAR[0x0000AE]))
|
||||
#define MCF_CS_CSAR4 (*(vuint16*)(void*)(&__IPSBAR[0x0000B0]))
|
||||
#define MCF_CS_CSMR4 (*(vuint32*)(void*)(&__IPSBAR[0x0000B4]))
|
||||
#define MCF_CS_CSCR4 (*(vuint16*)(void*)(&__IPSBAR[0x0000BA]))
|
||||
#define MCF_CS_CSAR5 (*(vuint16*)(void*)(&__IPSBAR[0x0000BC]))
|
||||
#define MCF_CS_CSMR5 (*(vuint32*)(void*)(&__IPSBAR[0x0000C0]))
|
||||
#define MCF_CS_CSCR5 (*(vuint16*)(void*)(&__IPSBAR[0x0000C6]))
|
||||
#define MCF_CS_CSAR6 (*(vuint16*)(void*)(&__IPSBAR[0x0000C8]))
|
||||
#define MCF_CS_CSMR6 (*(vuint32*)(void*)(&__IPSBAR[0x0000CC]))
|
||||
#define MCF_CS_CSCR6 (*(vuint16*)(void*)(&__IPSBAR[0x0000D2]))
|
||||
#define MCF_CS_CSAR7 (*(vuint16*)(void*)(&__IPSBAR[0x0000D4]))
|
||||
#define MCF_CS_CSMR7 (*(vuint32*)(void*)(&__IPSBAR[0x0000D8]))
|
||||
#define MCF_CS_CSCR7 (*(vuint16*)(void*)(&__IPSBAR[0x0000DE]))
|
||||
#define MCF_CS_CSAR(x) (*(vuint16*)(void*)(&__IPSBAR[0x000080+((x)*0x00C)]))
|
||||
#define MCF_CS_CSMR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000084+((x)*0x00C)]))
|
||||
#define MCF_CS_CSCR(x) (*(vuint16*)(void*)(&__IPSBAR[0x00008A+((x)*0x00C)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_CS_CSAR */
|
||||
#define MCF_CS_CSAR_BA(x) ((uint16)(((x)&0xFFFF0000)>>16))
|
||||
|
||||
/* Bit definitions and macros for MCF_CS_CSMR */
|
||||
#define MCF_CS_CSMR_V (0x00000001)
|
||||
#define MCF_CS_CSMR_UD (0x00000002)
|
||||
#define MCF_CS_CSMR_UC (0x00000004)
|
||||
#define MCF_CS_CSMR_SD (0x00000008)
|
||||
#define MCF_CS_CSMR_SC (0x00000010)
|
||||
#define MCF_CS_CSMR_CI (0x00000020)
|
||||
#define MCF_CS_CSMR_AM (0x00000040)
|
||||
#define MCF_CS_CSMR_WP (0x00000100)
|
||||
#define MCF_CS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16)
|
||||
#define MCF_CS_CSMR_BAM_4G (0xFFFF0000)
|
||||
#define MCF_CS_CSMR_BAM_2G (0x7FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_1G (0x3FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_1024M (0x3FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_512M (0x1FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_256M (0x0FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_128M (0x07FF0000)
|
||||
#define MCF_CS_CSMR_BAM_64M (0x03FF0000)
|
||||
#define MCF_CS_CSMR_BAM_32M (0x01FF0000)
|
||||
#define MCF_CS_CSMR_BAM_16M (0x00FF0000)
|
||||
#define MCF_CS_CSMR_BAM_8M (0x007F0000)
|
||||
#define MCF_CS_CSMR_BAM_4M (0x003F0000)
|
||||
#define MCF_CS_CSMR_BAM_2M (0x001F0000)
|
||||
#define MCF_CS_CSMR_BAM_1M (0x000F0000)
|
||||
#define MCF_CS_CSMR_BAM_1024K (0x000F0000)
|
||||
#define MCF_CS_CSMR_BAM_512K (0x00070000)
|
||||
#define MCF_CS_CSMR_BAM_256K (0x00030000)
|
||||
#define MCF_CS_CSMR_BAM_128K (0x00010000)
|
||||
#define MCF_CS_CSMR_BAM_64K (0x00000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CS_CSCR */
|
||||
#define MCF_CS_CSCR_SWWS(x) (((x)&0x0007)<<0)
|
||||
#define MCF_CS_CSCR_BSTW (0x0008)
|
||||
#define MCF_CS_CSCR_BSTR (0x0010)
|
||||
#define MCF_CS_CSCR_BEM (0x0020)
|
||||
#define MCF_CS_CSCR_PS(x) (((x)&0x0003)<<6)
|
||||
#define MCF_CS_CSCR_AA (0x0100)
|
||||
#define MCF_CS_CSCR_IWS(x) (((x)&0x000F)<<10)
|
||||
#define MCF_CS_CSCR_SRWS(x) (((x)&0x0003)<<14)
|
||||
#define MCF_CS_CSCR_PS_8 (0x0040)
|
||||
#define MCF_CS_CSCR_PS_16 (0x0080)
|
||||
#define MCF_CS_CSCR_PS_32 (0x0000)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_CS_H__ */
|
||||
|
|
|
|||
|
|
@ -1,92 +1,92 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_eport.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_EPORT_H__
|
||||
#define __MCF523X_EPORT_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Edge Port Module (EPORT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_EPORT_EPPAR (*(vuint16*)(void*)(&__IPSBAR[0x130000]))
|
||||
#define MCF_EPORT_EPDDR (*(vuint8 *)(void*)(&__IPSBAR[0x130002]))
|
||||
#define MCF_EPORT_EPIER (*(vuint8 *)(void*)(&__IPSBAR[0x130003]))
|
||||
#define MCF_EPORT_EPDR (*(vuint8 *)(void*)(&__IPSBAR[0x130004]))
|
||||
#define MCF_EPORT_EPPDR (*(vuint8 *)(void*)(&__IPSBAR[0x130005]))
|
||||
#define MCF_EPORT_EPFR (*(vuint8 *)(void*)(&__IPSBAR[0x130006]))
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPAR */
|
||||
#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
|
||||
#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
|
||||
#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
|
||||
#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
|
||||
#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
|
||||
#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
|
||||
#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
|
||||
#define MCF_EPORT_EPPAR_EPPAx_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPAx_RISING (1)
|
||||
#define MCF_EPORT_EPPAR_EPPAx_FALLING (2)
|
||||
#define MCF_EPORT_EPPAR_EPPAx_BOTH (3)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDDR */
|
||||
#define MCF_EPORT_EPDDR_EPDD1 (0x02)
|
||||
#define MCF_EPORT_EPDDR_EPDD2 (0x04)
|
||||
#define MCF_EPORT_EPDDR_EPDD3 (0x08)
|
||||
#define MCF_EPORT_EPDDR_EPDD4 (0x10)
|
||||
#define MCF_EPORT_EPDDR_EPDD5 (0x20)
|
||||
#define MCF_EPORT_EPDDR_EPDD6 (0x40)
|
||||
#define MCF_EPORT_EPDDR_EPDD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPIER */
|
||||
#define MCF_EPORT_EPIER_EPIE1 (0x02)
|
||||
#define MCF_EPORT_EPIER_EPIE2 (0x04)
|
||||
#define MCF_EPORT_EPIER_EPIE3 (0x08)
|
||||
#define MCF_EPORT_EPIER_EPIE4 (0x10)
|
||||
#define MCF_EPORT_EPIER_EPIE5 (0x20)
|
||||
#define MCF_EPORT_EPIER_EPIE6 (0x40)
|
||||
#define MCF_EPORT_EPIER_EPIE7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDR */
|
||||
#define MCF_EPORT_EPDR_EPD1 (0x02)
|
||||
#define MCF_EPORT_EPDR_EPD2 (0x04)
|
||||
#define MCF_EPORT_EPDR_EPD3 (0x08)
|
||||
#define MCF_EPORT_EPDR_EPD4 (0x10)
|
||||
#define MCF_EPORT_EPDR_EPD5 (0x20)
|
||||
#define MCF_EPORT_EPDR_EPD6 (0x40)
|
||||
#define MCF_EPORT_EPDR_EPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPDR */
|
||||
#define MCF_EPORT_EPPDR_EPPD1 (0x02)
|
||||
#define MCF_EPORT_EPPDR_EPPD2 (0x04)
|
||||
#define MCF_EPORT_EPPDR_EPPD3 (0x08)
|
||||
#define MCF_EPORT_EPPDR_EPPD4 (0x10)
|
||||
#define MCF_EPORT_EPPDR_EPPD5 (0x20)
|
||||
#define MCF_EPORT_EPPDR_EPPD6 (0x40)
|
||||
#define MCF_EPORT_EPPDR_EPPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPFR */
|
||||
#define MCF_EPORT_EPFR_EPF1 (0x02)
|
||||
#define MCF_EPORT_EPFR_EPF2 (0x04)
|
||||
#define MCF_EPORT_EPFR_EPF3 (0x08)
|
||||
#define MCF_EPORT_EPFR_EPF4 (0x10)
|
||||
#define MCF_EPORT_EPFR_EPF5 (0x20)
|
||||
#define MCF_EPORT_EPFR_EPF6 (0x40)
|
||||
#define MCF_EPORT_EPFR_EPF7 (0x80)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_EPORT_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_eport.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_EPORT_H__
|
||||
#define __MCF523X_EPORT_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Edge Port Module (EPORT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_EPORT_EPPAR (*(vuint16*)(void*)(&__IPSBAR[0x130000]))
|
||||
#define MCF_EPORT_EPDDR (*(vuint8 *)(void*)(&__IPSBAR[0x130002]))
|
||||
#define MCF_EPORT_EPIER (*(vuint8 *)(void*)(&__IPSBAR[0x130003]))
|
||||
#define MCF_EPORT_EPDR (*(vuint8 *)(void*)(&__IPSBAR[0x130004]))
|
||||
#define MCF_EPORT_EPPDR (*(vuint8 *)(void*)(&__IPSBAR[0x130005]))
|
||||
#define MCF_EPORT_EPFR (*(vuint8 *)(void*)(&__IPSBAR[0x130006]))
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPAR */
|
||||
#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
|
||||
#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
|
||||
#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
|
||||
#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
|
||||
#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
|
||||
#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
|
||||
#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
|
||||
#define MCF_EPORT_EPPAR_EPPAx_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPAx_RISING (1)
|
||||
#define MCF_EPORT_EPPAR_EPPAx_FALLING (2)
|
||||
#define MCF_EPORT_EPPAR_EPPAx_BOTH (3)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDDR */
|
||||
#define MCF_EPORT_EPDDR_EPDD1 (0x02)
|
||||
#define MCF_EPORT_EPDDR_EPDD2 (0x04)
|
||||
#define MCF_EPORT_EPDDR_EPDD3 (0x08)
|
||||
#define MCF_EPORT_EPDDR_EPDD4 (0x10)
|
||||
#define MCF_EPORT_EPDDR_EPDD5 (0x20)
|
||||
#define MCF_EPORT_EPDDR_EPDD6 (0x40)
|
||||
#define MCF_EPORT_EPDDR_EPDD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPIER */
|
||||
#define MCF_EPORT_EPIER_EPIE1 (0x02)
|
||||
#define MCF_EPORT_EPIER_EPIE2 (0x04)
|
||||
#define MCF_EPORT_EPIER_EPIE3 (0x08)
|
||||
#define MCF_EPORT_EPIER_EPIE4 (0x10)
|
||||
#define MCF_EPORT_EPIER_EPIE5 (0x20)
|
||||
#define MCF_EPORT_EPIER_EPIE6 (0x40)
|
||||
#define MCF_EPORT_EPIER_EPIE7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDR */
|
||||
#define MCF_EPORT_EPDR_EPD1 (0x02)
|
||||
#define MCF_EPORT_EPDR_EPD2 (0x04)
|
||||
#define MCF_EPORT_EPDR_EPD3 (0x08)
|
||||
#define MCF_EPORT_EPDR_EPD4 (0x10)
|
||||
#define MCF_EPORT_EPDR_EPD5 (0x20)
|
||||
#define MCF_EPORT_EPDR_EPD6 (0x40)
|
||||
#define MCF_EPORT_EPDR_EPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPDR */
|
||||
#define MCF_EPORT_EPPDR_EPPD1 (0x02)
|
||||
#define MCF_EPORT_EPPDR_EPPD2 (0x04)
|
||||
#define MCF_EPORT_EPPDR_EPPD3 (0x08)
|
||||
#define MCF_EPORT_EPPDR_EPPD4 (0x10)
|
||||
#define MCF_EPORT_EPPDR_EPPD5 (0x20)
|
||||
#define MCF_EPORT_EPPDR_EPPD6 (0x40)
|
||||
#define MCF_EPORT_EPPDR_EPPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPFR */
|
||||
#define MCF_EPORT_EPFR_EPF1 (0x02)
|
||||
#define MCF_EPORT_EPFR_EPF2 (0x04)
|
||||
#define MCF_EPORT_EPFR_EPF3 (0x08)
|
||||
#define MCF_EPORT_EPFR_EPF4 (0x10)
|
||||
#define MCF_EPORT_EPFR_EPF5 (0x20)
|
||||
#define MCF_EPORT_EPFR_EPF6 (0x40)
|
||||
#define MCF_EPORT_EPFR_EPF7 (0x80)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_EPORT_H__ */
|
||||
|
|
|
|||
|
|
@ -1,493 +1,493 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_etpu.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_ETPU_H__
|
||||
#define __MCF523X_ETPU_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* enhanced Time Processor Unit (ETPU)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_ETPU_EMCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0000]))
|
||||
#define MCF_ETPU_ECDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0004]))
|
||||
#define MCF_ETPU_EMISCCR (*(vuint32*)(void*)(&__IPSBAR[0x1D000C]))
|
||||
#define MCF_ETPU_ESCMODR (*(vuint32*)(void*)(&__IPSBAR[0x1D0010]))
|
||||
#define MCF_ETPU_EECR (*(vuint32*)(void*)(&__IPSBAR[0x1D0014]))
|
||||
#define MCF_ETPU_ETBCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0020]))
|
||||
#define MCF_ETPU_ETB1R (*(vuint32*)(void*)(&__IPSBAR[0x1D0024]))
|
||||
#define MCF_ETPU_ETB2R (*(vuint32*)(void*)(&__IPSBAR[0x1D0028]))
|
||||
#define MCF_ETPU_EREDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D002C]))
|
||||
#define MCF_ETPU_ECISR (*(vuint32*)(void*)(&__IPSBAR[0x1D0200]))
|
||||
#define MCF_ETPU_ECDTRSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0210]))
|
||||
#define MCF_ETPU_ECIOSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0220]))
|
||||
#define MCF_ETPU_ECDTROSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0230]))
|
||||
#define MCF_ETPU_ECIER (*(vuint32*)(void*)(&__IPSBAR[0x1D0240]))
|
||||
#define MCF_ETPU_ECDTRER (*(vuint32*)(void*)(&__IPSBAR[0x1D0250]))
|
||||
#define MCF_ETPU_ECPSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0280]))
|
||||
#define MCF_ETPU_ECSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0290]))
|
||||
#define MCF_ETPU_EC0SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0404]))
|
||||
#define MCF_ETPU_EC1SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0414]))
|
||||
#define MCF_ETPU_EC2SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0424]))
|
||||
#define MCF_ETPU_EC3SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0434]))
|
||||
#define MCF_ETPU_EC4SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0444]))
|
||||
#define MCF_ETPU_EC5SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0454]))
|
||||
#define MCF_ETPU_EC6SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0464]))
|
||||
#define MCF_ETPU_EC7SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0474]))
|
||||
#define MCF_ETPU_EC8SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0484]))
|
||||
#define MCF_ETPU_EC9SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0494]))
|
||||
#define MCF_ETPU_EC10SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A4]))
|
||||
#define MCF_ETPU_EC11SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B4]))
|
||||
#define MCF_ETPU_EC12SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C4]))
|
||||
#define MCF_ETPU_EC13SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D4]))
|
||||
#define MCF_ETPU_EC14SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E4]))
|
||||
#define MCF_ETPU_EC15SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F4]))
|
||||
#define MCF_ETPU_EC16SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0504]))
|
||||
#define MCF_ETPU_EC17SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0514]))
|
||||
#define MCF_ETPU_EC18SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0524]))
|
||||
#define MCF_ETPU_EC19SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0534]))
|
||||
#define MCF_ETPU_EC20SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0544]))
|
||||
#define MCF_ETPU_EC21SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0554]))
|
||||
#define MCF_ETPU_EC22SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0564]))
|
||||
#define MCF_ETPU_EC23SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0574]))
|
||||
#define MCF_ETPU_EC24SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0584]))
|
||||
#define MCF_ETPU_EC25SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0594]))
|
||||
#define MCF_ETPU_EC26SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A4]))
|
||||
#define MCF_ETPU_EC27SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B4]))
|
||||
#define MCF_ETPU_EC28SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C4]))
|
||||
#define MCF_ETPU_EC29SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D4]))
|
||||
#define MCF_ETPU_EC30SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E4]))
|
||||
#define MCF_ETPU_EC31SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F4]))
|
||||
#define MCF_ETPU_ECnSCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0404+((x)*0x010)]))
|
||||
#define MCF_ETPU_EC0CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0400]))
|
||||
#define MCF_ETPU_EC1CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0410]))
|
||||
#define MCF_ETPU_EC2CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0420]))
|
||||
#define MCF_ETPU_EC3CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0430]))
|
||||
#define MCF_ETPU_EC4CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0440]))
|
||||
#define MCF_ETPU_EC5CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0450]))
|
||||
#define MCF_ETPU_EC6CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0460]))
|
||||
#define MCF_ETPU_EC7CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0470]))
|
||||
#define MCF_ETPU_EC8CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0480]))
|
||||
#define MCF_ETPU_EC9CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0490]))
|
||||
#define MCF_ETPU_EC10CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A0]))
|
||||
#define MCF_ETPU_EC11CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B0]))
|
||||
#define MCF_ETPU_EC12CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C0]))
|
||||
#define MCF_ETPU_EC13CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D0]))
|
||||
#define MCF_ETPU_EC14CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E0]))
|
||||
#define MCF_ETPU_EC15CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F0]))
|
||||
#define MCF_ETPU_EC16CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0500]))
|
||||
#define MCF_ETPU_EC17CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0510]))
|
||||
#define MCF_ETPU_EC18CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0520]))
|
||||
#define MCF_ETPU_EC19CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0530]))
|
||||
#define MCF_ETPU_EC20CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0540]))
|
||||
#define MCF_ETPU_EC21CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0550]))
|
||||
#define MCF_ETPU_EC22CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0560]))
|
||||
#define MCF_ETPU_EC23CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0570]))
|
||||
#define MCF_ETPU_EC24CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0580]))
|
||||
#define MCF_ETPU_EC25CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0590]))
|
||||
#define MCF_ETPU_EC26CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A0]))
|
||||
#define MCF_ETPU_EC27CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B0]))
|
||||
#define MCF_ETPU_EC28CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C0]))
|
||||
#define MCF_ETPU_EC29CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D0]))
|
||||
#define MCF_ETPU_EC30CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E0]))
|
||||
#define MCF_ETPU_EC31CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F0]))
|
||||
#define MCF_ETPU_ECnCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0400+((x)*0x010)]))
|
||||
#define MCF_ETPU_EC0HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0408]))
|
||||
#define MCF_ETPU_EC1HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0418]))
|
||||
#define MCF_ETPU_EC2HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0428]))
|
||||
#define MCF_ETPU_EC3HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0438]))
|
||||
#define MCF_ETPU_EC4HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0448]))
|
||||
#define MCF_ETPU_EC5HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0458]))
|
||||
#define MCF_ETPU_EC6HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0468]))
|
||||
#define MCF_ETPU_EC7HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0478]))
|
||||
#define MCF_ETPU_EC8HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0488]))
|
||||
#define MCF_ETPU_EC9HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0498]))
|
||||
#define MCF_ETPU_EC10HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A8]))
|
||||
#define MCF_ETPU_EC11HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B8]))
|
||||
#define MCF_ETPU_EC12HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C8]))
|
||||
#define MCF_ETPU_EC13HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D8]))
|
||||
#define MCF_ETPU_EC14HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E8]))
|
||||
#define MCF_ETPU_EC15HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F8]))
|
||||
#define MCF_ETPU_EC16HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0508]))
|
||||
#define MCF_ETPU_EC17HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0518]))
|
||||
#define MCF_ETPU_EC18HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0528]))
|
||||
#define MCF_ETPU_EC19HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0538]))
|
||||
#define MCF_ETPU_EC20HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0548]))
|
||||
#define MCF_ETPU_EC21HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0558]))
|
||||
#define MCF_ETPU_EC22HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0568]))
|
||||
#define MCF_ETPU_EC23HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0578]))
|
||||
#define MCF_ETPU_EC24HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0588]))
|
||||
#define MCF_ETPU_EC25HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0598]))
|
||||
#define MCF_ETPU_EC26HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A8]))
|
||||
#define MCF_ETPU_EC27HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B8]))
|
||||
#define MCF_ETPU_EC28HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C8]))
|
||||
#define MCF_ETPU_EC29HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D8]))
|
||||
#define MCF_ETPU_EC30HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E8]))
|
||||
#define MCF_ETPU_EC31HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F8]))
|
||||
#define MCF_ETPU_ECnHSSR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0408+((x)*0x010)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_EMCR */
|
||||
#define MCF_ETPU_EMCR_GTBE (0x00000001)
|
||||
#define MCF_ETPU_EMCR_VIS (0x00000040)
|
||||
#define MCF_ETPU_EMCR_SCMMISEN (0x00000200)
|
||||
#define MCF_ETPU_EMCR_SCMMISF (0x00000400)
|
||||
#define MCF_ETPU_EMCR_SCMSIZE(x) (((x)&0x0000001F)<<16)
|
||||
#define MCF_ETPU_EMCR_ILF2 (0x01000000)
|
||||
#define MCF_ETPU_EMCR_ILF1 (0x02000000)
|
||||
#define MCF_ETPU_EMCR_MGE2 (0x04000000)
|
||||
#define MCF_ETPU_EMCR_MGE1 (0x08000000)
|
||||
#define MCF_ETPU_EMCR_GEC (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECDCR */
|
||||
#define MCF_ETPU_ECDCR_PARM1(x) (((x)&0x0000007F)<<0)
|
||||
#define MCF_ETPU_ECDCR_WR (0x00000080)
|
||||
#define MCF_ETPU_ECDCR_PARM0(x) (((x)&0x0000007F)<<8)
|
||||
#define MCF_ETPU_ECDCR_PWIDTH (0x00008000)
|
||||
#define MCF_ETPU_ECDCR_PBASE(x) (((x)&0x000003FF)<<16)
|
||||
#define MCF_ETPU_ECDCR_CTBASE(x) (((x)&0x0000001F)<<26)
|
||||
#define MCF_ETPU_ECDCR_STS (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_EECR */
|
||||
#define MCF_ETPU_EECR_ETB(x) (((x)&0x0000001F)<<0)
|
||||
#define MCF_ETPU_EECR_CDFC(x) (((x)&0x00000003)<<14)
|
||||
#define MCF_ETPU_EECR_FPSK(x) (((x)&0x00000007)<<16)
|
||||
#define MCF_ETPU_EECR_HLTF (0x00800000)
|
||||
#define MCF_ETPU_EECR_STF (0x10000000)
|
||||
#define MCF_ETPU_EECR_MDIS (0x40000000)
|
||||
#define MCF_ETPU_EECR_FEND (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ETBCR */
|
||||
#define MCF_ETPU_ETBCR_TCR1P(x) (((x)&0x000000FF)<<0)
|
||||
#define MCF_ETPU_ETBCR_TCR1CTL(x) (((x)&0x00000003)<<14)
|
||||
#define MCF_ETPU_ETBCR_TCR2P(x) (((x)&0x0000003F)<<16)
|
||||
#define MCF_ETPU_ETBCR_AM (0x02000000)
|
||||
#define MCF_ETPU_ETBCR_TCRCF(x) (((x)&0x00000003)<<27)
|
||||
#define MCF_ETPU_ETBCR_TCR2CTL(x) (((x)&0x00000007)<<29)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ETB1R */
|
||||
#define MCF_ETPU_ETB1R_TCR1(x) (((x)&0x00FFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ETB2R */
|
||||
#define MCF_ETPU_ETB2R_TCR2(x) (((x)&0x00FFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_EREDCR */
|
||||
#define MCF_ETPU_EREDCR_SRV2(x) (((x)&0x0000000F)<<0)
|
||||
#define MCF_ETPU_EREDCR_SERVER_ID2(x) (((x)&0x0000000F)<<8)
|
||||
#define MCF_ETPU_EREDCR_RSC2 (0x00004000)
|
||||
#define MCF_ETPU_EREDCR_REN2 (0x00008000)
|
||||
#define MCF_ETPU_EREDCR_SRV1(x) (((x)&0x0000000F)<<16)
|
||||
#define MCF_ETPU_EREDCR_SERVER_ID1(x) (((x)&0x0000000F)<<24)
|
||||
#define MCF_ETPU_EREDCR_RSC1 (0x40000000)
|
||||
#define MCF_ETPU_EREDCR_REN1 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECISR */
|
||||
#define MCF_ETPU_ECISR_CIS0 (0x00000001)
|
||||
#define MCF_ETPU_ECISR_CIS1 (0x00000002)
|
||||
#define MCF_ETPU_ECISR_CIS2 (0x00000004)
|
||||
#define MCF_ETPU_ECISR_CIS3 (0x00000008)
|
||||
#define MCF_ETPU_ECISR_CIS4 (0x00000010)
|
||||
#define MCF_ETPU_ECISR_CIS5 (0x00000020)
|
||||
#define MCF_ETPU_ECISR_CIS6 (0x00000040)
|
||||
#define MCF_ETPU_ECISR_CIS7 (0x00000080)
|
||||
#define MCF_ETPU_ECISR_CIS8 (0x00000100)
|
||||
#define MCF_ETPU_ECISR_CIS9 (0x00000200)
|
||||
#define MCF_ETPU_ECISR_CIS10 (0x00000400)
|
||||
#define MCF_ETPU_ECISR_CIS11 (0x00000800)
|
||||
#define MCF_ETPU_ECISR_CIS12 (0x00001000)
|
||||
#define MCF_ETPU_ECISR_CIS13 (0x00002000)
|
||||
#define MCF_ETPU_ECISR_CIS14 (0x00004000)
|
||||
#define MCF_ETPU_ECISR_CIS15 (0x00008000)
|
||||
#define MCF_ETPU_ECISR_CIS16 (0x00010000)
|
||||
#define MCF_ETPU_ECISR_CIS17 (0x00020000)
|
||||
#define MCF_ETPU_ECISR_CIS18 (0x00040000)
|
||||
#define MCF_ETPU_ECISR_CIS19 (0x00080000)
|
||||
#define MCF_ETPU_ECISR_CIS20 (0x00100000)
|
||||
#define MCF_ETPU_ECISR_CIS21 (0x00200000)
|
||||
#define MCF_ETPU_ECISR_CIS22 (0x00400000)
|
||||
#define MCF_ETPU_ECISR_CIS23 (0x00800000)
|
||||
#define MCF_ETPU_ECISR_CIS24 (0x01000000)
|
||||
#define MCF_ETPU_ECISR_CIS25 (0x02000000)
|
||||
#define MCF_ETPU_ECISR_CIS26 (0x04000000)
|
||||
#define MCF_ETPU_ECISR_CIS27 (0x08000000)
|
||||
#define MCF_ETPU_ECISR_CIS28 (0x10000000)
|
||||
#define MCF_ETPU_ECISR_CIS29 (0x20000000)
|
||||
#define MCF_ETPU_ECISR_CIS30 (0x40000000)
|
||||
#define MCF_ETPU_ECISR_CIS31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECDTRSR */
|
||||
#define MCF_ETPU_ECDTRSR_DTRS0 (0x00000001)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS1 (0x00000002)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS2 (0x00000004)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS3 (0x00000008)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS4 (0x00000010)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS5 (0x00000020)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS6 (0x00000040)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS7 (0x00000080)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS8 (0x00000100)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS9 (0x00000200)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS10 (0x00000400)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS11 (0x00000800)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS12 (0x00001000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS13 (0x00002000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS14 (0x00004000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS15 (0x00008000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS16 (0x00010000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS17 (0x00020000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS18 (0x00040000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS19 (0x00080000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS20 (0x00100000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS21 (0x00200000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS22 (0x00400000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS23 (0x00800000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS24 (0x01000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS25 (0x02000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS26 (0x04000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS27 (0x08000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS28 (0x10000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS29 (0x20000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS30 (0x40000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECIOSR */
|
||||
#define MCF_ETPU_ECIOSR_CIOS0 (0x00000001)
|
||||
#define MCF_ETPU_ECIOSR_CIOS1 (0x00000002)
|
||||
#define MCF_ETPU_ECIOSR_CIOS2 (0x00000004)
|
||||
#define MCF_ETPU_ECIOSR_CIOS3 (0x00000008)
|
||||
#define MCF_ETPU_ECIOSR_CIOS4 (0x00000010)
|
||||
#define MCF_ETPU_ECIOSR_CIOS5 (0x00000020)
|
||||
#define MCF_ETPU_ECIOSR_CIOS6 (0x00000040)
|
||||
#define MCF_ETPU_ECIOSR_CIOS7 (0x00000080)
|
||||
#define MCF_ETPU_ECIOSR_CIOS8 (0x00000100)
|
||||
#define MCF_ETPU_ECIOSR_CIOS9 (0x00000200)
|
||||
#define MCF_ETPU_ECIOSR_CIOS10 (0x00000400)
|
||||
#define MCF_ETPU_ECIOSR_CIOS11 (0x00000800)
|
||||
#define MCF_ETPU_ECIOSR_CIOS12 (0x00001000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS13 (0x00002000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS14 (0x00004000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS15 (0x00008000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS16 (0x00010000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS17 (0x00020000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS18 (0x00040000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS19 (0x00080000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS20 (0x00100000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS21 (0x00200000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS22 (0x00400000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS23 (0x00800000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS24 (0x01000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS25 (0x02000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS26 (0x04000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS27 (0x08000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS28 (0x10000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS29 (0x20000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS30 (0x40000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECDTROSR */
|
||||
#define MCF_ETPU_ECDTROSR_DTROS0 (0x00000001)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS1 (0x00000002)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS2 (0x00000004)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS3 (0x00000008)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS4 (0x00000010)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS5 (0x00000020)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS6 (0x00000040)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS7 (0x00000080)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS8 (0x00000100)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS9 (0x00000200)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS10 (0x00000400)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS11 (0x00000800)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS12 (0x00001000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS13 (0x00002000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS14 (0x00004000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS15 (0x00008000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS16 (0x00010000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS17 (0x00020000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS18 (0x00040000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS19 (0x00080000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS20 (0x00100000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS21 (0x00200000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS22 (0x00400000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS23 (0x00800000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS24 (0x01000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS25 (0x02000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS26 (0x04000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS27 (0x08000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS28 (0x10000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS29 (0x20000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS30 (0x40000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECIER */
|
||||
#define MCF_ETPU_ECIER_CIE0 (0x00000001)
|
||||
#define MCF_ETPU_ECIER_CIE1 (0x00000002)
|
||||
#define MCF_ETPU_ECIER_CIE2 (0x00000004)
|
||||
#define MCF_ETPU_ECIER_CIE3 (0x00000008)
|
||||
#define MCF_ETPU_ECIER_CIE4 (0x00000010)
|
||||
#define MCF_ETPU_ECIER_CIE5 (0x00000020)
|
||||
#define MCF_ETPU_ECIER_CIE6 (0x00000040)
|
||||
#define MCF_ETPU_ECIER_CIE7 (0x00000080)
|
||||
#define MCF_ETPU_ECIER_CIE8 (0x00000100)
|
||||
#define MCF_ETPU_ECIER_CIE9 (0x00000200)
|
||||
#define MCF_ETPU_ECIER_CIE10 (0x00000400)
|
||||
#define MCF_ETPU_ECIER_CIE11 (0x00000800)
|
||||
#define MCF_ETPU_ECIER_CIE12 (0x00001000)
|
||||
#define MCF_ETPU_ECIER_CIE13 (0x00002000)
|
||||
#define MCF_ETPU_ECIER_CIE14 (0x00004000)
|
||||
#define MCF_ETPU_ECIER_CIE15 (0x00008000)
|
||||
#define MCF_ETPU_ECIER_CIE16 (0x00010000)
|
||||
#define MCF_ETPU_ECIER_CIE17 (0x00020000)
|
||||
#define MCF_ETPU_ECIER_CIE18 (0x00040000)
|
||||
#define MCF_ETPU_ECIER_CIE19 (0x00080000)
|
||||
#define MCF_ETPU_ECIER_CIE20 (0x00100000)
|
||||
#define MCF_ETPU_ECIER_CIE21 (0x00200000)
|
||||
#define MCF_ETPU_ECIER_CIE22 (0x00400000)
|
||||
#define MCF_ETPU_ECIER_CIE23 (0x00800000)
|
||||
#define MCF_ETPU_ECIER_CIE24 (0x01000000)
|
||||
#define MCF_ETPU_ECIER_CIE25 (0x02000000)
|
||||
#define MCF_ETPU_ECIER_CIE26 (0x04000000)
|
||||
#define MCF_ETPU_ECIER_CIE27 (0x08000000)
|
||||
#define MCF_ETPU_ECIER_CIE28 (0x10000000)
|
||||
#define MCF_ETPU_ECIER_CIE29 (0x20000000)
|
||||
#define MCF_ETPU_ECIER_CIE30 (0x40000000)
|
||||
#define MCF_ETPU_ECIER_CIE31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECDTRER */
|
||||
#define MCF_ETPU_ECDTRER_DTRE0 (0x00000001)
|
||||
#define MCF_ETPU_ECDTRER_DTRE1 (0x00000002)
|
||||
#define MCF_ETPU_ECDTRER_DTRE2 (0x00000004)
|
||||
#define MCF_ETPU_ECDTRER_DTRE3 (0x00000008)
|
||||
#define MCF_ETPU_ECDTRER_DTRE4 (0x00000010)
|
||||
#define MCF_ETPU_ECDTRER_DTRE5 (0x00000020)
|
||||
#define MCF_ETPU_ECDTRER_DTRE6 (0x00000040)
|
||||
#define MCF_ETPU_ECDTRER_DTRE7 (0x00000080)
|
||||
#define MCF_ETPU_ECDTRER_DTRE8 (0x00000100)
|
||||
#define MCF_ETPU_ECDTRER_DTRE9 (0x00000200)
|
||||
#define MCF_ETPU_ECDTRER_DTRE10 (0x00000400)
|
||||
#define MCF_ETPU_ECDTRER_DTRE11 (0x00000800)
|
||||
#define MCF_ETPU_ECDTRER_DTRE12 (0x00001000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE13 (0x00002000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE14 (0x00004000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE15 (0x00008000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE16 (0x00010000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE17 (0x00020000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE18 (0x00040000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE19 (0x00080000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE20 (0x00100000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE21 (0x00200000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE22 (0x00400000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE23 (0x00800000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE24 (0x01000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE25 (0x02000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE26 (0x04000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE27 (0x08000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE28 (0x10000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE29 (0x20000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE30 (0x40000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECPSSR */
|
||||
#define MCF_ETPU_ECPSSR_SR0 (0x00000001)
|
||||
#define MCF_ETPU_ECPSSR_SR1 (0x00000002)
|
||||
#define MCF_ETPU_ECPSSR_SR2 (0x00000004)
|
||||
#define MCF_ETPU_ECPSSR_SR3 (0x00000008)
|
||||
#define MCF_ETPU_ECPSSR_SR4 (0x00000010)
|
||||
#define MCF_ETPU_ECPSSR_SR5 (0x00000020)
|
||||
#define MCF_ETPU_ECPSSR_SR6 (0x00000040)
|
||||
#define MCF_ETPU_ECPSSR_SR7 (0x00000080)
|
||||
#define MCF_ETPU_ECPSSR_SR8 (0x00000100)
|
||||
#define MCF_ETPU_ECPSSR_SR9 (0x00000200)
|
||||
#define MCF_ETPU_ECPSSR_SR10 (0x00000400)
|
||||
#define MCF_ETPU_ECPSSR_SR11 (0x00000800)
|
||||
#define MCF_ETPU_ECPSSR_SR12 (0x00001000)
|
||||
#define MCF_ETPU_ECPSSR_SR13 (0x00002000)
|
||||
#define MCF_ETPU_ECPSSR_SR14 (0x00004000)
|
||||
#define MCF_ETPU_ECPSSR_SR15 (0x00008000)
|
||||
#define MCF_ETPU_ECPSSR_SR16 (0x00010000)
|
||||
#define MCF_ETPU_ECPSSR_SR17 (0x00020000)
|
||||
#define MCF_ETPU_ECPSSR_SR18 (0x00040000)
|
||||
#define MCF_ETPU_ECPSSR_SR19 (0x00080000)
|
||||
#define MCF_ETPU_ECPSSR_SR20 (0x00100000)
|
||||
#define MCF_ETPU_ECPSSR_SR21 (0x00200000)
|
||||
#define MCF_ETPU_ECPSSR_SR22 (0x00400000)
|
||||
#define MCF_ETPU_ECPSSR_SR23 (0x00800000)
|
||||
#define MCF_ETPU_ECPSSR_SR24 (0x01000000)
|
||||
#define MCF_ETPU_ECPSSR_SR25 (0x02000000)
|
||||
#define MCF_ETPU_ECPSSR_SR26 (0x04000000)
|
||||
#define MCF_ETPU_ECPSSR_SR27 (0x08000000)
|
||||
#define MCF_ETPU_ECPSSR_SR28 (0x10000000)
|
||||
#define MCF_ETPU_ECPSSR_SR29 (0x20000000)
|
||||
#define MCF_ETPU_ECPSSR_SR30 (0x40000000)
|
||||
#define MCF_ETPU_ECPSSR_SR31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECSSR */
|
||||
#define MCF_ETPU_ECSSR_SS0 (0x00000001)
|
||||
#define MCF_ETPU_ECSSR_SS1 (0x00000002)
|
||||
#define MCF_ETPU_ECSSR_SS2 (0x00000004)
|
||||
#define MCF_ETPU_ECSSR_SS3 (0x00000008)
|
||||
#define MCF_ETPU_ECSSR_SS4 (0x00000010)
|
||||
#define MCF_ETPU_ECSSR_SS5 (0x00000020)
|
||||
#define MCF_ETPU_ECSSR_SS6 (0x00000040)
|
||||
#define MCF_ETPU_ECSSR_SS7 (0x00000080)
|
||||
#define MCF_ETPU_ECSSR_SS8 (0x00000100)
|
||||
#define MCF_ETPU_ECSSR_SS9 (0x00000200)
|
||||
#define MCF_ETPU_ECSSR_SS10 (0x00000400)
|
||||
#define MCF_ETPU_ECSSR_SS11 (0x00000800)
|
||||
#define MCF_ETPU_ECSSR_SS12 (0x00001000)
|
||||
#define MCF_ETPU_ECSSR_SS13 (0x00002000)
|
||||
#define MCF_ETPU_ECSSR_SS14 (0x00004000)
|
||||
#define MCF_ETPU_ECSSR_SS15 (0x00008000)
|
||||
#define MCF_ETPU_ECSSR_SS16 (0x00010000)
|
||||
#define MCF_ETPU_ECSSR_SS17 (0x00020000)
|
||||
#define MCF_ETPU_ECSSR_SS18 (0x00040000)
|
||||
#define MCF_ETPU_ECSSR_SS19 (0x00080000)
|
||||
#define MCF_ETPU_ECSSR_SS20 (0x00100000)
|
||||
#define MCF_ETPU_ECSSR_SS21 (0x00200000)
|
||||
#define MCF_ETPU_ECSSR_SS22 (0x00400000)
|
||||
#define MCF_ETPU_ECSSR_SS23 (0x00800000)
|
||||
#define MCF_ETPU_ECSSR_SS24 (0x01000000)
|
||||
#define MCF_ETPU_ECSSR_SS25 (0x02000000)
|
||||
#define MCF_ETPU_ECSSR_SS26 (0x04000000)
|
||||
#define MCF_ETPU_ECSSR_SS27 (0x08000000)
|
||||
#define MCF_ETPU_ECSSR_SS28 (0x10000000)
|
||||
#define MCF_ETPU_ECSSR_SS29 (0x20000000)
|
||||
#define MCF_ETPU_ECSSR_SS30 (0x40000000)
|
||||
#define MCF_ETPU_ECSSR_SS31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECnSCR */
|
||||
#define MCF_ETPU_ECnSCR_FM(x) (((x)&0x00000003)<<0)
|
||||
#define MCF_ETPU_ECnSCR_OBE (0x00002000)
|
||||
#define MCF_ETPU_ECnSCR_OPS (0x00004000)
|
||||
#define MCF_ETPU_ECnSCR_IPS (0x00008000)
|
||||
#define MCF_ETPU_ECnSCR_DTROS (0x00400000)
|
||||
#define MCF_ETPU_ECnSCR_DTRS (0x00800000)
|
||||
#define MCF_ETPU_ECnSCR_CIOS (0x40000000)
|
||||
#define MCF_ETPU_ECnSCR_CIS (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECnCR */
|
||||
#define MCF_ETPU_ECnCR_CPBA(x) (((x)&0x000007FF)<<0)
|
||||
#define MCF_ETPU_ECnCR_OPOL (0x00004000)
|
||||
#define MCF_ETPU_ECnCR_ODIS (0x00008000)
|
||||
#define MCF_ETPU_ECnCR_CFS(x) (((x)&0x0000001F)<<16)
|
||||
#define MCF_ETPU_ECnCR_ETCS (0x01000000)
|
||||
#define MCF_ETPU_ECnCR_CPR(x) (((x)&0x00000003)<<28)
|
||||
#define MCF_ETPU_ECnCR_DTRE (0x40000000)
|
||||
#define MCF_ETPU_ECnCR_CIE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECnHSSR */
|
||||
#define MCF_ETPU_ECnHSSR_HSR(x) (((x)&0x00000007)<<0)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_ETPU_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_etpu.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_ETPU_H__
|
||||
#define __MCF523X_ETPU_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* enhanced Time Processor Unit (ETPU)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_ETPU_EMCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0000]))
|
||||
#define MCF_ETPU_ECDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0004]))
|
||||
#define MCF_ETPU_EMISCCR (*(vuint32*)(void*)(&__IPSBAR[0x1D000C]))
|
||||
#define MCF_ETPU_ESCMODR (*(vuint32*)(void*)(&__IPSBAR[0x1D0010]))
|
||||
#define MCF_ETPU_EECR (*(vuint32*)(void*)(&__IPSBAR[0x1D0014]))
|
||||
#define MCF_ETPU_ETBCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0020]))
|
||||
#define MCF_ETPU_ETB1R (*(vuint32*)(void*)(&__IPSBAR[0x1D0024]))
|
||||
#define MCF_ETPU_ETB2R (*(vuint32*)(void*)(&__IPSBAR[0x1D0028]))
|
||||
#define MCF_ETPU_EREDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D002C]))
|
||||
#define MCF_ETPU_ECISR (*(vuint32*)(void*)(&__IPSBAR[0x1D0200]))
|
||||
#define MCF_ETPU_ECDTRSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0210]))
|
||||
#define MCF_ETPU_ECIOSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0220]))
|
||||
#define MCF_ETPU_ECDTROSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0230]))
|
||||
#define MCF_ETPU_ECIER (*(vuint32*)(void*)(&__IPSBAR[0x1D0240]))
|
||||
#define MCF_ETPU_ECDTRER (*(vuint32*)(void*)(&__IPSBAR[0x1D0250]))
|
||||
#define MCF_ETPU_ECPSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0280]))
|
||||
#define MCF_ETPU_ECSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0290]))
|
||||
#define MCF_ETPU_EC0SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0404]))
|
||||
#define MCF_ETPU_EC1SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0414]))
|
||||
#define MCF_ETPU_EC2SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0424]))
|
||||
#define MCF_ETPU_EC3SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0434]))
|
||||
#define MCF_ETPU_EC4SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0444]))
|
||||
#define MCF_ETPU_EC5SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0454]))
|
||||
#define MCF_ETPU_EC6SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0464]))
|
||||
#define MCF_ETPU_EC7SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0474]))
|
||||
#define MCF_ETPU_EC8SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0484]))
|
||||
#define MCF_ETPU_EC9SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0494]))
|
||||
#define MCF_ETPU_EC10SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A4]))
|
||||
#define MCF_ETPU_EC11SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B4]))
|
||||
#define MCF_ETPU_EC12SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C4]))
|
||||
#define MCF_ETPU_EC13SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D4]))
|
||||
#define MCF_ETPU_EC14SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E4]))
|
||||
#define MCF_ETPU_EC15SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F4]))
|
||||
#define MCF_ETPU_EC16SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0504]))
|
||||
#define MCF_ETPU_EC17SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0514]))
|
||||
#define MCF_ETPU_EC18SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0524]))
|
||||
#define MCF_ETPU_EC19SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0534]))
|
||||
#define MCF_ETPU_EC20SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0544]))
|
||||
#define MCF_ETPU_EC21SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0554]))
|
||||
#define MCF_ETPU_EC22SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0564]))
|
||||
#define MCF_ETPU_EC23SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0574]))
|
||||
#define MCF_ETPU_EC24SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0584]))
|
||||
#define MCF_ETPU_EC25SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0594]))
|
||||
#define MCF_ETPU_EC26SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A4]))
|
||||
#define MCF_ETPU_EC27SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B4]))
|
||||
#define MCF_ETPU_EC28SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C4]))
|
||||
#define MCF_ETPU_EC29SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D4]))
|
||||
#define MCF_ETPU_EC30SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E4]))
|
||||
#define MCF_ETPU_EC31SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F4]))
|
||||
#define MCF_ETPU_ECnSCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0404+((x)*0x010)]))
|
||||
#define MCF_ETPU_EC0CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0400]))
|
||||
#define MCF_ETPU_EC1CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0410]))
|
||||
#define MCF_ETPU_EC2CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0420]))
|
||||
#define MCF_ETPU_EC3CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0430]))
|
||||
#define MCF_ETPU_EC4CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0440]))
|
||||
#define MCF_ETPU_EC5CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0450]))
|
||||
#define MCF_ETPU_EC6CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0460]))
|
||||
#define MCF_ETPU_EC7CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0470]))
|
||||
#define MCF_ETPU_EC8CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0480]))
|
||||
#define MCF_ETPU_EC9CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0490]))
|
||||
#define MCF_ETPU_EC10CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A0]))
|
||||
#define MCF_ETPU_EC11CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B0]))
|
||||
#define MCF_ETPU_EC12CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C0]))
|
||||
#define MCF_ETPU_EC13CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D0]))
|
||||
#define MCF_ETPU_EC14CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E0]))
|
||||
#define MCF_ETPU_EC15CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F0]))
|
||||
#define MCF_ETPU_EC16CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0500]))
|
||||
#define MCF_ETPU_EC17CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0510]))
|
||||
#define MCF_ETPU_EC18CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0520]))
|
||||
#define MCF_ETPU_EC19CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0530]))
|
||||
#define MCF_ETPU_EC20CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0540]))
|
||||
#define MCF_ETPU_EC21CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0550]))
|
||||
#define MCF_ETPU_EC22CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0560]))
|
||||
#define MCF_ETPU_EC23CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0570]))
|
||||
#define MCF_ETPU_EC24CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0580]))
|
||||
#define MCF_ETPU_EC25CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0590]))
|
||||
#define MCF_ETPU_EC26CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A0]))
|
||||
#define MCF_ETPU_EC27CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B0]))
|
||||
#define MCF_ETPU_EC28CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C0]))
|
||||
#define MCF_ETPU_EC29CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D0]))
|
||||
#define MCF_ETPU_EC30CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E0]))
|
||||
#define MCF_ETPU_EC31CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F0]))
|
||||
#define MCF_ETPU_ECnCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0400+((x)*0x010)]))
|
||||
#define MCF_ETPU_EC0HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0408]))
|
||||
#define MCF_ETPU_EC1HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0418]))
|
||||
#define MCF_ETPU_EC2HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0428]))
|
||||
#define MCF_ETPU_EC3HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0438]))
|
||||
#define MCF_ETPU_EC4HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0448]))
|
||||
#define MCF_ETPU_EC5HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0458]))
|
||||
#define MCF_ETPU_EC6HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0468]))
|
||||
#define MCF_ETPU_EC7HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0478]))
|
||||
#define MCF_ETPU_EC8HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0488]))
|
||||
#define MCF_ETPU_EC9HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0498]))
|
||||
#define MCF_ETPU_EC10HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A8]))
|
||||
#define MCF_ETPU_EC11HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B8]))
|
||||
#define MCF_ETPU_EC12HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C8]))
|
||||
#define MCF_ETPU_EC13HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D8]))
|
||||
#define MCF_ETPU_EC14HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E8]))
|
||||
#define MCF_ETPU_EC15HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F8]))
|
||||
#define MCF_ETPU_EC16HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0508]))
|
||||
#define MCF_ETPU_EC17HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0518]))
|
||||
#define MCF_ETPU_EC18HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0528]))
|
||||
#define MCF_ETPU_EC19HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0538]))
|
||||
#define MCF_ETPU_EC20HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0548]))
|
||||
#define MCF_ETPU_EC21HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0558]))
|
||||
#define MCF_ETPU_EC22HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0568]))
|
||||
#define MCF_ETPU_EC23HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0578]))
|
||||
#define MCF_ETPU_EC24HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0588]))
|
||||
#define MCF_ETPU_EC25HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0598]))
|
||||
#define MCF_ETPU_EC26HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A8]))
|
||||
#define MCF_ETPU_EC27HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B8]))
|
||||
#define MCF_ETPU_EC28HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C8]))
|
||||
#define MCF_ETPU_EC29HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D8]))
|
||||
#define MCF_ETPU_EC30HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E8]))
|
||||
#define MCF_ETPU_EC31HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F8]))
|
||||
#define MCF_ETPU_ECnHSSR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0408+((x)*0x010)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_EMCR */
|
||||
#define MCF_ETPU_EMCR_GTBE (0x00000001)
|
||||
#define MCF_ETPU_EMCR_VIS (0x00000040)
|
||||
#define MCF_ETPU_EMCR_SCMMISEN (0x00000200)
|
||||
#define MCF_ETPU_EMCR_SCMMISF (0x00000400)
|
||||
#define MCF_ETPU_EMCR_SCMSIZE(x) (((x)&0x0000001F)<<16)
|
||||
#define MCF_ETPU_EMCR_ILF2 (0x01000000)
|
||||
#define MCF_ETPU_EMCR_ILF1 (0x02000000)
|
||||
#define MCF_ETPU_EMCR_MGE2 (0x04000000)
|
||||
#define MCF_ETPU_EMCR_MGE1 (0x08000000)
|
||||
#define MCF_ETPU_EMCR_GEC (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECDCR */
|
||||
#define MCF_ETPU_ECDCR_PARM1(x) (((x)&0x0000007F)<<0)
|
||||
#define MCF_ETPU_ECDCR_WR (0x00000080)
|
||||
#define MCF_ETPU_ECDCR_PARM0(x) (((x)&0x0000007F)<<8)
|
||||
#define MCF_ETPU_ECDCR_PWIDTH (0x00008000)
|
||||
#define MCF_ETPU_ECDCR_PBASE(x) (((x)&0x000003FF)<<16)
|
||||
#define MCF_ETPU_ECDCR_CTBASE(x) (((x)&0x0000001F)<<26)
|
||||
#define MCF_ETPU_ECDCR_STS (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_EECR */
|
||||
#define MCF_ETPU_EECR_ETB(x) (((x)&0x0000001F)<<0)
|
||||
#define MCF_ETPU_EECR_CDFC(x) (((x)&0x00000003)<<14)
|
||||
#define MCF_ETPU_EECR_FPSK(x) (((x)&0x00000007)<<16)
|
||||
#define MCF_ETPU_EECR_HLTF (0x00800000)
|
||||
#define MCF_ETPU_EECR_STF (0x10000000)
|
||||
#define MCF_ETPU_EECR_MDIS (0x40000000)
|
||||
#define MCF_ETPU_EECR_FEND (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ETBCR */
|
||||
#define MCF_ETPU_ETBCR_TCR1P(x) (((x)&0x000000FF)<<0)
|
||||
#define MCF_ETPU_ETBCR_TCR1CTL(x) (((x)&0x00000003)<<14)
|
||||
#define MCF_ETPU_ETBCR_TCR2P(x) (((x)&0x0000003F)<<16)
|
||||
#define MCF_ETPU_ETBCR_AM (0x02000000)
|
||||
#define MCF_ETPU_ETBCR_TCRCF(x) (((x)&0x00000003)<<27)
|
||||
#define MCF_ETPU_ETBCR_TCR2CTL(x) (((x)&0x00000007)<<29)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ETB1R */
|
||||
#define MCF_ETPU_ETB1R_TCR1(x) (((x)&0x00FFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ETB2R */
|
||||
#define MCF_ETPU_ETB2R_TCR2(x) (((x)&0x00FFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_EREDCR */
|
||||
#define MCF_ETPU_EREDCR_SRV2(x) (((x)&0x0000000F)<<0)
|
||||
#define MCF_ETPU_EREDCR_SERVER_ID2(x) (((x)&0x0000000F)<<8)
|
||||
#define MCF_ETPU_EREDCR_RSC2 (0x00004000)
|
||||
#define MCF_ETPU_EREDCR_REN2 (0x00008000)
|
||||
#define MCF_ETPU_EREDCR_SRV1(x) (((x)&0x0000000F)<<16)
|
||||
#define MCF_ETPU_EREDCR_SERVER_ID1(x) (((x)&0x0000000F)<<24)
|
||||
#define MCF_ETPU_EREDCR_RSC1 (0x40000000)
|
||||
#define MCF_ETPU_EREDCR_REN1 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECISR */
|
||||
#define MCF_ETPU_ECISR_CIS0 (0x00000001)
|
||||
#define MCF_ETPU_ECISR_CIS1 (0x00000002)
|
||||
#define MCF_ETPU_ECISR_CIS2 (0x00000004)
|
||||
#define MCF_ETPU_ECISR_CIS3 (0x00000008)
|
||||
#define MCF_ETPU_ECISR_CIS4 (0x00000010)
|
||||
#define MCF_ETPU_ECISR_CIS5 (0x00000020)
|
||||
#define MCF_ETPU_ECISR_CIS6 (0x00000040)
|
||||
#define MCF_ETPU_ECISR_CIS7 (0x00000080)
|
||||
#define MCF_ETPU_ECISR_CIS8 (0x00000100)
|
||||
#define MCF_ETPU_ECISR_CIS9 (0x00000200)
|
||||
#define MCF_ETPU_ECISR_CIS10 (0x00000400)
|
||||
#define MCF_ETPU_ECISR_CIS11 (0x00000800)
|
||||
#define MCF_ETPU_ECISR_CIS12 (0x00001000)
|
||||
#define MCF_ETPU_ECISR_CIS13 (0x00002000)
|
||||
#define MCF_ETPU_ECISR_CIS14 (0x00004000)
|
||||
#define MCF_ETPU_ECISR_CIS15 (0x00008000)
|
||||
#define MCF_ETPU_ECISR_CIS16 (0x00010000)
|
||||
#define MCF_ETPU_ECISR_CIS17 (0x00020000)
|
||||
#define MCF_ETPU_ECISR_CIS18 (0x00040000)
|
||||
#define MCF_ETPU_ECISR_CIS19 (0x00080000)
|
||||
#define MCF_ETPU_ECISR_CIS20 (0x00100000)
|
||||
#define MCF_ETPU_ECISR_CIS21 (0x00200000)
|
||||
#define MCF_ETPU_ECISR_CIS22 (0x00400000)
|
||||
#define MCF_ETPU_ECISR_CIS23 (0x00800000)
|
||||
#define MCF_ETPU_ECISR_CIS24 (0x01000000)
|
||||
#define MCF_ETPU_ECISR_CIS25 (0x02000000)
|
||||
#define MCF_ETPU_ECISR_CIS26 (0x04000000)
|
||||
#define MCF_ETPU_ECISR_CIS27 (0x08000000)
|
||||
#define MCF_ETPU_ECISR_CIS28 (0x10000000)
|
||||
#define MCF_ETPU_ECISR_CIS29 (0x20000000)
|
||||
#define MCF_ETPU_ECISR_CIS30 (0x40000000)
|
||||
#define MCF_ETPU_ECISR_CIS31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECDTRSR */
|
||||
#define MCF_ETPU_ECDTRSR_DTRS0 (0x00000001)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS1 (0x00000002)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS2 (0x00000004)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS3 (0x00000008)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS4 (0x00000010)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS5 (0x00000020)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS6 (0x00000040)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS7 (0x00000080)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS8 (0x00000100)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS9 (0x00000200)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS10 (0x00000400)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS11 (0x00000800)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS12 (0x00001000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS13 (0x00002000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS14 (0x00004000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS15 (0x00008000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS16 (0x00010000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS17 (0x00020000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS18 (0x00040000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS19 (0x00080000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS20 (0x00100000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS21 (0x00200000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS22 (0x00400000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS23 (0x00800000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS24 (0x01000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS25 (0x02000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS26 (0x04000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS27 (0x08000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS28 (0x10000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS29 (0x20000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS30 (0x40000000)
|
||||
#define MCF_ETPU_ECDTRSR_DTRS31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECIOSR */
|
||||
#define MCF_ETPU_ECIOSR_CIOS0 (0x00000001)
|
||||
#define MCF_ETPU_ECIOSR_CIOS1 (0x00000002)
|
||||
#define MCF_ETPU_ECIOSR_CIOS2 (0x00000004)
|
||||
#define MCF_ETPU_ECIOSR_CIOS3 (0x00000008)
|
||||
#define MCF_ETPU_ECIOSR_CIOS4 (0x00000010)
|
||||
#define MCF_ETPU_ECIOSR_CIOS5 (0x00000020)
|
||||
#define MCF_ETPU_ECIOSR_CIOS6 (0x00000040)
|
||||
#define MCF_ETPU_ECIOSR_CIOS7 (0x00000080)
|
||||
#define MCF_ETPU_ECIOSR_CIOS8 (0x00000100)
|
||||
#define MCF_ETPU_ECIOSR_CIOS9 (0x00000200)
|
||||
#define MCF_ETPU_ECIOSR_CIOS10 (0x00000400)
|
||||
#define MCF_ETPU_ECIOSR_CIOS11 (0x00000800)
|
||||
#define MCF_ETPU_ECIOSR_CIOS12 (0x00001000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS13 (0x00002000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS14 (0x00004000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS15 (0x00008000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS16 (0x00010000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS17 (0x00020000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS18 (0x00040000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS19 (0x00080000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS20 (0x00100000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS21 (0x00200000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS22 (0x00400000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS23 (0x00800000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS24 (0x01000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS25 (0x02000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS26 (0x04000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS27 (0x08000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS28 (0x10000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS29 (0x20000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS30 (0x40000000)
|
||||
#define MCF_ETPU_ECIOSR_CIOS31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECDTROSR */
|
||||
#define MCF_ETPU_ECDTROSR_DTROS0 (0x00000001)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS1 (0x00000002)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS2 (0x00000004)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS3 (0x00000008)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS4 (0x00000010)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS5 (0x00000020)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS6 (0x00000040)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS7 (0x00000080)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS8 (0x00000100)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS9 (0x00000200)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS10 (0x00000400)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS11 (0x00000800)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS12 (0x00001000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS13 (0x00002000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS14 (0x00004000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS15 (0x00008000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS16 (0x00010000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS17 (0x00020000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS18 (0x00040000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS19 (0x00080000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS20 (0x00100000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS21 (0x00200000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS22 (0x00400000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS23 (0x00800000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS24 (0x01000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS25 (0x02000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS26 (0x04000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS27 (0x08000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS28 (0x10000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS29 (0x20000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS30 (0x40000000)
|
||||
#define MCF_ETPU_ECDTROSR_DTROS31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECIER */
|
||||
#define MCF_ETPU_ECIER_CIE0 (0x00000001)
|
||||
#define MCF_ETPU_ECIER_CIE1 (0x00000002)
|
||||
#define MCF_ETPU_ECIER_CIE2 (0x00000004)
|
||||
#define MCF_ETPU_ECIER_CIE3 (0x00000008)
|
||||
#define MCF_ETPU_ECIER_CIE4 (0x00000010)
|
||||
#define MCF_ETPU_ECIER_CIE5 (0x00000020)
|
||||
#define MCF_ETPU_ECIER_CIE6 (0x00000040)
|
||||
#define MCF_ETPU_ECIER_CIE7 (0x00000080)
|
||||
#define MCF_ETPU_ECIER_CIE8 (0x00000100)
|
||||
#define MCF_ETPU_ECIER_CIE9 (0x00000200)
|
||||
#define MCF_ETPU_ECIER_CIE10 (0x00000400)
|
||||
#define MCF_ETPU_ECIER_CIE11 (0x00000800)
|
||||
#define MCF_ETPU_ECIER_CIE12 (0x00001000)
|
||||
#define MCF_ETPU_ECIER_CIE13 (0x00002000)
|
||||
#define MCF_ETPU_ECIER_CIE14 (0x00004000)
|
||||
#define MCF_ETPU_ECIER_CIE15 (0x00008000)
|
||||
#define MCF_ETPU_ECIER_CIE16 (0x00010000)
|
||||
#define MCF_ETPU_ECIER_CIE17 (0x00020000)
|
||||
#define MCF_ETPU_ECIER_CIE18 (0x00040000)
|
||||
#define MCF_ETPU_ECIER_CIE19 (0x00080000)
|
||||
#define MCF_ETPU_ECIER_CIE20 (0x00100000)
|
||||
#define MCF_ETPU_ECIER_CIE21 (0x00200000)
|
||||
#define MCF_ETPU_ECIER_CIE22 (0x00400000)
|
||||
#define MCF_ETPU_ECIER_CIE23 (0x00800000)
|
||||
#define MCF_ETPU_ECIER_CIE24 (0x01000000)
|
||||
#define MCF_ETPU_ECIER_CIE25 (0x02000000)
|
||||
#define MCF_ETPU_ECIER_CIE26 (0x04000000)
|
||||
#define MCF_ETPU_ECIER_CIE27 (0x08000000)
|
||||
#define MCF_ETPU_ECIER_CIE28 (0x10000000)
|
||||
#define MCF_ETPU_ECIER_CIE29 (0x20000000)
|
||||
#define MCF_ETPU_ECIER_CIE30 (0x40000000)
|
||||
#define MCF_ETPU_ECIER_CIE31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECDTRER */
|
||||
#define MCF_ETPU_ECDTRER_DTRE0 (0x00000001)
|
||||
#define MCF_ETPU_ECDTRER_DTRE1 (0x00000002)
|
||||
#define MCF_ETPU_ECDTRER_DTRE2 (0x00000004)
|
||||
#define MCF_ETPU_ECDTRER_DTRE3 (0x00000008)
|
||||
#define MCF_ETPU_ECDTRER_DTRE4 (0x00000010)
|
||||
#define MCF_ETPU_ECDTRER_DTRE5 (0x00000020)
|
||||
#define MCF_ETPU_ECDTRER_DTRE6 (0x00000040)
|
||||
#define MCF_ETPU_ECDTRER_DTRE7 (0x00000080)
|
||||
#define MCF_ETPU_ECDTRER_DTRE8 (0x00000100)
|
||||
#define MCF_ETPU_ECDTRER_DTRE9 (0x00000200)
|
||||
#define MCF_ETPU_ECDTRER_DTRE10 (0x00000400)
|
||||
#define MCF_ETPU_ECDTRER_DTRE11 (0x00000800)
|
||||
#define MCF_ETPU_ECDTRER_DTRE12 (0x00001000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE13 (0x00002000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE14 (0x00004000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE15 (0x00008000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE16 (0x00010000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE17 (0x00020000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE18 (0x00040000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE19 (0x00080000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE20 (0x00100000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE21 (0x00200000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE22 (0x00400000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE23 (0x00800000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE24 (0x01000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE25 (0x02000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE26 (0x04000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE27 (0x08000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE28 (0x10000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE29 (0x20000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE30 (0x40000000)
|
||||
#define MCF_ETPU_ECDTRER_DTRE31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECPSSR */
|
||||
#define MCF_ETPU_ECPSSR_SR0 (0x00000001)
|
||||
#define MCF_ETPU_ECPSSR_SR1 (0x00000002)
|
||||
#define MCF_ETPU_ECPSSR_SR2 (0x00000004)
|
||||
#define MCF_ETPU_ECPSSR_SR3 (0x00000008)
|
||||
#define MCF_ETPU_ECPSSR_SR4 (0x00000010)
|
||||
#define MCF_ETPU_ECPSSR_SR5 (0x00000020)
|
||||
#define MCF_ETPU_ECPSSR_SR6 (0x00000040)
|
||||
#define MCF_ETPU_ECPSSR_SR7 (0x00000080)
|
||||
#define MCF_ETPU_ECPSSR_SR8 (0x00000100)
|
||||
#define MCF_ETPU_ECPSSR_SR9 (0x00000200)
|
||||
#define MCF_ETPU_ECPSSR_SR10 (0x00000400)
|
||||
#define MCF_ETPU_ECPSSR_SR11 (0x00000800)
|
||||
#define MCF_ETPU_ECPSSR_SR12 (0x00001000)
|
||||
#define MCF_ETPU_ECPSSR_SR13 (0x00002000)
|
||||
#define MCF_ETPU_ECPSSR_SR14 (0x00004000)
|
||||
#define MCF_ETPU_ECPSSR_SR15 (0x00008000)
|
||||
#define MCF_ETPU_ECPSSR_SR16 (0x00010000)
|
||||
#define MCF_ETPU_ECPSSR_SR17 (0x00020000)
|
||||
#define MCF_ETPU_ECPSSR_SR18 (0x00040000)
|
||||
#define MCF_ETPU_ECPSSR_SR19 (0x00080000)
|
||||
#define MCF_ETPU_ECPSSR_SR20 (0x00100000)
|
||||
#define MCF_ETPU_ECPSSR_SR21 (0x00200000)
|
||||
#define MCF_ETPU_ECPSSR_SR22 (0x00400000)
|
||||
#define MCF_ETPU_ECPSSR_SR23 (0x00800000)
|
||||
#define MCF_ETPU_ECPSSR_SR24 (0x01000000)
|
||||
#define MCF_ETPU_ECPSSR_SR25 (0x02000000)
|
||||
#define MCF_ETPU_ECPSSR_SR26 (0x04000000)
|
||||
#define MCF_ETPU_ECPSSR_SR27 (0x08000000)
|
||||
#define MCF_ETPU_ECPSSR_SR28 (0x10000000)
|
||||
#define MCF_ETPU_ECPSSR_SR29 (0x20000000)
|
||||
#define MCF_ETPU_ECPSSR_SR30 (0x40000000)
|
||||
#define MCF_ETPU_ECPSSR_SR31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECSSR */
|
||||
#define MCF_ETPU_ECSSR_SS0 (0x00000001)
|
||||
#define MCF_ETPU_ECSSR_SS1 (0x00000002)
|
||||
#define MCF_ETPU_ECSSR_SS2 (0x00000004)
|
||||
#define MCF_ETPU_ECSSR_SS3 (0x00000008)
|
||||
#define MCF_ETPU_ECSSR_SS4 (0x00000010)
|
||||
#define MCF_ETPU_ECSSR_SS5 (0x00000020)
|
||||
#define MCF_ETPU_ECSSR_SS6 (0x00000040)
|
||||
#define MCF_ETPU_ECSSR_SS7 (0x00000080)
|
||||
#define MCF_ETPU_ECSSR_SS8 (0x00000100)
|
||||
#define MCF_ETPU_ECSSR_SS9 (0x00000200)
|
||||
#define MCF_ETPU_ECSSR_SS10 (0x00000400)
|
||||
#define MCF_ETPU_ECSSR_SS11 (0x00000800)
|
||||
#define MCF_ETPU_ECSSR_SS12 (0x00001000)
|
||||
#define MCF_ETPU_ECSSR_SS13 (0x00002000)
|
||||
#define MCF_ETPU_ECSSR_SS14 (0x00004000)
|
||||
#define MCF_ETPU_ECSSR_SS15 (0x00008000)
|
||||
#define MCF_ETPU_ECSSR_SS16 (0x00010000)
|
||||
#define MCF_ETPU_ECSSR_SS17 (0x00020000)
|
||||
#define MCF_ETPU_ECSSR_SS18 (0x00040000)
|
||||
#define MCF_ETPU_ECSSR_SS19 (0x00080000)
|
||||
#define MCF_ETPU_ECSSR_SS20 (0x00100000)
|
||||
#define MCF_ETPU_ECSSR_SS21 (0x00200000)
|
||||
#define MCF_ETPU_ECSSR_SS22 (0x00400000)
|
||||
#define MCF_ETPU_ECSSR_SS23 (0x00800000)
|
||||
#define MCF_ETPU_ECSSR_SS24 (0x01000000)
|
||||
#define MCF_ETPU_ECSSR_SS25 (0x02000000)
|
||||
#define MCF_ETPU_ECSSR_SS26 (0x04000000)
|
||||
#define MCF_ETPU_ECSSR_SS27 (0x08000000)
|
||||
#define MCF_ETPU_ECSSR_SS28 (0x10000000)
|
||||
#define MCF_ETPU_ECSSR_SS29 (0x20000000)
|
||||
#define MCF_ETPU_ECSSR_SS30 (0x40000000)
|
||||
#define MCF_ETPU_ECSSR_SS31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECnSCR */
|
||||
#define MCF_ETPU_ECnSCR_FM(x) (((x)&0x00000003)<<0)
|
||||
#define MCF_ETPU_ECnSCR_OBE (0x00002000)
|
||||
#define MCF_ETPU_ECnSCR_OPS (0x00004000)
|
||||
#define MCF_ETPU_ECnSCR_IPS (0x00008000)
|
||||
#define MCF_ETPU_ECnSCR_DTROS (0x00400000)
|
||||
#define MCF_ETPU_ECnSCR_DTRS (0x00800000)
|
||||
#define MCF_ETPU_ECnSCR_CIOS (0x40000000)
|
||||
#define MCF_ETPU_ECnSCR_CIS (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECnCR */
|
||||
#define MCF_ETPU_ECnCR_CPBA(x) (((x)&0x000007FF)<<0)
|
||||
#define MCF_ETPU_ECnCR_OPOL (0x00004000)
|
||||
#define MCF_ETPU_ECnCR_ODIS (0x00008000)
|
||||
#define MCF_ETPU_ECnCR_CFS(x) (((x)&0x0000001F)<<16)
|
||||
#define MCF_ETPU_ECnCR_ETCS (0x01000000)
|
||||
#define MCF_ETPU_ECnCR_CPR(x) (((x)&0x00000003)<<28)
|
||||
#define MCF_ETPU_ECnCR_DTRE (0x40000000)
|
||||
#define MCF_ETPU_ECnCR_CIE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_ETPU_ECnHSSR */
|
||||
#define MCF_ETPU_ECnHSSR_HSR(x) (((x)&0x00000007)<<0)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_ETPU_H__ */
|
||||
|
|
|
|||
|
|
@ -1,208 +1,208 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_fec.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_FEC_H__
|
||||
#define __MCF523X_FEC_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Fast Ethernet Controller (FEC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_FEC_EIR (*(vuint32*)(void*)(&__IPSBAR[0x001004]))
|
||||
#define MCF_FEC_EIMR (*(vuint32*)(void*)(&__IPSBAR[0x001008]))
|
||||
#define MCF_FEC_RDAR (*(vuint32*)(void*)(&__IPSBAR[0x001010]))
|
||||
#define MCF_FEC_TDAR (*(vuint32*)(void*)(&__IPSBAR[0x001014]))
|
||||
#define MCF_FEC_ECR (*(vuint32*)(void*)(&__IPSBAR[0x001024]))
|
||||
#define MCF_FEC_MMFR (*(vuint32*)(void*)(&__IPSBAR[0x001040]))
|
||||
#define MCF_FEC_MSCR (*(vuint32*)(void*)(&__IPSBAR[0x001044]))
|
||||
#define MCF_FEC_MIBC (*(vuint32*)(void*)(&__IPSBAR[0x001064]))
|
||||
#define MCF_FEC_RCR (*(vuint32*)(void*)(&__IPSBAR[0x001084]))
|
||||
#define MCF_FEC_TCR (*(vuint32*)(void*)(&__IPSBAR[0x0010C4]))
|
||||
#define MCF_FEC_PALR (*(vuint32*)(void*)(&__IPSBAR[0x0010E4]))
|
||||
#define MCF_FEC_PAUR (*(vuint32*)(void*)(&__IPSBAR[0x0010E8]))
|
||||
#define MCF_FEC_OPD (*(vuint32*)(void*)(&__IPSBAR[0x0010EC]))
|
||||
#define MCF_FEC_IAUR (*(vuint32*)(void*)(&__IPSBAR[0x001118]))
|
||||
#define MCF_FEC_IALR (*(vuint32*)(void*)(&__IPSBAR[0x00111C]))
|
||||
#define MCF_FEC_GAUR (*(vuint32*)(void*)(&__IPSBAR[0x001120]))
|
||||
#define MCF_FEC_GALR (*(vuint32*)(void*)(&__IPSBAR[0x001124]))
|
||||
#define MCF_FEC_TFWR (*(vuint32*)(void*)(&__IPSBAR[0x001144]))
|
||||
#define MCF_FEC_FRBR (*(vuint32*)(void*)(&__IPSBAR[0x00114C]))
|
||||
#define MCF_FEC_FRSR (*(vuint32*)(void*)(&__IPSBAR[0x001150]))
|
||||
#define MCF_FEC_ERDSR (*(vuint32*)(void*)(&__IPSBAR[0x001180]))
|
||||
#define MCF_FEC_ETDSR (*(vuint32*)(void*)(&__IPSBAR[0x001184]))
|
||||
#define MCF_FEC_EMRBR (*(vuint32*)(void*)(&__IPSBAR[0x001188]))
|
||||
#define MCF_FEC_RMON_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001200]))
|
||||
#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001204]))
|
||||
#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001208]))
|
||||
#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00120C]))
|
||||
#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001210]))
|
||||
#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001214]))
|
||||
#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001218]))
|
||||
#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00121C]))
|
||||
#define MCF_FEC_RMON_T_JAB (*(vuint32*)(void*)(&__IPSBAR[0x001220]))
|
||||
#define MCF_FEC_RMON_T_COL (*(vuint32*)(void*)(&__IPSBAR[0x001224]))
|
||||
#define MCF_FEC_RMON_T_P64 (*(vuint32*)(void*)(&__IPSBAR[0x001228]))
|
||||
#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x00122C]))
|
||||
#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x001230]))
|
||||
#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x001234]))
|
||||
#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x001238]))
|
||||
#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x00123C]))
|
||||
#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x001240]))
|
||||
#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x001244]))
|
||||
#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001248]))
|
||||
#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x00124C]))
|
||||
#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(void*)(&__IPSBAR[0x001250]))
|
||||
#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(void*)(&__IPSBAR[0x001254]))
|
||||
#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(void*)(&__IPSBAR[0x001258]))
|
||||
#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(void*)(&__IPSBAR[0x00125C]))
|
||||
#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(void*)(&__IPSBAR[0x001260]))
|
||||
#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x001264]))
|
||||
#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(void*)(&__IPSBAR[0x001268]))
|
||||
#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(void*)(&__IPSBAR[0x00126C]))
|
||||
#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x001270]))
|
||||
#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x001274]))
|
||||
#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001284]))
|
||||
#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001288]))
|
||||
#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00128C]))
|
||||
#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001290]))
|
||||
#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001294]))
|
||||
#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001298]))
|
||||
#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00129C]))
|
||||
#define MCF_FEC_RMON_R_JAB (*(vuint32*)(void*)(&__IPSBAR[0x0012A0]))
|
||||
#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(void*)(&__IPSBAR[0x0012A4]))
|
||||
#define MCF_FEC_RMON_R_P64 (*(vuint32*)(void*)(&__IPSBAR[0x0012A8]))
|
||||
#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x0012AC]))
|
||||
#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x0012B0]))
|
||||
#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x0012B4]))
|
||||
#define MCF_FEC_RMON_R_512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x0012B8]))
|
||||
#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x0012C0]))
|
||||
#define MCF_FEC_RMON_R_1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x0012BC]))
|
||||
#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x0012C4]))
|
||||
#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(void*)(&__IPSBAR[0x0012C8]))
|
||||
#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012CC]))
|
||||
#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(void*)(&__IPSBAR[0x0012D0]))
|
||||
#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x0012D4]))
|
||||
#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x0012D8]))
|
||||
#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x0012DC]))
|
||||
#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012E0]))
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EIR */
|
||||
#define MCF_FEC_EIR_UN (0x00080000)
|
||||
#define MCF_FEC_EIR_RL (0x00100000)
|
||||
#define MCF_FEC_EIR_LC (0x00200000)
|
||||
#define MCF_FEC_EIR_EBERR (0x00400000)
|
||||
#define MCF_FEC_EIR_MII (0x00800000)
|
||||
#define MCF_FEC_EIR_RXB (0x01000000)
|
||||
#define MCF_FEC_EIR_RXF (0x02000000)
|
||||
#define MCF_FEC_EIR_TXB (0x04000000)
|
||||
#define MCF_FEC_EIR_TXF (0x08000000)
|
||||
#define MCF_FEC_EIR_GRA (0x10000000)
|
||||
#define MCF_FEC_EIR_BABT (0x20000000)
|
||||
#define MCF_FEC_EIR_BABR (0x40000000)
|
||||
#define MCF_FEC_EIR_HBERR (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EIMR */
|
||||
#define MCF_FEC_EIMR_UN (0x00080000)
|
||||
#define MCF_FEC_EIMR_RL (0x00100000)
|
||||
#define MCF_FEC_EIMR_LC (0x00200000)
|
||||
#define MCF_FEC_EIMR_EBERR (0x00400000)
|
||||
#define MCF_FEC_EIMR_MII (0x00800000)
|
||||
#define MCF_FEC_EIMR_RXB (0x01000000)
|
||||
#define MCF_FEC_EIMR_RXF (0x02000000)
|
||||
#define MCF_FEC_EIMR_TXB (0x04000000)
|
||||
#define MCF_FEC_EIMR_TXF (0x08000000)
|
||||
#define MCF_FEC_EIMR_GRA (0x10000000)
|
||||
#define MCF_FEC_EIMR_BABT (0x20000000)
|
||||
#define MCF_FEC_EIMR_BABR (0x40000000)
|
||||
#define MCF_FEC_EIMR_HBERR (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RDAR */
|
||||
#define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TDAR */
|
||||
#define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ECR */
|
||||
#define MCF_FEC_ECR_RESET (0x00000001)
|
||||
#define MCF_FEC_ECR_ETHER_EN (0x00000002)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MMFR */
|
||||
#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0)
|
||||
#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16)
|
||||
#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18)
|
||||
#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23)
|
||||
#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28)
|
||||
#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30)
|
||||
#define MCF_FEC_MMFR_ST_01 (0x40000000)
|
||||
#define MCF_FEC_MMFR_OP_READ (0x20000000)
|
||||
#define MCF_FEC_MMFR_OP_WRITE (0x10000000)
|
||||
#define MCF_FEC_MMFR_TA_10 (0x00020000)
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MSCR */
|
||||
#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1)
|
||||
#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MIBC */
|
||||
#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
|
||||
#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RCR */
|
||||
#define MCF_FEC_RCR_LOOP (0x00000001)
|
||||
#define MCF_FEC_RCR_DRT (0x00000002)
|
||||
#define MCF_FEC_RCR_MII_MODE (0x00000004)
|
||||
#define MCF_FEC_RCR_PROM (0x00000008)
|
||||
#define MCF_FEC_RCR_BC_REJ (0x00000010)
|
||||
#define MCF_FEC_RCR_FCE (0x00000020)
|
||||
#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TCR */
|
||||
#define MCF_FEC_TCR_GTS (0x00000001)
|
||||
#define MCF_FEC_TCR_HBC (0x00000002)
|
||||
#define MCF_FEC_TCR_FDEN (0x00000004)
|
||||
#define MCF_FEC_TCR_TFC_PAUSE (0x00000008)
|
||||
#define MCF_FEC_TCR_RFC_PAUSE (0x00000010)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_PAUR */
|
||||
#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0)
|
||||
#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_OPD */
|
||||
#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
|
||||
#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TFWR */
|
||||
#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FRBR */
|
||||
#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FRSR */
|
||||
#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ERDSR */
|
||||
#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ETDSR */
|
||||
#define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EMRBR */
|
||||
#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_FEC_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_fec.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_FEC_H__
|
||||
#define __MCF523X_FEC_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Fast Ethernet Controller (FEC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_FEC_EIR (*(vuint32*)(void*)(&__IPSBAR[0x001004]))
|
||||
#define MCF_FEC_EIMR (*(vuint32*)(void*)(&__IPSBAR[0x001008]))
|
||||
#define MCF_FEC_RDAR (*(vuint32*)(void*)(&__IPSBAR[0x001010]))
|
||||
#define MCF_FEC_TDAR (*(vuint32*)(void*)(&__IPSBAR[0x001014]))
|
||||
#define MCF_FEC_ECR (*(vuint32*)(void*)(&__IPSBAR[0x001024]))
|
||||
#define MCF_FEC_MMFR (*(vuint32*)(void*)(&__IPSBAR[0x001040]))
|
||||
#define MCF_FEC_MSCR (*(vuint32*)(void*)(&__IPSBAR[0x001044]))
|
||||
#define MCF_FEC_MIBC (*(vuint32*)(void*)(&__IPSBAR[0x001064]))
|
||||
#define MCF_FEC_RCR (*(vuint32*)(void*)(&__IPSBAR[0x001084]))
|
||||
#define MCF_FEC_TCR (*(vuint32*)(void*)(&__IPSBAR[0x0010C4]))
|
||||
#define MCF_FEC_PALR (*(vuint32*)(void*)(&__IPSBAR[0x0010E4]))
|
||||
#define MCF_FEC_PAUR (*(vuint32*)(void*)(&__IPSBAR[0x0010E8]))
|
||||
#define MCF_FEC_OPD (*(vuint32*)(void*)(&__IPSBAR[0x0010EC]))
|
||||
#define MCF_FEC_IAUR (*(vuint32*)(void*)(&__IPSBAR[0x001118]))
|
||||
#define MCF_FEC_IALR (*(vuint32*)(void*)(&__IPSBAR[0x00111C]))
|
||||
#define MCF_FEC_GAUR (*(vuint32*)(void*)(&__IPSBAR[0x001120]))
|
||||
#define MCF_FEC_GALR (*(vuint32*)(void*)(&__IPSBAR[0x001124]))
|
||||
#define MCF_FEC_TFWR (*(vuint32*)(void*)(&__IPSBAR[0x001144]))
|
||||
#define MCF_FEC_FRBR (*(vuint32*)(void*)(&__IPSBAR[0x00114C]))
|
||||
#define MCF_FEC_FRSR (*(vuint32*)(void*)(&__IPSBAR[0x001150]))
|
||||
#define MCF_FEC_ERDSR (*(vuint32*)(void*)(&__IPSBAR[0x001180]))
|
||||
#define MCF_FEC_ETDSR (*(vuint32*)(void*)(&__IPSBAR[0x001184]))
|
||||
#define MCF_FEC_EMRBR (*(vuint32*)(void*)(&__IPSBAR[0x001188]))
|
||||
#define MCF_FEC_RMON_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001200]))
|
||||
#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001204]))
|
||||
#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001208]))
|
||||
#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00120C]))
|
||||
#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001210]))
|
||||
#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001214]))
|
||||
#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001218]))
|
||||
#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00121C]))
|
||||
#define MCF_FEC_RMON_T_JAB (*(vuint32*)(void*)(&__IPSBAR[0x001220]))
|
||||
#define MCF_FEC_RMON_T_COL (*(vuint32*)(void*)(&__IPSBAR[0x001224]))
|
||||
#define MCF_FEC_RMON_T_P64 (*(vuint32*)(void*)(&__IPSBAR[0x001228]))
|
||||
#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x00122C]))
|
||||
#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x001230]))
|
||||
#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x001234]))
|
||||
#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x001238]))
|
||||
#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x00123C]))
|
||||
#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x001240]))
|
||||
#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x001244]))
|
||||
#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001248]))
|
||||
#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x00124C]))
|
||||
#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(void*)(&__IPSBAR[0x001250]))
|
||||
#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(void*)(&__IPSBAR[0x001254]))
|
||||
#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(void*)(&__IPSBAR[0x001258]))
|
||||
#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(void*)(&__IPSBAR[0x00125C]))
|
||||
#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(void*)(&__IPSBAR[0x001260]))
|
||||
#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x001264]))
|
||||
#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(void*)(&__IPSBAR[0x001268]))
|
||||
#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(void*)(&__IPSBAR[0x00126C]))
|
||||
#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x001270]))
|
||||
#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x001274]))
|
||||
#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001284]))
|
||||
#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001288]))
|
||||
#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00128C]))
|
||||
#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001290]))
|
||||
#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001294]))
|
||||
#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001298]))
|
||||
#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00129C]))
|
||||
#define MCF_FEC_RMON_R_JAB (*(vuint32*)(void*)(&__IPSBAR[0x0012A0]))
|
||||
#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(void*)(&__IPSBAR[0x0012A4]))
|
||||
#define MCF_FEC_RMON_R_P64 (*(vuint32*)(void*)(&__IPSBAR[0x0012A8]))
|
||||
#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x0012AC]))
|
||||
#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x0012B0]))
|
||||
#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x0012B4]))
|
||||
#define MCF_FEC_RMON_R_512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x0012B8]))
|
||||
#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x0012C0]))
|
||||
#define MCF_FEC_RMON_R_1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x0012BC]))
|
||||
#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x0012C4]))
|
||||
#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(void*)(&__IPSBAR[0x0012C8]))
|
||||
#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012CC]))
|
||||
#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(void*)(&__IPSBAR[0x0012D0]))
|
||||
#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x0012D4]))
|
||||
#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x0012D8]))
|
||||
#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x0012DC]))
|
||||
#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012E0]))
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EIR */
|
||||
#define MCF_FEC_EIR_UN (0x00080000)
|
||||
#define MCF_FEC_EIR_RL (0x00100000)
|
||||
#define MCF_FEC_EIR_LC (0x00200000)
|
||||
#define MCF_FEC_EIR_EBERR (0x00400000)
|
||||
#define MCF_FEC_EIR_MII (0x00800000)
|
||||
#define MCF_FEC_EIR_RXB (0x01000000)
|
||||
#define MCF_FEC_EIR_RXF (0x02000000)
|
||||
#define MCF_FEC_EIR_TXB (0x04000000)
|
||||
#define MCF_FEC_EIR_TXF (0x08000000)
|
||||
#define MCF_FEC_EIR_GRA (0x10000000)
|
||||
#define MCF_FEC_EIR_BABT (0x20000000)
|
||||
#define MCF_FEC_EIR_BABR (0x40000000)
|
||||
#define MCF_FEC_EIR_HBERR (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EIMR */
|
||||
#define MCF_FEC_EIMR_UN (0x00080000)
|
||||
#define MCF_FEC_EIMR_RL (0x00100000)
|
||||
#define MCF_FEC_EIMR_LC (0x00200000)
|
||||
#define MCF_FEC_EIMR_EBERR (0x00400000)
|
||||
#define MCF_FEC_EIMR_MII (0x00800000)
|
||||
#define MCF_FEC_EIMR_RXB (0x01000000)
|
||||
#define MCF_FEC_EIMR_RXF (0x02000000)
|
||||
#define MCF_FEC_EIMR_TXB (0x04000000)
|
||||
#define MCF_FEC_EIMR_TXF (0x08000000)
|
||||
#define MCF_FEC_EIMR_GRA (0x10000000)
|
||||
#define MCF_FEC_EIMR_BABT (0x20000000)
|
||||
#define MCF_FEC_EIMR_BABR (0x40000000)
|
||||
#define MCF_FEC_EIMR_HBERR (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RDAR */
|
||||
#define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TDAR */
|
||||
#define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ECR */
|
||||
#define MCF_FEC_ECR_RESET (0x00000001)
|
||||
#define MCF_FEC_ECR_ETHER_EN (0x00000002)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MMFR */
|
||||
#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0)
|
||||
#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16)
|
||||
#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18)
|
||||
#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23)
|
||||
#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28)
|
||||
#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30)
|
||||
#define MCF_FEC_MMFR_ST_01 (0x40000000)
|
||||
#define MCF_FEC_MMFR_OP_READ (0x20000000)
|
||||
#define MCF_FEC_MMFR_OP_WRITE (0x10000000)
|
||||
#define MCF_FEC_MMFR_TA_10 (0x00020000)
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MSCR */
|
||||
#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1)
|
||||
#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MIBC */
|
||||
#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
|
||||
#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RCR */
|
||||
#define MCF_FEC_RCR_LOOP (0x00000001)
|
||||
#define MCF_FEC_RCR_DRT (0x00000002)
|
||||
#define MCF_FEC_RCR_MII_MODE (0x00000004)
|
||||
#define MCF_FEC_RCR_PROM (0x00000008)
|
||||
#define MCF_FEC_RCR_BC_REJ (0x00000010)
|
||||
#define MCF_FEC_RCR_FCE (0x00000020)
|
||||
#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TCR */
|
||||
#define MCF_FEC_TCR_GTS (0x00000001)
|
||||
#define MCF_FEC_TCR_HBC (0x00000002)
|
||||
#define MCF_FEC_TCR_FDEN (0x00000004)
|
||||
#define MCF_FEC_TCR_TFC_PAUSE (0x00000008)
|
||||
#define MCF_FEC_TCR_RFC_PAUSE (0x00000010)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_PAUR */
|
||||
#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0)
|
||||
#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_OPD */
|
||||
#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
|
||||
#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TFWR */
|
||||
#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FRBR */
|
||||
#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FRSR */
|
||||
#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ERDSR */
|
||||
#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ETDSR */
|
||||
#define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EMRBR */
|
||||
#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_FEC_H__ */
|
||||
|
|
|
|||
|
|
@ -1,55 +1,55 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_fmpll.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_FMPLL_H__
|
||||
#define __MCF523X_FMPLL_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Frequency Modulated Phase Locked Loop (FMPLL)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_FMPLL_SYNCR (*(vuint32*)(void*)(&__IPSBAR[0x120000]))
|
||||
#define MCF_FMPLL_SYNSR (*(vuint32*)(void*)(&__IPSBAR[0x120004]))
|
||||
|
||||
/* Bit definitions and macros for MCF_FMPLL_SYNCR */
|
||||
#define MCF_FMPLL_SYNCR_EXP(x) (((x)&0x000003FF)<<0)
|
||||
#define MCF_FMPLL_SYNCR_DEPTH(x) (((x)&0x00000003)<<10)
|
||||
#define MCF_FMPLL_SYNCR_RATE (0x00001000)
|
||||
#define MCF_FMPLL_SYNCR_LOCIRQ (0x00002000)
|
||||
#define MCF_FMPLL_SYNCR_LOLIRQ (0x00004000)
|
||||
#define MCF_FMPLL_SYNCR_DISCLK (0x00008000)
|
||||
#define MCF_FMPLL_SYNCR_LOCRE (0x00010000)
|
||||
#define MCF_FMPLL_SYNCR_LOLRE (0x00020000)
|
||||
#define MCF_FMPLL_SYNCR_LOCEN (0x00040000)
|
||||
#define MCF_FMPLL_SYNCR_RFD(x) (((x)&0x00000007)<<19)
|
||||
#define MCF_FMPLL_SYNCR_MFD(x) (((x)&0x00000007)<<24)
|
||||
|
||||
/* Bit definitions and macros for MCF_FMPLL_SYNSR */
|
||||
#define MCF_FMPLL_SYNSR_CALPASS (0x00000001)
|
||||
#define MCF_FMPLL_SYNSR_CALDONE (0x00000002)
|
||||
#define MCF_FMPLL_SYNSR_LOCF (0x00000004)
|
||||
#define MCF_FMPLL_SYNSR_LOCK (0x00000008)
|
||||
#define MCF_FMPLL_SYNSR_LOCKS (0x00000010)
|
||||
#define MCF_FMPLL_SYNSR_PLLREF (0x00000020)
|
||||
#define MCF_FMPLL_SYNSR_PLLSEL (0x00000040)
|
||||
#define MCF_FMPLL_SYNSR_MODE (0x00000080)
|
||||
#define MCF_FMPLL_SYNSR_LOC (0x00000100)
|
||||
#define MCF_FMPLL_SYNSR_LOLF (0x00000200)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_FMPLL_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_fmpll.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_FMPLL_H__
|
||||
#define __MCF523X_FMPLL_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Frequency Modulated Phase Locked Loop (FMPLL)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_FMPLL_SYNCR (*(vuint32*)(void*)(&__IPSBAR[0x120000]))
|
||||
#define MCF_FMPLL_SYNSR (*(vuint32*)(void*)(&__IPSBAR[0x120004]))
|
||||
|
||||
/* Bit definitions and macros for MCF_FMPLL_SYNCR */
|
||||
#define MCF_FMPLL_SYNCR_EXP(x) (((x)&0x000003FF)<<0)
|
||||
#define MCF_FMPLL_SYNCR_DEPTH(x) (((x)&0x00000003)<<10)
|
||||
#define MCF_FMPLL_SYNCR_RATE (0x00001000)
|
||||
#define MCF_FMPLL_SYNCR_LOCIRQ (0x00002000)
|
||||
#define MCF_FMPLL_SYNCR_LOLIRQ (0x00004000)
|
||||
#define MCF_FMPLL_SYNCR_DISCLK (0x00008000)
|
||||
#define MCF_FMPLL_SYNCR_LOCRE (0x00010000)
|
||||
#define MCF_FMPLL_SYNCR_LOLRE (0x00020000)
|
||||
#define MCF_FMPLL_SYNCR_LOCEN (0x00040000)
|
||||
#define MCF_FMPLL_SYNCR_RFD(x) (((x)&0x00000007)<<19)
|
||||
#define MCF_FMPLL_SYNCR_MFD(x) (((x)&0x00000007)<<24)
|
||||
|
||||
/* Bit definitions and macros for MCF_FMPLL_SYNSR */
|
||||
#define MCF_FMPLL_SYNSR_CALPASS (0x00000001)
|
||||
#define MCF_FMPLL_SYNSR_CALDONE (0x00000002)
|
||||
#define MCF_FMPLL_SYNSR_LOCF (0x00000004)
|
||||
#define MCF_FMPLL_SYNSR_LOCK (0x00000008)
|
||||
#define MCF_FMPLL_SYNSR_LOCKS (0x00000010)
|
||||
#define MCF_FMPLL_SYNSR_PLLREF (0x00000020)
|
||||
#define MCF_FMPLL_SYNSR_PLLSEL (0x00000040)
|
||||
#define MCF_FMPLL_SYNSR_MODE (0x00000080)
|
||||
#define MCF_FMPLL_SYNSR_LOC (0x00000100)
|
||||
#define MCF_FMPLL_SYNSR_LOLF (0x00000200)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_FMPLL_H__ */
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,63 +1,63 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_i2c.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_I2C_H__
|
||||
#define __MCF523X_I2C_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* I2C Module (I2C)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_I2C_I2AR (*(vuint8 *)(void*)(&__IPSBAR[0x000300]))
|
||||
#define MCF_I2C_I2FDR (*(vuint8 *)(void*)(&__IPSBAR[0x000304]))
|
||||
#define MCF_I2C_I2CR (*(vuint8 *)(void*)(&__IPSBAR[0x000308]))
|
||||
#define MCF_I2C_I2SR (*(vuint8 *)(void*)(&__IPSBAR[0x00030C]))
|
||||
#define MCF_I2C_I2DR (*(vuint8 *)(void*)(&__IPSBAR[0x000310]))
|
||||
#define MCF_I2C_I2ICR (*(vuint8 *)(void*)(&__IPSBAR[0x000320]))
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2AR */
|
||||
#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2FDR */
|
||||
#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2CR */
|
||||
#define MCF_I2C_I2CR_RSTA (0x04)
|
||||
#define MCF_I2C_I2CR_TXAK (0x08)
|
||||
#define MCF_I2C_I2CR_MTX (0x10)
|
||||
#define MCF_I2C_I2CR_MSTA (0x20)
|
||||
#define MCF_I2C_I2CR_IIEN (0x40)
|
||||
#define MCF_I2C_I2CR_IEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2SR */
|
||||
#define MCF_I2C_I2SR_RXAK (0x01)
|
||||
#define MCF_I2C_I2SR_IIF (0x02)
|
||||
#define MCF_I2C_I2SR_SRW (0x04)
|
||||
#define MCF_I2C_I2SR_IAL (0x10)
|
||||
#define MCF_I2C_I2SR_IBB (0x20)
|
||||
#define MCF_I2C_I2SR_IAAS (0x40)
|
||||
#define MCF_I2C_I2SR_ICF (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2ICR */
|
||||
#define MCF_I2C_I2ICR_IE (0x01)
|
||||
#define MCF_I2C_I2ICR_RE (0x02)
|
||||
#define MCF_I2C_I2ICR_TE (0x04)
|
||||
#define MCF_I2C_I2ICR_BNBE (0x08)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_I2C_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_i2c.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_I2C_H__
|
||||
#define __MCF523X_I2C_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* I2C Module (I2C)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_I2C_I2AR (*(vuint8 *)(void*)(&__IPSBAR[0x000300]))
|
||||
#define MCF_I2C_I2FDR (*(vuint8 *)(void*)(&__IPSBAR[0x000304]))
|
||||
#define MCF_I2C_I2CR (*(vuint8 *)(void*)(&__IPSBAR[0x000308]))
|
||||
#define MCF_I2C_I2SR (*(vuint8 *)(void*)(&__IPSBAR[0x00030C]))
|
||||
#define MCF_I2C_I2DR (*(vuint8 *)(void*)(&__IPSBAR[0x000310]))
|
||||
#define MCF_I2C_I2ICR (*(vuint8 *)(void*)(&__IPSBAR[0x000320]))
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2AR */
|
||||
#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2FDR */
|
||||
#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2CR */
|
||||
#define MCF_I2C_I2CR_RSTA (0x04)
|
||||
#define MCF_I2C_I2CR_TXAK (0x08)
|
||||
#define MCF_I2C_I2CR_MTX (0x10)
|
||||
#define MCF_I2C_I2CR_MSTA (0x20)
|
||||
#define MCF_I2C_I2CR_IIEN (0x40)
|
||||
#define MCF_I2C_I2CR_IEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2SR */
|
||||
#define MCF_I2C_I2SR_RXAK (0x01)
|
||||
#define MCF_I2C_I2SR_IIF (0x02)
|
||||
#define MCF_I2C_I2SR_SRW (0x04)
|
||||
#define MCF_I2C_I2SR_IAL (0x10)
|
||||
#define MCF_I2C_I2SR_IBB (0x20)
|
||||
#define MCF_I2C_I2SR_IAAS (0x40)
|
||||
#define MCF_I2C_I2SR_ICF (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2ICR */
|
||||
#define MCF_I2C_I2ICR_IE (0x01)
|
||||
#define MCF_I2C_I2ICR_RE (0x02)
|
||||
#define MCF_I2C_I2ICR_TE (0x04)
|
||||
#define MCF_I2C_I2ICR_BNBE (0x08)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_I2C_H__ */
|
||||
|
|
|
|||
|
|
@ -1,323 +1,323 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_intc0.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_INTC0_H__
|
||||
#define __MCF523X_INTC0_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Interrupt Controller 0 (INTC0)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_INTC0_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000C00]))
|
||||
#define MCF_INTC0_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000C04]))
|
||||
#define MCF_INTC0_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000C08]))
|
||||
#define MCF_INTC0_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000C0C]))
|
||||
#define MCF_INTC0_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000C10]))
|
||||
#define MCF_INTC0_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000C14]))
|
||||
#define MCF_INTC0_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000C18]))
|
||||
#define MCF_INTC0_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000C19]))
|
||||
#define MCF_INTC0_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000C40]))
|
||||
#define MCF_INTC0_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000C41]))
|
||||
#define MCF_INTC0_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000C42]))
|
||||
#define MCF_INTC0_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000C43]))
|
||||
#define MCF_INTC0_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000C44]))
|
||||
#define MCF_INTC0_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000C45]))
|
||||
#define MCF_INTC0_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000C46]))
|
||||
#define MCF_INTC0_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000C47]))
|
||||
#define MCF_INTC0_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000C48]))
|
||||
#define MCF_INTC0_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000C49]))
|
||||
#define MCF_INTC0_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4A]))
|
||||
#define MCF_INTC0_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4B]))
|
||||
#define MCF_INTC0_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4C]))
|
||||
#define MCF_INTC0_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4D]))
|
||||
#define MCF_INTC0_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4E]))
|
||||
#define MCF_INTC0_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4F]))
|
||||
#define MCF_INTC0_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000C50]))
|
||||
#define MCF_INTC0_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000C51]))
|
||||
#define MCF_INTC0_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000C52]))
|
||||
#define MCF_INTC0_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000C53]))
|
||||
#define MCF_INTC0_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000C54]))
|
||||
#define MCF_INTC0_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000C55]))
|
||||
#define MCF_INTC0_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000C56]))
|
||||
#define MCF_INTC0_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000C57]))
|
||||
#define MCF_INTC0_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000C58]))
|
||||
#define MCF_INTC0_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000C59]))
|
||||
#define MCF_INTC0_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5A]))
|
||||
#define MCF_INTC0_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5B]))
|
||||
#define MCF_INTC0_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5C]))
|
||||
#define MCF_INTC0_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5D]))
|
||||
#define MCF_INTC0_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5E]))
|
||||
#define MCF_INTC0_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5F]))
|
||||
#define MCF_INTC0_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000C60]))
|
||||
#define MCF_INTC0_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000C61]))
|
||||
#define MCF_INTC0_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000C62]))
|
||||
#define MCF_INTC0_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000C63]))
|
||||
#define MCF_INTC0_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000C64]))
|
||||
#define MCF_INTC0_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000C65]))
|
||||
#define MCF_INTC0_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000C66]))
|
||||
#define MCF_INTC0_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000C67]))
|
||||
#define MCF_INTC0_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000C68]))
|
||||
#define MCF_INTC0_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000C69]))
|
||||
#define MCF_INTC0_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6A]))
|
||||
#define MCF_INTC0_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6B]))
|
||||
#define MCF_INTC0_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6C]))
|
||||
#define MCF_INTC0_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6D]))
|
||||
#define MCF_INTC0_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6E]))
|
||||
#define MCF_INTC0_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6F]))
|
||||
#define MCF_INTC0_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000C70]))
|
||||
#define MCF_INTC0_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000C71]))
|
||||
#define MCF_INTC0_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000C72]))
|
||||
#define MCF_INTC0_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000C73]))
|
||||
#define MCF_INTC0_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000C74]))
|
||||
#define MCF_INTC0_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000C75]))
|
||||
#define MCF_INTC0_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000C76]))
|
||||
#define MCF_INTC0_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000C77]))
|
||||
#define MCF_INTC0_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000C78]))
|
||||
#define MCF_INTC0_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000C79]))
|
||||
#define MCF_INTC0_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7A]))
|
||||
#define MCF_INTC0_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7B]))
|
||||
#define MCF_INTC0_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7C]))
|
||||
#define MCF_INTC0_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7D]))
|
||||
#define MCF_INTC0_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7E]))
|
||||
#define MCF_INTC0_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7F]))
|
||||
#define MCF_INTC0_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000C40+((x)*0x001)]))
|
||||
#define MCF_INTC0_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE0]))
|
||||
#define MCF_INTC0_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4]))
|
||||
#define MCF_INTC0_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE8]))
|
||||
#define MCF_INTC0_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CEC]))
|
||||
#define MCF_INTC0_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF0]))
|
||||
#define MCF_INTC0_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF4]))
|
||||
#define MCF_INTC0_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF8]))
|
||||
#define MCF_INTC0_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CFC]))
|
||||
#define MCF_INTC0_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4+((x)*0x004)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IPRH */
|
||||
#define MCF_INTC0_IPRH_INT32 (0x00000001)
|
||||
#define MCF_INTC0_IPRH_INT33 (0x00000002)
|
||||
#define MCF_INTC0_IPRH_INT34 (0x00000004)
|
||||
#define MCF_INTC0_IPRH_INT35 (0x00000008)
|
||||
#define MCF_INTC0_IPRH_INT36 (0x00000010)
|
||||
#define MCF_INTC0_IPRH_INT37 (0x00000020)
|
||||
#define MCF_INTC0_IPRH_INT38 (0x00000040)
|
||||
#define MCF_INTC0_IPRH_INT39 (0x00000080)
|
||||
#define MCF_INTC0_IPRH_INT40 (0x00000100)
|
||||
#define MCF_INTC0_IPRH_INT41 (0x00000200)
|
||||
#define MCF_INTC0_IPRH_INT42 (0x00000400)
|
||||
#define MCF_INTC0_IPRH_INT43 (0x00000800)
|
||||
#define MCF_INTC0_IPRH_INT44 (0x00001000)
|
||||
#define MCF_INTC0_IPRH_INT45 (0x00002000)
|
||||
#define MCF_INTC0_IPRH_INT46 (0x00004000)
|
||||
#define MCF_INTC0_IPRH_INT47 (0x00008000)
|
||||
#define MCF_INTC0_IPRH_INT48 (0x00010000)
|
||||
#define MCF_INTC0_IPRH_INT49 (0x00020000)
|
||||
#define MCF_INTC0_IPRH_INT50 (0x00040000)
|
||||
#define MCF_INTC0_IPRH_INT51 (0x00080000)
|
||||
#define MCF_INTC0_IPRH_INT52 (0x00100000)
|
||||
#define MCF_INTC0_IPRH_INT53 (0x00200000)
|
||||
#define MCF_INTC0_IPRH_INT54 (0x00400000)
|
||||
#define MCF_INTC0_IPRH_INT55 (0x00800000)
|
||||
#define MCF_INTC0_IPRH_INT56 (0x01000000)
|
||||
#define MCF_INTC0_IPRH_INT57 (0x02000000)
|
||||
#define MCF_INTC0_IPRH_INT58 (0x04000000)
|
||||
#define MCF_INTC0_IPRH_INT59 (0x08000000)
|
||||
#define MCF_INTC0_IPRH_INT60 (0x10000000)
|
||||
#define MCF_INTC0_IPRH_INT61 (0x20000000)
|
||||
#define MCF_INTC0_IPRH_INT62 (0x40000000)
|
||||
#define MCF_INTC0_IPRH_INT63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IPRL */
|
||||
#define MCF_INTC0_IPRL_INT1 (0x00000002)
|
||||
#define MCF_INTC0_IPRL_INT2 (0x00000004)
|
||||
#define MCF_INTC0_IPRL_INT3 (0x00000008)
|
||||
#define MCF_INTC0_IPRL_INT4 (0x00000010)
|
||||
#define MCF_INTC0_IPRL_INT5 (0x00000020)
|
||||
#define MCF_INTC0_IPRL_INT6 (0x00000040)
|
||||
#define MCF_INTC0_IPRL_INT7 (0x00000080)
|
||||
#define MCF_INTC0_IPRL_INT8 (0x00000100)
|
||||
#define MCF_INTC0_IPRL_INT9 (0x00000200)
|
||||
#define MCF_INTC0_IPRL_INT10 (0x00000400)
|
||||
#define MCF_INTC0_IPRL_INT11 (0x00000800)
|
||||
#define MCF_INTC0_IPRL_INT12 (0x00001000)
|
||||
#define MCF_INTC0_IPRL_INT13 (0x00002000)
|
||||
#define MCF_INTC0_IPRL_INT14 (0x00004000)
|
||||
#define MCF_INTC0_IPRL_INT15 (0x00008000)
|
||||
#define MCF_INTC0_IPRL_INT16 (0x00010000)
|
||||
#define MCF_INTC0_IPRL_INT17 (0x00020000)
|
||||
#define MCF_INTC0_IPRL_INT18 (0x00040000)
|
||||
#define MCF_INTC0_IPRL_INT19 (0x00080000)
|
||||
#define MCF_INTC0_IPRL_INT20 (0x00100000)
|
||||
#define MCF_INTC0_IPRL_INT21 (0x00200000)
|
||||
#define MCF_INTC0_IPRL_INT22 (0x00400000)
|
||||
#define MCF_INTC0_IPRL_INT23 (0x00800000)
|
||||
#define MCF_INTC0_IPRL_INT24 (0x01000000)
|
||||
#define MCF_INTC0_IPRL_INT25 (0x02000000)
|
||||
#define MCF_INTC0_IPRL_INT26 (0x04000000)
|
||||
#define MCF_INTC0_IPRL_INT27 (0x08000000)
|
||||
#define MCF_INTC0_IPRL_INT28 (0x10000000)
|
||||
#define MCF_INTC0_IPRL_INT29 (0x20000000)
|
||||
#define MCF_INTC0_IPRL_INT30 (0x40000000)
|
||||
#define MCF_INTC0_IPRL_INT31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IMRH */
|
||||
#define MCF_INTC0_IMRH_INT_MASK32 (0x00000001)
|
||||
#define MCF_INTC0_IMRH_INT_MASK33 (0x00000002)
|
||||
#define MCF_INTC0_IMRH_INT_MASK34 (0x00000004)
|
||||
#define MCF_INTC0_IMRH_INT_MASK35 (0x00000008)
|
||||
#define MCF_INTC0_IMRH_INT_MASK36 (0x00000010)
|
||||
#define MCF_INTC0_IMRH_INT_MASK37 (0x00000020)
|
||||
#define MCF_INTC0_IMRH_INT_MASK38 (0x00000040)
|
||||
#define MCF_INTC0_IMRH_INT_MASK39 (0x00000080)
|
||||
#define MCF_INTC0_IMRH_INT_MASK40 (0x00000100)
|
||||
#define MCF_INTC0_IMRH_INT_MASK41 (0x00000200)
|
||||
#define MCF_INTC0_IMRH_INT_MASK42 (0x00000400)
|
||||
#define MCF_INTC0_IMRH_INT_MASK43 (0x00000800)
|
||||
#define MCF_INTC0_IMRH_INT_MASK44 (0x00001000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK45 (0x00002000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK46 (0x00004000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK47 (0x00008000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK48 (0x00010000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK49 (0x00020000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK50 (0x00040000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK51 (0x00080000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK52 (0x00100000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK53 (0x00200000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK54 (0x00400000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK55 (0x00800000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK56 (0x01000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK57 (0x02000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK58 (0x04000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK59 (0x08000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK60 (0x10000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK61 (0x20000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK62 (0x40000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IMRL */
|
||||
#define MCF_INTC0_IMRL_MASKALL (0x00000001)
|
||||
#define MCF_INTC0_IMRL_INT_MASK1 (0x00000002)
|
||||
#define MCF_INTC0_IMRL_INT_MASK2 (0x00000004)
|
||||
#define MCF_INTC0_IMRL_INT_MASK3 (0x00000008)
|
||||
#define MCF_INTC0_IMRL_INT_MASK4 (0x00000010)
|
||||
#define MCF_INTC0_IMRL_INT_MASK5 (0x00000020)
|
||||
#define MCF_INTC0_IMRL_INT_MASK6 (0x00000040)
|
||||
#define MCF_INTC0_IMRL_INT_MASK7 (0x00000080)
|
||||
#define MCF_INTC0_IMRL_INT_MASK8 (0x00000100)
|
||||
#define MCF_INTC0_IMRL_INT_MASK9 (0x00000200)
|
||||
#define MCF_INTC0_IMRL_INT_MASK10 (0x00000400)
|
||||
#define MCF_INTC0_IMRL_INT_MASK11 (0x00000800)
|
||||
#define MCF_INTC0_IMRL_INT_MASK12 (0x00001000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK13 (0x00002000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK14 (0x00004000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK15 (0x00008000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK16 (0x00010000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK17 (0x00020000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK18 (0x00040000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK19 (0x00080000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK20 (0x00100000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK21 (0x00200000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK22 (0x00400000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK23 (0x00800000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK24 (0x01000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK25 (0x02000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK26 (0x04000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK27 (0x08000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK28 (0x10000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK29 (0x20000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK30 (0x40000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_INTFRCH */
|
||||
#define MCF_INTC0_INTFRCH_INTFRC32 (0x00000001)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC33 (0x00000002)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC34 (0x00000004)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC35 (0x00000008)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC36 (0x00000010)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC37 (0x00000020)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC38 (0x00000040)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC39 (0x00000080)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC40 (0x00000100)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC41 (0x00000200)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC42 (0x00000400)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC43 (0x00000800)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC44 (0x00001000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC45 (0x00002000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC46 (0x00004000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC47 (0x00008000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC48 (0x00010000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC49 (0x00020000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC50 (0x00040000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC51 (0x00080000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC52 (0x00100000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC53 (0x00200000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC54 (0x00400000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC55 (0x00800000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC56 (0x01000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC57 (0x02000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC58 (0x04000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC59 (0x08000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC60 (0x10000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC61 (0x20000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC62 (0x40000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_INTFRCL */
|
||||
#define MCF_INTC0_INTFRCL_INTFRC1 (0x00000002)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC2 (0x00000004)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC3 (0x00000008)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC4 (0x00000010)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC5 (0x00000020)
|
||||
#define MCF_INTC0_INTFRCL_INT6 (0x00000040)
|
||||
#define MCF_INTC0_INTFRCL_INT7 (0x00000080)
|
||||
#define MCF_INTC0_INTFRCL_INT8 (0x00000100)
|
||||
#define MCF_INTC0_INTFRCL_INT9 (0x00000200)
|
||||
#define MCF_INTC0_INTFRCL_INT10 (0x00000400)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC11 (0x00000800)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC12 (0x00001000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC13 (0x00002000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC14 (0x00004000)
|
||||
#define MCF_INTC0_INTFRCL_INT15 (0x00008000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC16 (0x00010000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC17 (0x00020000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC18 (0x00040000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC19 (0x00080000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC20 (0x00100000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC21 (0x00200000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC22 (0x00400000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC23 (0x00800000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC24 (0x01000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC25 (0x02000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC26 (0x04000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC27 (0x08000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC28 (0x10000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC29 (0x20000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC30 (0x40000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IRLR */
|
||||
#define MCF_INTC0_IRLR_IRQ(x) (((x)&0x7F)<<1)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IACKLPR */
|
||||
#define MCF_INTC0_IACKLPR_PRI(x) (((x)&0x0F)<<0)
|
||||
#define MCF_INTC0_IACKLPR_LEVEL(x) (((x)&0x07)<<4)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_ICRn */
|
||||
#define MCF_INTC0_ICRn_IP(x) (((x)&0x07)<<0)
|
||||
#define MCF_INTC0_ICRn_IL(x) (((x)&0x07)<<3)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_INTC0_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_intc0.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_INTC0_H__
|
||||
#define __MCF523X_INTC0_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Interrupt Controller 0 (INTC0)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_INTC0_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000C00]))
|
||||
#define MCF_INTC0_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000C04]))
|
||||
#define MCF_INTC0_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000C08]))
|
||||
#define MCF_INTC0_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000C0C]))
|
||||
#define MCF_INTC0_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000C10]))
|
||||
#define MCF_INTC0_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000C14]))
|
||||
#define MCF_INTC0_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000C18]))
|
||||
#define MCF_INTC0_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000C19]))
|
||||
#define MCF_INTC0_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000C40]))
|
||||
#define MCF_INTC0_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000C41]))
|
||||
#define MCF_INTC0_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000C42]))
|
||||
#define MCF_INTC0_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000C43]))
|
||||
#define MCF_INTC0_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000C44]))
|
||||
#define MCF_INTC0_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000C45]))
|
||||
#define MCF_INTC0_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000C46]))
|
||||
#define MCF_INTC0_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000C47]))
|
||||
#define MCF_INTC0_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000C48]))
|
||||
#define MCF_INTC0_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000C49]))
|
||||
#define MCF_INTC0_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4A]))
|
||||
#define MCF_INTC0_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4B]))
|
||||
#define MCF_INTC0_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4C]))
|
||||
#define MCF_INTC0_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4D]))
|
||||
#define MCF_INTC0_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4E]))
|
||||
#define MCF_INTC0_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4F]))
|
||||
#define MCF_INTC0_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000C50]))
|
||||
#define MCF_INTC0_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000C51]))
|
||||
#define MCF_INTC0_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000C52]))
|
||||
#define MCF_INTC0_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000C53]))
|
||||
#define MCF_INTC0_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000C54]))
|
||||
#define MCF_INTC0_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000C55]))
|
||||
#define MCF_INTC0_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000C56]))
|
||||
#define MCF_INTC0_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000C57]))
|
||||
#define MCF_INTC0_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000C58]))
|
||||
#define MCF_INTC0_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000C59]))
|
||||
#define MCF_INTC0_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5A]))
|
||||
#define MCF_INTC0_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5B]))
|
||||
#define MCF_INTC0_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5C]))
|
||||
#define MCF_INTC0_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5D]))
|
||||
#define MCF_INTC0_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5E]))
|
||||
#define MCF_INTC0_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5F]))
|
||||
#define MCF_INTC0_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000C60]))
|
||||
#define MCF_INTC0_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000C61]))
|
||||
#define MCF_INTC0_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000C62]))
|
||||
#define MCF_INTC0_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000C63]))
|
||||
#define MCF_INTC0_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000C64]))
|
||||
#define MCF_INTC0_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000C65]))
|
||||
#define MCF_INTC0_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000C66]))
|
||||
#define MCF_INTC0_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000C67]))
|
||||
#define MCF_INTC0_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000C68]))
|
||||
#define MCF_INTC0_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000C69]))
|
||||
#define MCF_INTC0_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6A]))
|
||||
#define MCF_INTC0_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6B]))
|
||||
#define MCF_INTC0_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6C]))
|
||||
#define MCF_INTC0_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6D]))
|
||||
#define MCF_INTC0_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6E]))
|
||||
#define MCF_INTC0_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6F]))
|
||||
#define MCF_INTC0_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000C70]))
|
||||
#define MCF_INTC0_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000C71]))
|
||||
#define MCF_INTC0_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000C72]))
|
||||
#define MCF_INTC0_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000C73]))
|
||||
#define MCF_INTC0_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000C74]))
|
||||
#define MCF_INTC0_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000C75]))
|
||||
#define MCF_INTC0_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000C76]))
|
||||
#define MCF_INTC0_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000C77]))
|
||||
#define MCF_INTC0_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000C78]))
|
||||
#define MCF_INTC0_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000C79]))
|
||||
#define MCF_INTC0_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7A]))
|
||||
#define MCF_INTC0_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7B]))
|
||||
#define MCF_INTC0_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7C]))
|
||||
#define MCF_INTC0_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7D]))
|
||||
#define MCF_INTC0_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7E]))
|
||||
#define MCF_INTC0_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7F]))
|
||||
#define MCF_INTC0_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000C40+((x)*0x001)]))
|
||||
#define MCF_INTC0_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE0]))
|
||||
#define MCF_INTC0_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4]))
|
||||
#define MCF_INTC0_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE8]))
|
||||
#define MCF_INTC0_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CEC]))
|
||||
#define MCF_INTC0_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF0]))
|
||||
#define MCF_INTC0_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF4]))
|
||||
#define MCF_INTC0_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF8]))
|
||||
#define MCF_INTC0_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CFC]))
|
||||
#define MCF_INTC0_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4+((x)*0x004)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IPRH */
|
||||
#define MCF_INTC0_IPRH_INT32 (0x00000001)
|
||||
#define MCF_INTC0_IPRH_INT33 (0x00000002)
|
||||
#define MCF_INTC0_IPRH_INT34 (0x00000004)
|
||||
#define MCF_INTC0_IPRH_INT35 (0x00000008)
|
||||
#define MCF_INTC0_IPRH_INT36 (0x00000010)
|
||||
#define MCF_INTC0_IPRH_INT37 (0x00000020)
|
||||
#define MCF_INTC0_IPRH_INT38 (0x00000040)
|
||||
#define MCF_INTC0_IPRH_INT39 (0x00000080)
|
||||
#define MCF_INTC0_IPRH_INT40 (0x00000100)
|
||||
#define MCF_INTC0_IPRH_INT41 (0x00000200)
|
||||
#define MCF_INTC0_IPRH_INT42 (0x00000400)
|
||||
#define MCF_INTC0_IPRH_INT43 (0x00000800)
|
||||
#define MCF_INTC0_IPRH_INT44 (0x00001000)
|
||||
#define MCF_INTC0_IPRH_INT45 (0x00002000)
|
||||
#define MCF_INTC0_IPRH_INT46 (0x00004000)
|
||||
#define MCF_INTC0_IPRH_INT47 (0x00008000)
|
||||
#define MCF_INTC0_IPRH_INT48 (0x00010000)
|
||||
#define MCF_INTC0_IPRH_INT49 (0x00020000)
|
||||
#define MCF_INTC0_IPRH_INT50 (0x00040000)
|
||||
#define MCF_INTC0_IPRH_INT51 (0x00080000)
|
||||
#define MCF_INTC0_IPRH_INT52 (0x00100000)
|
||||
#define MCF_INTC0_IPRH_INT53 (0x00200000)
|
||||
#define MCF_INTC0_IPRH_INT54 (0x00400000)
|
||||
#define MCF_INTC0_IPRH_INT55 (0x00800000)
|
||||
#define MCF_INTC0_IPRH_INT56 (0x01000000)
|
||||
#define MCF_INTC0_IPRH_INT57 (0x02000000)
|
||||
#define MCF_INTC0_IPRH_INT58 (0x04000000)
|
||||
#define MCF_INTC0_IPRH_INT59 (0x08000000)
|
||||
#define MCF_INTC0_IPRH_INT60 (0x10000000)
|
||||
#define MCF_INTC0_IPRH_INT61 (0x20000000)
|
||||
#define MCF_INTC0_IPRH_INT62 (0x40000000)
|
||||
#define MCF_INTC0_IPRH_INT63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IPRL */
|
||||
#define MCF_INTC0_IPRL_INT1 (0x00000002)
|
||||
#define MCF_INTC0_IPRL_INT2 (0x00000004)
|
||||
#define MCF_INTC0_IPRL_INT3 (0x00000008)
|
||||
#define MCF_INTC0_IPRL_INT4 (0x00000010)
|
||||
#define MCF_INTC0_IPRL_INT5 (0x00000020)
|
||||
#define MCF_INTC0_IPRL_INT6 (0x00000040)
|
||||
#define MCF_INTC0_IPRL_INT7 (0x00000080)
|
||||
#define MCF_INTC0_IPRL_INT8 (0x00000100)
|
||||
#define MCF_INTC0_IPRL_INT9 (0x00000200)
|
||||
#define MCF_INTC0_IPRL_INT10 (0x00000400)
|
||||
#define MCF_INTC0_IPRL_INT11 (0x00000800)
|
||||
#define MCF_INTC0_IPRL_INT12 (0x00001000)
|
||||
#define MCF_INTC0_IPRL_INT13 (0x00002000)
|
||||
#define MCF_INTC0_IPRL_INT14 (0x00004000)
|
||||
#define MCF_INTC0_IPRL_INT15 (0x00008000)
|
||||
#define MCF_INTC0_IPRL_INT16 (0x00010000)
|
||||
#define MCF_INTC0_IPRL_INT17 (0x00020000)
|
||||
#define MCF_INTC0_IPRL_INT18 (0x00040000)
|
||||
#define MCF_INTC0_IPRL_INT19 (0x00080000)
|
||||
#define MCF_INTC0_IPRL_INT20 (0x00100000)
|
||||
#define MCF_INTC0_IPRL_INT21 (0x00200000)
|
||||
#define MCF_INTC0_IPRL_INT22 (0x00400000)
|
||||
#define MCF_INTC0_IPRL_INT23 (0x00800000)
|
||||
#define MCF_INTC0_IPRL_INT24 (0x01000000)
|
||||
#define MCF_INTC0_IPRL_INT25 (0x02000000)
|
||||
#define MCF_INTC0_IPRL_INT26 (0x04000000)
|
||||
#define MCF_INTC0_IPRL_INT27 (0x08000000)
|
||||
#define MCF_INTC0_IPRL_INT28 (0x10000000)
|
||||
#define MCF_INTC0_IPRL_INT29 (0x20000000)
|
||||
#define MCF_INTC0_IPRL_INT30 (0x40000000)
|
||||
#define MCF_INTC0_IPRL_INT31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IMRH */
|
||||
#define MCF_INTC0_IMRH_INT_MASK32 (0x00000001)
|
||||
#define MCF_INTC0_IMRH_INT_MASK33 (0x00000002)
|
||||
#define MCF_INTC0_IMRH_INT_MASK34 (0x00000004)
|
||||
#define MCF_INTC0_IMRH_INT_MASK35 (0x00000008)
|
||||
#define MCF_INTC0_IMRH_INT_MASK36 (0x00000010)
|
||||
#define MCF_INTC0_IMRH_INT_MASK37 (0x00000020)
|
||||
#define MCF_INTC0_IMRH_INT_MASK38 (0x00000040)
|
||||
#define MCF_INTC0_IMRH_INT_MASK39 (0x00000080)
|
||||
#define MCF_INTC0_IMRH_INT_MASK40 (0x00000100)
|
||||
#define MCF_INTC0_IMRH_INT_MASK41 (0x00000200)
|
||||
#define MCF_INTC0_IMRH_INT_MASK42 (0x00000400)
|
||||
#define MCF_INTC0_IMRH_INT_MASK43 (0x00000800)
|
||||
#define MCF_INTC0_IMRH_INT_MASK44 (0x00001000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK45 (0x00002000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK46 (0x00004000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK47 (0x00008000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK48 (0x00010000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK49 (0x00020000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK50 (0x00040000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK51 (0x00080000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK52 (0x00100000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK53 (0x00200000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK54 (0x00400000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK55 (0x00800000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK56 (0x01000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK57 (0x02000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK58 (0x04000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK59 (0x08000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK60 (0x10000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK61 (0x20000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK62 (0x40000000)
|
||||
#define MCF_INTC0_IMRH_INT_MASK63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IMRL */
|
||||
#define MCF_INTC0_IMRL_MASKALL (0x00000001)
|
||||
#define MCF_INTC0_IMRL_INT_MASK1 (0x00000002)
|
||||
#define MCF_INTC0_IMRL_INT_MASK2 (0x00000004)
|
||||
#define MCF_INTC0_IMRL_INT_MASK3 (0x00000008)
|
||||
#define MCF_INTC0_IMRL_INT_MASK4 (0x00000010)
|
||||
#define MCF_INTC0_IMRL_INT_MASK5 (0x00000020)
|
||||
#define MCF_INTC0_IMRL_INT_MASK6 (0x00000040)
|
||||
#define MCF_INTC0_IMRL_INT_MASK7 (0x00000080)
|
||||
#define MCF_INTC0_IMRL_INT_MASK8 (0x00000100)
|
||||
#define MCF_INTC0_IMRL_INT_MASK9 (0x00000200)
|
||||
#define MCF_INTC0_IMRL_INT_MASK10 (0x00000400)
|
||||
#define MCF_INTC0_IMRL_INT_MASK11 (0x00000800)
|
||||
#define MCF_INTC0_IMRL_INT_MASK12 (0x00001000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK13 (0x00002000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK14 (0x00004000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK15 (0x00008000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK16 (0x00010000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK17 (0x00020000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK18 (0x00040000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK19 (0x00080000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK20 (0x00100000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK21 (0x00200000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK22 (0x00400000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK23 (0x00800000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK24 (0x01000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK25 (0x02000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK26 (0x04000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK27 (0x08000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK28 (0x10000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK29 (0x20000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK30 (0x40000000)
|
||||
#define MCF_INTC0_IMRL_INT_MASK31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_INTFRCH */
|
||||
#define MCF_INTC0_INTFRCH_INTFRC32 (0x00000001)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC33 (0x00000002)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC34 (0x00000004)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC35 (0x00000008)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC36 (0x00000010)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC37 (0x00000020)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC38 (0x00000040)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC39 (0x00000080)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC40 (0x00000100)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC41 (0x00000200)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC42 (0x00000400)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC43 (0x00000800)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC44 (0x00001000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC45 (0x00002000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC46 (0x00004000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC47 (0x00008000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC48 (0x00010000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC49 (0x00020000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC50 (0x00040000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC51 (0x00080000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC52 (0x00100000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC53 (0x00200000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC54 (0x00400000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC55 (0x00800000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC56 (0x01000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC57 (0x02000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC58 (0x04000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC59 (0x08000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC60 (0x10000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC61 (0x20000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC62 (0x40000000)
|
||||
#define MCF_INTC0_INTFRCH_INTFRC63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_INTFRCL */
|
||||
#define MCF_INTC0_INTFRCL_INTFRC1 (0x00000002)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC2 (0x00000004)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC3 (0x00000008)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC4 (0x00000010)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC5 (0x00000020)
|
||||
#define MCF_INTC0_INTFRCL_INT6 (0x00000040)
|
||||
#define MCF_INTC0_INTFRCL_INT7 (0x00000080)
|
||||
#define MCF_INTC0_INTFRCL_INT8 (0x00000100)
|
||||
#define MCF_INTC0_INTFRCL_INT9 (0x00000200)
|
||||
#define MCF_INTC0_INTFRCL_INT10 (0x00000400)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC11 (0x00000800)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC12 (0x00001000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC13 (0x00002000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC14 (0x00004000)
|
||||
#define MCF_INTC0_INTFRCL_INT15 (0x00008000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC16 (0x00010000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC17 (0x00020000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC18 (0x00040000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC19 (0x00080000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC20 (0x00100000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC21 (0x00200000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC22 (0x00400000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC23 (0x00800000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC24 (0x01000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC25 (0x02000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC26 (0x04000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC27 (0x08000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC28 (0x10000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC29 (0x20000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC30 (0x40000000)
|
||||
#define MCF_INTC0_INTFRCL_INTFRC31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IRLR */
|
||||
#define MCF_INTC0_IRLR_IRQ(x) (((x)&0x7F)<<1)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_IACKLPR */
|
||||
#define MCF_INTC0_IACKLPR_PRI(x) (((x)&0x0F)<<0)
|
||||
#define MCF_INTC0_IACKLPR_LEVEL(x) (((x)&0x07)<<4)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC0_ICRn */
|
||||
#define MCF_INTC0_ICRn_IP(x) (((x)&0x07)<<0)
|
||||
#define MCF_INTC0_ICRn_IL(x) (((x)&0x07)<<3)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_INTC0_H__ */
|
||||
|
|
|
|||
|
|
@ -1,323 +1,323 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_intc1.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_INTC1_H__
|
||||
#define __MCF523X_INTC1_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Interrupt Controller 1 (INTC1)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_INTC1_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000D00]))
|
||||
#define MCF_INTC1_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000D04]))
|
||||
#define MCF_INTC1_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000D08]))
|
||||
#define MCF_INTC1_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000D0C]))
|
||||
#define MCF_INTC1_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000D10]))
|
||||
#define MCF_INTC1_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000D14]))
|
||||
#define MCF_INTC1_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000D18]))
|
||||
#define MCF_INTC1_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000D19]))
|
||||
#define MCF_INTC1_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000D40]))
|
||||
#define MCF_INTC1_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000D41]))
|
||||
#define MCF_INTC1_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000D42]))
|
||||
#define MCF_INTC1_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000D43]))
|
||||
#define MCF_INTC1_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000D44]))
|
||||
#define MCF_INTC1_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000D45]))
|
||||
#define MCF_INTC1_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000D46]))
|
||||
#define MCF_INTC1_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000D47]))
|
||||
#define MCF_INTC1_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000D48]))
|
||||
#define MCF_INTC1_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000D49]))
|
||||
#define MCF_INTC1_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4A]))
|
||||
#define MCF_INTC1_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4B]))
|
||||
#define MCF_INTC1_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4C]))
|
||||
#define MCF_INTC1_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4D]))
|
||||
#define MCF_INTC1_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4E]))
|
||||
#define MCF_INTC1_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4F]))
|
||||
#define MCF_INTC1_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000D50]))
|
||||
#define MCF_INTC1_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000D51]))
|
||||
#define MCF_INTC1_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000D52]))
|
||||
#define MCF_INTC1_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000D53]))
|
||||
#define MCF_INTC1_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000D54]))
|
||||
#define MCF_INTC1_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000D55]))
|
||||
#define MCF_INTC1_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000D56]))
|
||||
#define MCF_INTC1_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000D57]))
|
||||
#define MCF_INTC1_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000D58]))
|
||||
#define MCF_INTC1_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000D59]))
|
||||
#define MCF_INTC1_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5A]))
|
||||
#define MCF_INTC1_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5B]))
|
||||
#define MCF_INTC1_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5C]))
|
||||
#define MCF_INTC1_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5D]))
|
||||
#define MCF_INTC1_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5E]))
|
||||
#define MCF_INTC1_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5F]))
|
||||
#define MCF_INTC1_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000D60]))
|
||||
#define MCF_INTC1_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000D61]))
|
||||
#define MCF_INTC1_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000D62]))
|
||||
#define MCF_INTC1_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000D63]))
|
||||
#define MCF_INTC1_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000D64]))
|
||||
#define MCF_INTC1_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000D65]))
|
||||
#define MCF_INTC1_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000D66]))
|
||||
#define MCF_INTC1_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000D67]))
|
||||
#define MCF_INTC1_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000D68]))
|
||||
#define MCF_INTC1_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000D69]))
|
||||
#define MCF_INTC1_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6A]))
|
||||
#define MCF_INTC1_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6B]))
|
||||
#define MCF_INTC1_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6C]))
|
||||
#define MCF_INTC1_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6D]))
|
||||
#define MCF_INTC1_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6E]))
|
||||
#define MCF_INTC1_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6F]))
|
||||
#define MCF_INTC1_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000D70]))
|
||||
#define MCF_INTC1_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000D71]))
|
||||
#define MCF_INTC1_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000D72]))
|
||||
#define MCF_INTC1_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000D73]))
|
||||
#define MCF_INTC1_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000D74]))
|
||||
#define MCF_INTC1_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000D75]))
|
||||
#define MCF_INTC1_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000D76]))
|
||||
#define MCF_INTC1_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000D77]))
|
||||
#define MCF_INTC1_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000D78]))
|
||||
#define MCF_INTC1_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000D79]))
|
||||
#define MCF_INTC1_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7A]))
|
||||
#define MCF_INTC1_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7B]))
|
||||
#define MCF_INTC1_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7C]))
|
||||
#define MCF_INTC1_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7D]))
|
||||
#define MCF_INTC1_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7E]))
|
||||
#define MCF_INTC1_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7F]))
|
||||
#define MCF_INTC1_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000D40+((x)*0x001)]))
|
||||
#define MCF_INTC1_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE0]))
|
||||
#define MCF_INTC1_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4]))
|
||||
#define MCF_INTC1_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE8]))
|
||||
#define MCF_INTC1_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DEC]))
|
||||
#define MCF_INTC1_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF0]))
|
||||
#define MCF_INTC1_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF4]))
|
||||
#define MCF_INTC1_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF8]))
|
||||
#define MCF_INTC1_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DFC]))
|
||||
#define MCF_INTC1_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4+((x)*0x004)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IPRH */
|
||||
#define MCF_INTC1_IPRH_INT32 (0x00000001)
|
||||
#define MCF_INTC1_IPRH_INT33 (0x00000002)
|
||||
#define MCF_INTC1_IPRH_INT34 (0x00000004)
|
||||
#define MCF_INTC1_IPRH_INT35 (0x00000008)
|
||||
#define MCF_INTC1_IPRH_INT36 (0x00000010)
|
||||
#define MCF_INTC1_IPRH_INT37 (0x00000020)
|
||||
#define MCF_INTC1_IPRH_INT38 (0x00000040)
|
||||
#define MCF_INTC1_IPRH_INT39 (0x00000080)
|
||||
#define MCF_INTC1_IPRH_INT40 (0x00000100)
|
||||
#define MCF_INTC1_IPRH_INT41 (0x00000200)
|
||||
#define MCF_INTC1_IPRH_INT42 (0x00000400)
|
||||
#define MCF_INTC1_IPRH_INT43 (0x00000800)
|
||||
#define MCF_INTC1_IPRH_INT44 (0x00001000)
|
||||
#define MCF_INTC1_IPRH_INT45 (0x00002000)
|
||||
#define MCF_INTC1_IPRH_INT46 (0x00004000)
|
||||
#define MCF_INTC1_IPRH_INT47 (0x00008000)
|
||||
#define MCF_INTC1_IPRH_INT48 (0x00010000)
|
||||
#define MCF_INTC1_IPRH_INT49 (0x00020000)
|
||||
#define MCF_INTC1_IPRH_INT50 (0x00040000)
|
||||
#define MCF_INTC1_IPRH_INT51 (0x00080000)
|
||||
#define MCF_INTC1_IPRH_INT52 (0x00100000)
|
||||
#define MCF_INTC1_IPRH_INT53 (0x00200000)
|
||||
#define MCF_INTC1_IPRH_INT54 (0x00400000)
|
||||
#define MCF_INTC1_IPRH_INT55 (0x00800000)
|
||||
#define MCF_INTC1_IPRH_INT56 (0x01000000)
|
||||
#define MCF_INTC1_IPRH_INT57 (0x02000000)
|
||||
#define MCF_INTC1_IPRH_INT58 (0x04000000)
|
||||
#define MCF_INTC1_IPRH_INT59 (0x08000000)
|
||||
#define MCF_INTC1_IPRH_INT60 (0x10000000)
|
||||
#define MCF_INTC1_IPRH_INT61 (0x20000000)
|
||||
#define MCF_INTC1_IPRH_INT62 (0x40000000)
|
||||
#define MCF_INTC1_IPRH_INT63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IPRL */
|
||||
#define MCF_INTC1_IPRL_INT1 (0x00000002)
|
||||
#define MCF_INTC1_IPRL_INT2 (0x00000004)
|
||||
#define MCF_INTC1_IPRL_INT3 (0x00000008)
|
||||
#define MCF_INTC1_IPRL_INT4 (0x00000010)
|
||||
#define MCF_INTC1_IPRL_INT5 (0x00000020)
|
||||
#define MCF_INTC1_IPRL_INT6 (0x00000040)
|
||||
#define MCF_INTC1_IPRL_INT7 (0x00000080)
|
||||
#define MCF_INTC1_IPRL_INT8 (0x00000100)
|
||||
#define MCF_INTC1_IPRL_INT9 (0x00000200)
|
||||
#define MCF_INTC1_IPRL_INT10 (0x00000400)
|
||||
#define MCF_INTC1_IPRL_INT11 (0x00000800)
|
||||
#define MCF_INTC1_IPRL_INT12 (0x00001000)
|
||||
#define MCF_INTC1_IPRL_INT13 (0x00002000)
|
||||
#define MCF_INTC1_IPRL_INT14 (0x00004000)
|
||||
#define MCF_INTC1_IPRL_INT15 (0x00008000)
|
||||
#define MCF_INTC1_IPRL_INT16 (0x00010000)
|
||||
#define MCF_INTC1_IPRL_INT17 (0x00020000)
|
||||
#define MCF_INTC1_IPRL_INT18 (0x00040000)
|
||||
#define MCF_INTC1_IPRL_INT19 (0x00080000)
|
||||
#define MCF_INTC1_IPRL_INT20 (0x00100000)
|
||||
#define MCF_INTC1_IPRL_INT21 (0x00200000)
|
||||
#define MCF_INTC1_IPRL_INT22 (0x00400000)
|
||||
#define MCF_INTC1_IPRL_INT23 (0x00800000)
|
||||
#define MCF_INTC1_IPRL_INT24 (0x01000000)
|
||||
#define MCF_INTC1_IPRL_INT25 (0x02000000)
|
||||
#define MCF_INTC1_IPRL_INT26 (0x04000000)
|
||||
#define MCF_INTC1_IPRL_INT27 (0x08000000)
|
||||
#define MCF_INTC1_IPRL_INT28 (0x10000000)
|
||||
#define MCF_INTC1_IPRL_INT29 (0x20000000)
|
||||
#define MCF_INTC1_IPRL_INT30 (0x40000000)
|
||||
#define MCF_INTC1_IPRL_INT31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IMRH */
|
||||
#define MCF_INTC1_IMRH_INT_MASK32 (0x00000001)
|
||||
#define MCF_INTC1_IMRH_INT_MASK33 (0x00000002)
|
||||
#define MCF_INTC1_IMRH_INT_MASK34 (0x00000004)
|
||||
#define MCF_INTC1_IMRH_INT_MASK35 (0x00000008)
|
||||
#define MCF_INTC1_IMRH_INT_MASK36 (0x00000010)
|
||||
#define MCF_INTC1_IMRH_INT_MASK37 (0x00000020)
|
||||
#define MCF_INTC1_IMRH_INT_MASK38 (0x00000040)
|
||||
#define MCF_INTC1_IMRH_INT_MASK39 (0x00000080)
|
||||
#define MCF_INTC1_IMRH_INT_MASK40 (0x00000100)
|
||||
#define MCF_INTC1_IMRH_INT_MASK41 (0x00000200)
|
||||
#define MCF_INTC1_IMRH_INT_MASK42 (0x00000400)
|
||||
#define MCF_INTC1_IMRH_INT_MASK43 (0x00000800)
|
||||
#define MCF_INTC1_IMRH_INT_MASK44 (0x00001000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK45 (0x00002000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK46 (0x00004000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK47 (0x00008000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK48 (0x00010000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK49 (0x00020000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK50 (0x00040000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK51 (0x00080000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK52 (0x00100000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK53 (0x00200000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK54 (0x00400000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK55 (0x00800000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK56 (0x01000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK57 (0x02000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK58 (0x04000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK59 (0x08000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK60 (0x10000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK61 (0x20000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK62 (0x40000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IMRL */
|
||||
#define MCF_INTC1_IMRL_MASKALL (0x00000001)
|
||||
#define MCF_INTC1_IMRL_INT_MASK1 (0x00000002)
|
||||
#define MCF_INTC1_IMRL_INT_MASK2 (0x00000004)
|
||||
#define MCF_INTC1_IMRL_INT_MASK3 (0x00000008)
|
||||
#define MCF_INTC1_IMRL_INT_MASK4 (0x00000010)
|
||||
#define MCF_INTC1_IMRL_INT_MASK5 (0x00000020)
|
||||
#define MCF_INTC1_IMRL_INT_MASK6 (0x00000040)
|
||||
#define MCF_INTC1_IMRL_INT_MASK7 (0x00000080)
|
||||
#define MCF_INTC1_IMRL_INT_MASK8 (0x00000100)
|
||||
#define MCF_INTC1_IMRL_INT_MASK9 (0x00000200)
|
||||
#define MCF_INTC1_IMRL_INT_MASK10 (0x00000400)
|
||||
#define MCF_INTC1_IMRL_INT_MASK11 (0x00000800)
|
||||
#define MCF_INTC1_IMRL_INT_MASK12 (0x00001000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK13 (0x00002000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK14 (0x00004000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK15 (0x00008000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK16 (0x00010000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK17 (0x00020000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK18 (0x00040000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK19 (0x00080000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK20 (0x00100000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK21 (0x00200000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK22 (0x00400000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK23 (0x00800000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK24 (0x01000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK25 (0x02000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK26 (0x04000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK27 (0x08000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK28 (0x10000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK29 (0x20000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK30 (0x40000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_INTFRCH */
|
||||
#define MCF_INTC1_INTFRCH_INTFRC32 (0x00000001)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC33 (0x00000002)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC34 (0x00000004)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC35 (0x00000008)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC36 (0x00000010)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC37 (0x00000020)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC38 (0x00000040)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC39 (0x00000080)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC40 (0x00000100)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC41 (0x00000200)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC42 (0x00000400)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC43 (0x00000800)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC44 (0x00001000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC45 (0x00002000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC46 (0x00004000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC47 (0x00008000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC48 (0x00010000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC49 (0x00020000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC50 (0x00040000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC51 (0x00080000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC52 (0x00100000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC53 (0x00200000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC54 (0x00400000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC55 (0x00800000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC56 (0x01000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC57 (0x02000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC58 (0x04000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC59 (0x08000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC60 (0x10000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC61 (0x20000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC62 (0x40000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_INTFRCL */
|
||||
#define MCF_INTC1_INTFRCL_INTFRC1 (0x00000002)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC2 (0x00000004)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC3 (0x00000008)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC4 (0x00000010)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC5 (0x00000020)
|
||||
#define MCF_INTC1_INTFRCL_INT6 (0x00000040)
|
||||
#define MCF_INTC1_INTFRCL_INT7 (0x00000080)
|
||||
#define MCF_INTC1_INTFRCL_INT8 (0x00000100)
|
||||
#define MCF_INTC1_INTFRCL_INT9 (0x00000200)
|
||||
#define MCF_INTC1_INTFRCL_INT10 (0x00000400)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC11 (0x00000800)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC12 (0x00001000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC13 (0x00002000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC14 (0x00004000)
|
||||
#define MCF_INTC1_INTFRCL_INT15 (0x00008000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC16 (0x00010000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC17 (0x00020000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC18 (0x00040000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC19 (0x00080000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC20 (0x00100000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC21 (0x00200000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC22 (0x00400000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC23 (0x00800000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC24 (0x01000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC25 (0x02000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC26 (0x04000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC27 (0x08000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC28 (0x10000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC29 (0x20000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC30 (0x40000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IRLR */
|
||||
#define MCF_INTC1_IRLR_IRQ(x) (((x)&0x7F)<<1)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IACKLPR */
|
||||
#define MCF_INTC1_IACKLPR_PRI(x) (((x)&0x0F)<<0)
|
||||
#define MCF_INTC1_IACKLPR_LEVEL(x) (((x)&0x07)<<4)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_ICRn */
|
||||
#define MCF_INTC1_ICRn_IP(x) (((x)&0x07)<<0)
|
||||
#define MCF_INTC1_ICRn_IL(x) (((x)&0x07)<<3)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_INTC1_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_intc1.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_INTC1_H__
|
||||
#define __MCF523X_INTC1_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Interrupt Controller 1 (INTC1)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_INTC1_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000D00]))
|
||||
#define MCF_INTC1_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000D04]))
|
||||
#define MCF_INTC1_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000D08]))
|
||||
#define MCF_INTC1_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000D0C]))
|
||||
#define MCF_INTC1_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000D10]))
|
||||
#define MCF_INTC1_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000D14]))
|
||||
#define MCF_INTC1_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000D18]))
|
||||
#define MCF_INTC1_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000D19]))
|
||||
#define MCF_INTC1_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000D40]))
|
||||
#define MCF_INTC1_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000D41]))
|
||||
#define MCF_INTC1_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000D42]))
|
||||
#define MCF_INTC1_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000D43]))
|
||||
#define MCF_INTC1_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000D44]))
|
||||
#define MCF_INTC1_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000D45]))
|
||||
#define MCF_INTC1_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000D46]))
|
||||
#define MCF_INTC1_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000D47]))
|
||||
#define MCF_INTC1_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000D48]))
|
||||
#define MCF_INTC1_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000D49]))
|
||||
#define MCF_INTC1_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4A]))
|
||||
#define MCF_INTC1_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4B]))
|
||||
#define MCF_INTC1_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4C]))
|
||||
#define MCF_INTC1_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4D]))
|
||||
#define MCF_INTC1_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4E]))
|
||||
#define MCF_INTC1_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4F]))
|
||||
#define MCF_INTC1_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000D50]))
|
||||
#define MCF_INTC1_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000D51]))
|
||||
#define MCF_INTC1_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000D52]))
|
||||
#define MCF_INTC1_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000D53]))
|
||||
#define MCF_INTC1_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000D54]))
|
||||
#define MCF_INTC1_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000D55]))
|
||||
#define MCF_INTC1_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000D56]))
|
||||
#define MCF_INTC1_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000D57]))
|
||||
#define MCF_INTC1_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000D58]))
|
||||
#define MCF_INTC1_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000D59]))
|
||||
#define MCF_INTC1_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5A]))
|
||||
#define MCF_INTC1_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5B]))
|
||||
#define MCF_INTC1_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5C]))
|
||||
#define MCF_INTC1_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5D]))
|
||||
#define MCF_INTC1_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5E]))
|
||||
#define MCF_INTC1_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5F]))
|
||||
#define MCF_INTC1_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000D60]))
|
||||
#define MCF_INTC1_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000D61]))
|
||||
#define MCF_INTC1_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000D62]))
|
||||
#define MCF_INTC1_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000D63]))
|
||||
#define MCF_INTC1_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000D64]))
|
||||
#define MCF_INTC1_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000D65]))
|
||||
#define MCF_INTC1_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000D66]))
|
||||
#define MCF_INTC1_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000D67]))
|
||||
#define MCF_INTC1_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000D68]))
|
||||
#define MCF_INTC1_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000D69]))
|
||||
#define MCF_INTC1_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6A]))
|
||||
#define MCF_INTC1_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6B]))
|
||||
#define MCF_INTC1_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6C]))
|
||||
#define MCF_INTC1_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6D]))
|
||||
#define MCF_INTC1_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6E]))
|
||||
#define MCF_INTC1_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6F]))
|
||||
#define MCF_INTC1_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000D70]))
|
||||
#define MCF_INTC1_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000D71]))
|
||||
#define MCF_INTC1_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000D72]))
|
||||
#define MCF_INTC1_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000D73]))
|
||||
#define MCF_INTC1_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000D74]))
|
||||
#define MCF_INTC1_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000D75]))
|
||||
#define MCF_INTC1_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000D76]))
|
||||
#define MCF_INTC1_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000D77]))
|
||||
#define MCF_INTC1_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000D78]))
|
||||
#define MCF_INTC1_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000D79]))
|
||||
#define MCF_INTC1_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7A]))
|
||||
#define MCF_INTC1_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7B]))
|
||||
#define MCF_INTC1_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7C]))
|
||||
#define MCF_INTC1_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7D]))
|
||||
#define MCF_INTC1_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7E]))
|
||||
#define MCF_INTC1_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7F]))
|
||||
#define MCF_INTC1_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000D40+((x)*0x001)]))
|
||||
#define MCF_INTC1_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE0]))
|
||||
#define MCF_INTC1_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4]))
|
||||
#define MCF_INTC1_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE8]))
|
||||
#define MCF_INTC1_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DEC]))
|
||||
#define MCF_INTC1_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF0]))
|
||||
#define MCF_INTC1_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF4]))
|
||||
#define MCF_INTC1_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF8]))
|
||||
#define MCF_INTC1_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DFC]))
|
||||
#define MCF_INTC1_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4+((x)*0x004)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IPRH */
|
||||
#define MCF_INTC1_IPRH_INT32 (0x00000001)
|
||||
#define MCF_INTC1_IPRH_INT33 (0x00000002)
|
||||
#define MCF_INTC1_IPRH_INT34 (0x00000004)
|
||||
#define MCF_INTC1_IPRH_INT35 (0x00000008)
|
||||
#define MCF_INTC1_IPRH_INT36 (0x00000010)
|
||||
#define MCF_INTC1_IPRH_INT37 (0x00000020)
|
||||
#define MCF_INTC1_IPRH_INT38 (0x00000040)
|
||||
#define MCF_INTC1_IPRH_INT39 (0x00000080)
|
||||
#define MCF_INTC1_IPRH_INT40 (0x00000100)
|
||||
#define MCF_INTC1_IPRH_INT41 (0x00000200)
|
||||
#define MCF_INTC1_IPRH_INT42 (0x00000400)
|
||||
#define MCF_INTC1_IPRH_INT43 (0x00000800)
|
||||
#define MCF_INTC1_IPRH_INT44 (0x00001000)
|
||||
#define MCF_INTC1_IPRH_INT45 (0x00002000)
|
||||
#define MCF_INTC1_IPRH_INT46 (0x00004000)
|
||||
#define MCF_INTC1_IPRH_INT47 (0x00008000)
|
||||
#define MCF_INTC1_IPRH_INT48 (0x00010000)
|
||||
#define MCF_INTC1_IPRH_INT49 (0x00020000)
|
||||
#define MCF_INTC1_IPRH_INT50 (0x00040000)
|
||||
#define MCF_INTC1_IPRH_INT51 (0x00080000)
|
||||
#define MCF_INTC1_IPRH_INT52 (0x00100000)
|
||||
#define MCF_INTC1_IPRH_INT53 (0x00200000)
|
||||
#define MCF_INTC1_IPRH_INT54 (0x00400000)
|
||||
#define MCF_INTC1_IPRH_INT55 (0x00800000)
|
||||
#define MCF_INTC1_IPRH_INT56 (0x01000000)
|
||||
#define MCF_INTC1_IPRH_INT57 (0x02000000)
|
||||
#define MCF_INTC1_IPRH_INT58 (0x04000000)
|
||||
#define MCF_INTC1_IPRH_INT59 (0x08000000)
|
||||
#define MCF_INTC1_IPRH_INT60 (0x10000000)
|
||||
#define MCF_INTC1_IPRH_INT61 (0x20000000)
|
||||
#define MCF_INTC1_IPRH_INT62 (0x40000000)
|
||||
#define MCF_INTC1_IPRH_INT63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IPRL */
|
||||
#define MCF_INTC1_IPRL_INT1 (0x00000002)
|
||||
#define MCF_INTC1_IPRL_INT2 (0x00000004)
|
||||
#define MCF_INTC1_IPRL_INT3 (0x00000008)
|
||||
#define MCF_INTC1_IPRL_INT4 (0x00000010)
|
||||
#define MCF_INTC1_IPRL_INT5 (0x00000020)
|
||||
#define MCF_INTC1_IPRL_INT6 (0x00000040)
|
||||
#define MCF_INTC1_IPRL_INT7 (0x00000080)
|
||||
#define MCF_INTC1_IPRL_INT8 (0x00000100)
|
||||
#define MCF_INTC1_IPRL_INT9 (0x00000200)
|
||||
#define MCF_INTC1_IPRL_INT10 (0x00000400)
|
||||
#define MCF_INTC1_IPRL_INT11 (0x00000800)
|
||||
#define MCF_INTC1_IPRL_INT12 (0x00001000)
|
||||
#define MCF_INTC1_IPRL_INT13 (0x00002000)
|
||||
#define MCF_INTC1_IPRL_INT14 (0x00004000)
|
||||
#define MCF_INTC1_IPRL_INT15 (0x00008000)
|
||||
#define MCF_INTC1_IPRL_INT16 (0x00010000)
|
||||
#define MCF_INTC1_IPRL_INT17 (0x00020000)
|
||||
#define MCF_INTC1_IPRL_INT18 (0x00040000)
|
||||
#define MCF_INTC1_IPRL_INT19 (0x00080000)
|
||||
#define MCF_INTC1_IPRL_INT20 (0x00100000)
|
||||
#define MCF_INTC1_IPRL_INT21 (0x00200000)
|
||||
#define MCF_INTC1_IPRL_INT22 (0x00400000)
|
||||
#define MCF_INTC1_IPRL_INT23 (0x00800000)
|
||||
#define MCF_INTC1_IPRL_INT24 (0x01000000)
|
||||
#define MCF_INTC1_IPRL_INT25 (0x02000000)
|
||||
#define MCF_INTC1_IPRL_INT26 (0x04000000)
|
||||
#define MCF_INTC1_IPRL_INT27 (0x08000000)
|
||||
#define MCF_INTC1_IPRL_INT28 (0x10000000)
|
||||
#define MCF_INTC1_IPRL_INT29 (0x20000000)
|
||||
#define MCF_INTC1_IPRL_INT30 (0x40000000)
|
||||
#define MCF_INTC1_IPRL_INT31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IMRH */
|
||||
#define MCF_INTC1_IMRH_INT_MASK32 (0x00000001)
|
||||
#define MCF_INTC1_IMRH_INT_MASK33 (0x00000002)
|
||||
#define MCF_INTC1_IMRH_INT_MASK34 (0x00000004)
|
||||
#define MCF_INTC1_IMRH_INT_MASK35 (0x00000008)
|
||||
#define MCF_INTC1_IMRH_INT_MASK36 (0x00000010)
|
||||
#define MCF_INTC1_IMRH_INT_MASK37 (0x00000020)
|
||||
#define MCF_INTC1_IMRH_INT_MASK38 (0x00000040)
|
||||
#define MCF_INTC1_IMRH_INT_MASK39 (0x00000080)
|
||||
#define MCF_INTC1_IMRH_INT_MASK40 (0x00000100)
|
||||
#define MCF_INTC1_IMRH_INT_MASK41 (0x00000200)
|
||||
#define MCF_INTC1_IMRH_INT_MASK42 (0x00000400)
|
||||
#define MCF_INTC1_IMRH_INT_MASK43 (0x00000800)
|
||||
#define MCF_INTC1_IMRH_INT_MASK44 (0x00001000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK45 (0x00002000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK46 (0x00004000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK47 (0x00008000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK48 (0x00010000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK49 (0x00020000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK50 (0x00040000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK51 (0x00080000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK52 (0x00100000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK53 (0x00200000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK54 (0x00400000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK55 (0x00800000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK56 (0x01000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK57 (0x02000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK58 (0x04000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK59 (0x08000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK60 (0x10000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK61 (0x20000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK62 (0x40000000)
|
||||
#define MCF_INTC1_IMRH_INT_MASK63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IMRL */
|
||||
#define MCF_INTC1_IMRL_MASKALL (0x00000001)
|
||||
#define MCF_INTC1_IMRL_INT_MASK1 (0x00000002)
|
||||
#define MCF_INTC1_IMRL_INT_MASK2 (0x00000004)
|
||||
#define MCF_INTC1_IMRL_INT_MASK3 (0x00000008)
|
||||
#define MCF_INTC1_IMRL_INT_MASK4 (0x00000010)
|
||||
#define MCF_INTC1_IMRL_INT_MASK5 (0x00000020)
|
||||
#define MCF_INTC1_IMRL_INT_MASK6 (0x00000040)
|
||||
#define MCF_INTC1_IMRL_INT_MASK7 (0x00000080)
|
||||
#define MCF_INTC1_IMRL_INT_MASK8 (0x00000100)
|
||||
#define MCF_INTC1_IMRL_INT_MASK9 (0x00000200)
|
||||
#define MCF_INTC1_IMRL_INT_MASK10 (0x00000400)
|
||||
#define MCF_INTC1_IMRL_INT_MASK11 (0x00000800)
|
||||
#define MCF_INTC1_IMRL_INT_MASK12 (0x00001000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK13 (0x00002000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK14 (0x00004000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK15 (0x00008000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK16 (0x00010000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK17 (0x00020000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK18 (0x00040000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK19 (0x00080000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK20 (0x00100000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK21 (0x00200000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK22 (0x00400000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK23 (0x00800000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK24 (0x01000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK25 (0x02000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK26 (0x04000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK27 (0x08000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK28 (0x10000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK29 (0x20000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK30 (0x40000000)
|
||||
#define MCF_INTC1_IMRL_INT_MASK31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_INTFRCH */
|
||||
#define MCF_INTC1_INTFRCH_INTFRC32 (0x00000001)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC33 (0x00000002)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC34 (0x00000004)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC35 (0x00000008)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC36 (0x00000010)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC37 (0x00000020)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC38 (0x00000040)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC39 (0x00000080)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC40 (0x00000100)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC41 (0x00000200)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC42 (0x00000400)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC43 (0x00000800)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC44 (0x00001000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC45 (0x00002000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC46 (0x00004000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC47 (0x00008000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC48 (0x00010000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC49 (0x00020000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC50 (0x00040000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC51 (0x00080000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC52 (0x00100000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC53 (0x00200000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC54 (0x00400000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC55 (0x00800000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC56 (0x01000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC57 (0x02000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC58 (0x04000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC59 (0x08000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC60 (0x10000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC61 (0x20000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC62 (0x40000000)
|
||||
#define MCF_INTC1_INTFRCH_INTFRC63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_INTFRCL */
|
||||
#define MCF_INTC1_INTFRCL_INTFRC1 (0x00000002)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC2 (0x00000004)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC3 (0x00000008)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC4 (0x00000010)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC5 (0x00000020)
|
||||
#define MCF_INTC1_INTFRCL_INT6 (0x00000040)
|
||||
#define MCF_INTC1_INTFRCL_INT7 (0x00000080)
|
||||
#define MCF_INTC1_INTFRCL_INT8 (0x00000100)
|
||||
#define MCF_INTC1_INTFRCL_INT9 (0x00000200)
|
||||
#define MCF_INTC1_INTFRCL_INT10 (0x00000400)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC11 (0x00000800)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC12 (0x00001000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC13 (0x00002000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC14 (0x00004000)
|
||||
#define MCF_INTC1_INTFRCL_INT15 (0x00008000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC16 (0x00010000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC17 (0x00020000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC18 (0x00040000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC19 (0x00080000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC20 (0x00100000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC21 (0x00200000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC22 (0x00400000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC23 (0x00800000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC24 (0x01000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC25 (0x02000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC26 (0x04000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC27 (0x08000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC28 (0x10000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC29 (0x20000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC30 (0x40000000)
|
||||
#define MCF_INTC1_INTFRCL_INTFRC31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IRLR */
|
||||
#define MCF_INTC1_IRLR_IRQ(x) (((x)&0x7F)<<1)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_IACKLPR */
|
||||
#define MCF_INTC1_IACKLPR_PRI(x) (((x)&0x0F)<<0)
|
||||
#define MCF_INTC1_IACKLPR_LEVEL(x) (((x)&0x07)<<4)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC1_ICRn */
|
||||
#define MCF_INTC1_ICRn_IP(x) (((x)&0x07)<<0)
|
||||
#define MCF_INTC1_ICRn_IL(x) (((x)&0x07)<<3)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_INTC1_H__ */
|
||||
|
|
|
|||
|
|
@ -1,101 +1,101 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_mdha.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_MDHA_H__
|
||||
#define __MCF523X_MDHA_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Message Digest Hardware Accelerator (MDHA)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_MDHA_MDMR (*(vuint32*)(void*)(&__IPSBAR[0x190000]))
|
||||
#define MCF_MDHA_MDCR (*(vuint32*)(void*)(&__IPSBAR[0x190004]))
|
||||
#define MCF_MDHA_MDCMR (*(vuint32*)(void*)(&__IPSBAR[0x190008]))
|
||||
#define MCF_MDHA_MDSR (*(vuint32*)(void*)(&__IPSBAR[0x19000C]))
|
||||
#define MCF_MDHA_MDISR (*(vuint32*)(void*)(&__IPSBAR[0x190010]))
|
||||
#define MCF_MDHA_MDIMR (*(vuint32*)(void*)(&__IPSBAR[0x190014]))
|
||||
#define MCF_MDHA_MDDSR (*(vuint32*)(void*)(&__IPSBAR[0x19001C]))
|
||||
#define MCF_MDHA_MDIN (*(vuint32*)(void*)(&__IPSBAR[0x190020]))
|
||||
#define MCF_MDHA_MDA0 (*(vuint32*)(void*)(&__IPSBAR[0x190030]))
|
||||
#define MCF_MDHA_MDB0 (*(vuint32*)(void*)(&__IPSBAR[0x190034]))
|
||||
#define MCF_MDHA_MDC0 (*(vuint32*)(void*)(&__IPSBAR[0x190038]))
|
||||
#define MCF_MDHA_MDD0 (*(vuint32*)(void*)(&__IPSBAR[0x19003C]))
|
||||
#define MCF_MDHA_MDE0 (*(vuint32*)(void*)(&__IPSBAR[0x190040]))
|
||||
#define MCF_MDHA_MDMDS (*(vuint32*)(void*)(&__IPSBAR[0x190044]))
|
||||
#define MCF_MDHA_MDA1 (*(vuint32*)(void*)(&__IPSBAR[0x190070]))
|
||||
#define MCF_MDHA_MDB1 (*(vuint32*)(void*)(&__IPSBAR[0x190074]))
|
||||
#define MCF_MDHA_MDC1 (*(vuint32*)(void*)(&__IPSBAR[0x190078]))
|
||||
#define MCF_MDHA_MDD1 (*(vuint32*)(void*)(&__IPSBAR[0x19007C]))
|
||||
#define MCF_MDHA_MDE1 (*(vuint32*)(void*)(&__IPSBAR[0x190080]))
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDMR */
|
||||
#define MCF_MDHA_MDMR_ALG (0x00000001)
|
||||
#define MCF_MDHA_MDMR_PDATA (0x00000004)
|
||||
#define MCF_MDHA_MDMR_MAC(x) (((x)&0x00000003)<<3)
|
||||
#define MCF_MDHA_MDMR_INIT (0x00000020)
|
||||
#define MCF_MDHA_MDMR_IPAD (0x00000040)
|
||||
#define MCF_MDHA_MDMR_OPAD (0x00000080)
|
||||
#define MCF_MDHA_MDMR_SWAP (0x00000100)
|
||||
#define MCF_MDHA_MDMR_MACFULL (0x00000200)
|
||||
#define MCF_MDHA_MDMR_SSL (0x00000400)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDCR */
|
||||
#define MCF_MDHA_MDCR_IE (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDCMR */
|
||||
#define MCF_MDHA_MDCMR_SWR (0x00000001)
|
||||
#define MCF_MDHA_MDCMR_RI (0x00000002)
|
||||
#define MCF_MDHA_MDCMR_CI (0x00000004)
|
||||
#define MCF_MDHA_MDCMR_GO (0x00000008)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDSR */
|
||||
#define MCF_MDHA_MDSR_INT (0x00000001)
|
||||
#define MCF_MDHA_MDSR_DONE (0x00000002)
|
||||
#define MCF_MDHA_MDSR_ERR (0x00000004)
|
||||
#define MCF_MDHA_MDSR_RD (0x00000008)
|
||||
#define MCF_MDHA_MDSR_BUSY (0x00000010)
|
||||
#define MCF_MDHA_MDSR_END (0x00000020)
|
||||
#define MCF_MDHA_MDSR_HSH (0x00000040)
|
||||
#define MCF_MDHA_MDSR_GNW (0x00000080)
|
||||
#define MCF_MDHA_MDSR_FS(x) (((x)&0x00000007)<<8)
|
||||
#define MCF_MDHA_MDSR_APD(x) (((x)&0x00000007)<<13)
|
||||
#define MCF_MDHA_MDSR_IFL(x) (((x)&0x000000FF)<<16)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDIR */
|
||||
#define MCF_MDHA_MDIR_IFO (0x00000001)
|
||||
#define MCF_MDHA_MDIR_NON (0x00000004)
|
||||
#define MCF_MDHA_MDIR_IME (0x00000010)
|
||||
#define MCF_MDHA_MDIR_IDS (0x00000020)
|
||||
#define MCF_MDHA_MDIR_RMDP (0x00000080)
|
||||
#define MCF_MDHA_MDIR_ERE (0x00000100)
|
||||
#define MCF_MDHA_MDIR_GTDS (0x00000200)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDIMR */
|
||||
#define MCF_MDHA_MDIMR_IFO (0x00000001)
|
||||
#define MCF_MDHA_MDIMR_NON (0x00000004)
|
||||
#define MCF_MDHA_MDIMR_IME (0x00000010)
|
||||
#define MCF_MDHA_MDIMR_IDS (0x00000020)
|
||||
#define MCF_MDHA_MDIMR_RMDP (0x00000080)
|
||||
#define MCF_MDHA_MDIMR_ERE (0x00000100)
|
||||
#define MCF_MDHA_MDIMR_GTDS (0x00000200)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDDSR */
|
||||
#define MCF_MDHA_MDDSR_DATASIZE(x) (((x)&0x1FFFFFFF)<<0)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_MDHA_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_mdha.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_MDHA_H__
|
||||
#define __MCF523X_MDHA_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Message Digest Hardware Accelerator (MDHA)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_MDHA_MDMR (*(vuint32*)(void*)(&__IPSBAR[0x190000]))
|
||||
#define MCF_MDHA_MDCR (*(vuint32*)(void*)(&__IPSBAR[0x190004]))
|
||||
#define MCF_MDHA_MDCMR (*(vuint32*)(void*)(&__IPSBAR[0x190008]))
|
||||
#define MCF_MDHA_MDSR (*(vuint32*)(void*)(&__IPSBAR[0x19000C]))
|
||||
#define MCF_MDHA_MDISR (*(vuint32*)(void*)(&__IPSBAR[0x190010]))
|
||||
#define MCF_MDHA_MDIMR (*(vuint32*)(void*)(&__IPSBAR[0x190014]))
|
||||
#define MCF_MDHA_MDDSR (*(vuint32*)(void*)(&__IPSBAR[0x19001C]))
|
||||
#define MCF_MDHA_MDIN (*(vuint32*)(void*)(&__IPSBAR[0x190020]))
|
||||
#define MCF_MDHA_MDA0 (*(vuint32*)(void*)(&__IPSBAR[0x190030]))
|
||||
#define MCF_MDHA_MDB0 (*(vuint32*)(void*)(&__IPSBAR[0x190034]))
|
||||
#define MCF_MDHA_MDC0 (*(vuint32*)(void*)(&__IPSBAR[0x190038]))
|
||||
#define MCF_MDHA_MDD0 (*(vuint32*)(void*)(&__IPSBAR[0x19003C]))
|
||||
#define MCF_MDHA_MDE0 (*(vuint32*)(void*)(&__IPSBAR[0x190040]))
|
||||
#define MCF_MDHA_MDMDS (*(vuint32*)(void*)(&__IPSBAR[0x190044]))
|
||||
#define MCF_MDHA_MDA1 (*(vuint32*)(void*)(&__IPSBAR[0x190070]))
|
||||
#define MCF_MDHA_MDB1 (*(vuint32*)(void*)(&__IPSBAR[0x190074]))
|
||||
#define MCF_MDHA_MDC1 (*(vuint32*)(void*)(&__IPSBAR[0x190078]))
|
||||
#define MCF_MDHA_MDD1 (*(vuint32*)(void*)(&__IPSBAR[0x19007C]))
|
||||
#define MCF_MDHA_MDE1 (*(vuint32*)(void*)(&__IPSBAR[0x190080]))
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDMR */
|
||||
#define MCF_MDHA_MDMR_ALG (0x00000001)
|
||||
#define MCF_MDHA_MDMR_PDATA (0x00000004)
|
||||
#define MCF_MDHA_MDMR_MAC(x) (((x)&0x00000003)<<3)
|
||||
#define MCF_MDHA_MDMR_INIT (0x00000020)
|
||||
#define MCF_MDHA_MDMR_IPAD (0x00000040)
|
||||
#define MCF_MDHA_MDMR_OPAD (0x00000080)
|
||||
#define MCF_MDHA_MDMR_SWAP (0x00000100)
|
||||
#define MCF_MDHA_MDMR_MACFULL (0x00000200)
|
||||
#define MCF_MDHA_MDMR_SSL (0x00000400)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDCR */
|
||||
#define MCF_MDHA_MDCR_IE (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDCMR */
|
||||
#define MCF_MDHA_MDCMR_SWR (0x00000001)
|
||||
#define MCF_MDHA_MDCMR_RI (0x00000002)
|
||||
#define MCF_MDHA_MDCMR_CI (0x00000004)
|
||||
#define MCF_MDHA_MDCMR_GO (0x00000008)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDSR */
|
||||
#define MCF_MDHA_MDSR_INT (0x00000001)
|
||||
#define MCF_MDHA_MDSR_DONE (0x00000002)
|
||||
#define MCF_MDHA_MDSR_ERR (0x00000004)
|
||||
#define MCF_MDHA_MDSR_RD (0x00000008)
|
||||
#define MCF_MDHA_MDSR_BUSY (0x00000010)
|
||||
#define MCF_MDHA_MDSR_END (0x00000020)
|
||||
#define MCF_MDHA_MDSR_HSH (0x00000040)
|
||||
#define MCF_MDHA_MDSR_GNW (0x00000080)
|
||||
#define MCF_MDHA_MDSR_FS(x) (((x)&0x00000007)<<8)
|
||||
#define MCF_MDHA_MDSR_APD(x) (((x)&0x00000007)<<13)
|
||||
#define MCF_MDHA_MDSR_IFL(x) (((x)&0x000000FF)<<16)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDIR */
|
||||
#define MCF_MDHA_MDIR_IFO (0x00000001)
|
||||
#define MCF_MDHA_MDIR_NON (0x00000004)
|
||||
#define MCF_MDHA_MDIR_IME (0x00000010)
|
||||
#define MCF_MDHA_MDIR_IDS (0x00000020)
|
||||
#define MCF_MDHA_MDIR_RMDP (0x00000080)
|
||||
#define MCF_MDHA_MDIR_ERE (0x00000100)
|
||||
#define MCF_MDHA_MDIR_GTDS (0x00000200)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDIMR */
|
||||
#define MCF_MDHA_MDIMR_IFO (0x00000001)
|
||||
#define MCF_MDHA_MDIMR_NON (0x00000004)
|
||||
#define MCF_MDHA_MDIMR_IME (0x00000010)
|
||||
#define MCF_MDHA_MDIMR_IDS (0x00000020)
|
||||
#define MCF_MDHA_MDIMR_RMDP (0x00000080)
|
||||
#define MCF_MDHA_MDIMR_ERE (0x00000100)
|
||||
#define MCF_MDHA_MDIMR_GTDS (0x00000200)
|
||||
|
||||
/* Bit definitions and macros for MCF_MDHA_MDDSR */
|
||||
#define MCF_MDHA_MDDSR_DATASIZE(x) (((x)&0x1FFFFFFF)<<0)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_MDHA_H__ */
|
||||
|
|
|
|||
|
|
@ -1,89 +1,89 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_pit.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_PIT_H__
|
||||
#define __MCF523X_PIT_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Programmable Interrupt Timer Modules (PIT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PIT_PCSR0 (*(vuint16*)(void*)(&__IPSBAR[0x150000]))
|
||||
#define MCF_PIT_PMR0 (*(vuint16*)(void*)(&__IPSBAR[0x150002]))
|
||||
#define MCF_PIT_PCNTR0 (*(vuint16*)(void*)(&__IPSBAR[0x150004]))
|
||||
#define MCF_PIT_PCSR1 (*(vuint16*)(void*)(&__IPSBAR[0x160000]))
|
||||
#define MCF_PIT_PMR1 (*(vuint16*)(void*)(&__IPSBAR[0x160002]))
|
||||
#define MCF_PIT_PCNTR1 (*(vuint16*)(void*)(&__IPSBAR[0x160004]))
|
||||
#define MCF_PIT_PCSR2 (*(vuint16*)(void*)(&__IPSBAR[0x170000]))
|
||||
#define MCF_PIT_PMR2 (*(vuint16*)(void*)(&__IPSBAR[0x170002]))
|
||||
#define MCF_PIT_PCNTR2 (*(vuint16*)(void*)(&__IPSBAR[0x170004]))
|
||||
#define MCF_PIT_PCSR3 (*(vuint16*)(void*)(&__IPSBAR[0x180000]))
|
||||
#define MCF_PIT_PMR3 (*(vuint16*)(void*)(&__IPSBAR[0x180002]))
|
||||
#define MCF_PIT_PCNTR3 (*(vuint16*)(void*)(&__IPSBAR[0x180004]))
|
||||
#define MCF_PIT_PCSR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150000+((x)*0x10000)]))
|
||||
#define MCF_PIT_PMR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150002+((x)*0x10000)]))
|
||||
#define MCF_PIT_PCNTR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150004+((x)*0x10000)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PCSR */
|
||||
#define MCF_PIT_PCSR_EN (0x0001)
|
||||
#define MCF_PIT_PCSR_RLD (0x0002)
|
||||
#define MCF_PIT_PCSR_PIF (0x0004)
|
||||
#define MCF_PIT_PCSR_PIE (0x0008)
|
||||
#define MCF_PIT_PCSR_OVW (0x0010)
|
||||
#define MCF_PIT_PCSR_HALTED (0x0020)
|
||||
#define MCF_PIT_PCSR_DOZE (0x0040)
|
||||
#define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8)
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PMR */
|
||||
#define MCF_PIT_PMR_PM0 (0x0001)
|
||||
#define MCF_PIT_PMR_PM1 (0x0002)
|
||||
#define MCF_PIT_PMR_PM2 (0x0004)
|
||||
#define MCF_PIT_PMR_PM3 (0x0008)
|
||||
#define MCF_PIT_PMR_PM4 (0x0010)
|
||||
#define MCF_PIT_PMR_PM5 (0x0020)
|
||||
#define MCF_PIT_PMR_PM6 (0x0040)
|
||||
#define MCF_PIT_PMR_PM7 (0x0080)
|
||||
#define MCF_PIT_PMR_PM8 (0x0100)
|
||||
#define MCF_PIT_PMR_PM9 (0x0200)
|
||||
#define MCF_PIT_PMR_PM10 (0x0400)
|
||||
#define MCF_PIT_PMR_PM11 (0x0800)
|
||||
#define MCF_PIT_PMR_PM12 (0x1000)
|
||||
#define MCF_PIT_PMR_PM13 (0x2000)
|
||||
#define MCF_PIT_PMR_PM14 (0x4000)
|
||||
#define MCF_PIT_PMR_PM15 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PCNTR */
|
||||
#define MCF_PIT_PCNTR_PC0 (0x0001)
|
||||
#define MCF_PIT_PCNTR_PC1 (0x0002)
|
||||
#define MCF_PIT_PCNTR_PC2 (0x0004)
|
||||
#define MCF_PIT_PCNTR_PC3 (0x0008)
|
||||
#define MCF_PIT_PCNTR_PC4 (0x0010)
|
||||
#define MCF_PIT_PCNTR_PC5 (0x0020)
|
||||
#define MCF_PIT_PCNTR_PC6 (0x0040)
|
||||
#define MCF_PIT_PCNTR_PC7 (0x0080)
|
||||
#define MCF_PIT_PCNTR_PC8 (0x0100)
|
||||
#define MCF_PIT_PCNTR_PC9 (0x0200)
|
||||
#define MCF_PIT_PCNTR_PC10 (0x0400)
|
||||
#define MCF_PIT_PCNTR_PC11 (0x0800)
|
||||
#define MCF_PIT_PCNTR_PC12 (0x1000)
|
||||
#define MCF_PIT_PCNTR_PC13 (0x2000)
|
||||
#define MCF_PIT_PCNTR_PC14 (0x4000)
|
||||
#define MCF_PIT_PCNTR_PC15 (0x8000)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_PIT_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_pit.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_PIT_H__
|
||||
#define __MCF523X_PIT_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Programmable Interrupt Timer Modules (PIT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PIT_PCSR0 (*(vuint16*)(void*)(&__IPSBAR[0x150000]))
|
||||
#define MCF_PIT_PMR0 (*(vuint16*)(void*)(&__IPSBAR[0x150002]))
|
||||
#define MCF_PIT_PCNTR0 (*(vuint16*)(void*)(&__IPSBAR[0x150004]))
|
||||
#define MCF_PIT_PCSR1 (*(vuint16*)(void*)(&__IPSBAR[0x160000]))
|
||||
#define MCF_PIT_PMR1 (*(vuint16*)(void*)(&__IPSBAR[0x160002]))
|
||||
#define MCF_PIT_PCNTR1 (*(vuint16*)(void*)(&__IPSBAR[0x160004]))
|
||||
#define MCF_PIT_PCSR2 (*(vuint16*)(void*)(&__IPSBAR[0x170000]))
|
||||
#define MCF_PIT_PMR2 (*(vuint16*)(void*)(&__IPSBAR[0x170002]))
|
||||
#define MCF_PIT_PCNTR2 (*(vuint16*)(void*)(&__IPSBAR[0x170004]))
|
||||
#define MCF_PIT_PCSR3 (*(vuint16*)(void*)(&__IPSBAR[0x180000]))
|
||||
#define MCF_PIT_PMR3 (*(vuint16*)(void*)(&__IPSBAR[0x180002]))
|
||||
#define MCF_PIT_PCNTR3 (*(vuint16*)(void*)(&__IPSBAR[0x180004]))
|
||||
#define MCF_PIT_PCSR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150000+((x)*0x10000)]))
|
||||
#define MCF_PIT_PMR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150002+((x)*0x10000)]))
|
||||
#define MCF_PIT_PCNTR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150004+((x)*0x10000)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PCSR */
|
||||
#define MCF_PIT_PCSR_EN (0x0001)
|
||||
#define MCF_PIT_PCSR_RLD (0x0002)
|
||||
#define MCF_PIT_PCSR_PIF (0x0004)
|
||||
#define MCF_PIT_PCSR_PIE (0x0008)
|
||||
#define MCF_PIT_PCSR_OVW (0x0010)
|
||||
#define MCF_PIT_PCSR_HALTED (0x0020)
|
||||
#define MCF_PIT_PCSR_DOZE (0x0040)
|
||||
#define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8)
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PMR */
|
||||
#define MCF_PIT_PMR_PM0 (0x0001)
|
||||
#define MCF_PIT_PMR_PM1 (0x0002)
|
||||
#define MCF_PIT_PMR_PM2 (0x0004)
|
||||
#define MCF_PIT_PMR_PM3 (0x0008)
|
||||
#define MCF_PIT_PMR_PM4 (0x0010)
|
||||
#define MCF_PIT_PMR_PM5 (0x0020)
|
||||
#define MCF_PIT_PMR_PM6 (0x0040)
|
||||
#define MCF_PIT_PMR_PM7 (0x0080)
|
||||
#define MCF_PIT_PMR_PM8 (0x0100)
|
||||
#define MCF_PIT_PMR_PM9 (0x0200)
|
||||
#define MCF_PIT_PMR_PM10 (0x0400)
|
||||
#define MCF_PIT_PMR_PM11 (0x0800)
|
||||
#define MCF_PIT_PMR_PM12 (0x1000)
|
||||
#define MCF_PIT_PMR_PM13 (0x2000)
|
||||
#define MCF_PIT_PMR_PM14 (0x4000)
|
||||
#define MCF_PIT_PMR_PM15 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PCNTR */
|
||||
#define MCF_PIT_PCNTR_PC0 (0x0001)
|
||||
#define MCF_PIT_PCNTR_PC1 (0x0002)
|
||||
#define MCF_PIT_PCNTR_PC2 (0x0004)
|
||||
#define MCF_PIT_PCNTR_PC3 (0x0008)
|
||||
#define MCF_PIT_PCNTR_PC4 (0x0010)
|
||||
#define MCF_PIT_PCNTR_PC5 (0x0020)
|
||||
#define MCF_PIT_PCNTR_PC6 (0x0040)
|
||||
#define MCF_PIT_PCNTR_PC7 (0x0080)
|
||||
#define MCF_PIT_PCNTR_PC8 (0x0100)
|
||||
#define MCF_PIT_PCNTR_PC9 (0x0200)
|
||||
#define MCF_PIT_PCNTR_PC10 (0x0400)
|
||||
#define MCF_PIT_PCNTR_PC11 (0x0800)
|
||||
#define MCF_PIT_PCNTR_PC12 (0x1000)
|
||||
#define MCF_PIT_PCNTR_PC13 (0x2000)
|
||||
#define MCF_PIT_PCNTR_PC14 (0x4000)
|
||||
#define MCF_PIT_PCNTR_PC15 (0x8000)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_PIT_H__ */
|
||||
|
|
|
|||
|
|
@ -1,69 +1,69 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_qspi.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_QSPI_H__
|
||||
#define __MCF523X_QSPI_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Queued Serial Peripheral Interface (QSPI)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_QSPI_QMR (*(vuint16*)(void*)(&__IPSBAR[0x000340]))
|
||||
#define MCF_QSPI_QDLYR (*(vuint16*)(void*)(&__IPSBAR[0x000344]))
|
||||
#define MCF_QSPI_QWR (*(vuint16*)(void*)(&__IPSBAR[0x000348]))
|
||||
#define MCF_QSPI_QIR (*(vuint16*)(void*)(&__IPSBAR[0x00034C]))
|
||||
#define MCF_QSPI_QAR (*(vuint16*)(void*)(&__IPSBAR[0x000350]))
|
||||
#define MCF_QSPI_QDR (*(vuint16*)(void*)(&__IPSBAR[0x000354]))
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QMR */
|
||||
#define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0)
|
||||
#define MCF_QSPI_QMR_CPHA (0x0100)
|
||||
#define MCF_QSPI_QMR_CPOL (0x0200)
|
||||
#define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
|
||||
#define MCF_QSPI_QMR_DOHIE (0x4000)
|
||||
#define MCF_QSPI_QMR_MSTR (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QDLYR */
|
||||
#define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0)
|
||||
#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
|
||||
#define MCF_QSPI_QDLYR_SPE (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QWR */
|
||||
#define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0)
|
||||
#define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
|
||||
#define MCF_QSPI_QWR_CSIV (0x1000)
|
||||
#define MCF_QSPI_QWR_WRTO (0x2000)
|
||||
#define MCF_QSPI_QWR_WREN (0x4000)
|
||||
#define MCF_QSPI_QWR_HALT (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QIR */
|
||||
#define MCF_QSPI_QIR_SPIF (0x0001)
|
||||
#define MCF_QSPI_QIR_ABRT (0x0004)
|
||||
#define MCF_QSPI_QIR_WCEF (0x0008)
|
||||
#define MCF_QSPI_QIR_SPIFE (0x0100)
|
||||
#define MCF_QSPI_QIR_ABRTE (0x0400)
|
||||
#define MCF_QSPI_QIR_WCEFE (0x0800)
|
||||
#define MCF_QSPI_QIR_ABRTL (0x1000)
|
||||
#define MCF_QSPI_QIR_ABRTB (0x4000)
|
||||
#define MCF_QSPI_QIR_WCEFB (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QAR */
|
||||
#define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_QSPI_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_qspi.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_QSPI_H__
|
||||
#define __MCF523X_QSPI_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Queued Serial Peripheral Interface (QSPI)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_QSPI_QMR (*(vuint16*)(void*)(&__IPSBAR[0x000340]))
|
||||
#define MCF_QSPI_QDLYR (*(vuint16*)(void*)(&__IPSBAR[0x000344]))
|
||||
#define MCF_QSPI_QWR (*(vuint16*)(void*)(&__IPSBAR[0x000348]))
|
||||
#define MCF_QSPI_QIR (*(vuint16*)(void*)(&__IPSBAR[0x00034C]))
|
||||
#define MCF_QSPI_QAR (*(vuint16*)(void*)(&__IPSBAR[0x000350]))
|
||||
#define MCF_QSPI_QDR (*(vuint16*)(void*)(&__IPSBAR[0x000354]))
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QMR */
|
||||
#define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0)
|
||||
#define MCF_QSPI_QMR_CPHA (0x0100)
|
||||
#define MCF_QSPI_QMR_CPOL (0x0200)
|
||||
#define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
|
||||
#define MCF_QSPI_QMR_DOHIE (0x4000)
|
||||
#define MCF_QSPI_QMR_MSTR (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QDLYR */
|
||||
#define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0)
|
||||
#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
|
||||
#define MCF_QSPI_QDLYR_SPE (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QWR */
|
||||
#define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0)
|
||||
#define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
|
||||
#define MCF_QSPI_QWR_CSIV (0x1000)
|
||||
#define MCF_QSPI_QWR_WRTO (0x2000)
|
||||
#define MCF_QSPI_QWR_WREN (0x4000)
|
||||
#define MCF_QSPI_QWR_HALT (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QIR */
|
||||
#define MCF_QSPI_QIR_SPIF (0x0001)
|
||||
#define MCF_QSPI_QIR_ABRT (0x0004)
|
||||
#define MCF_QSPI_QIR_WCEF (0x0008)
|
||||
#define MCF_QSPI_QIR_SPIFE (0x0100)
|
||||
#define MCF_QSPI_QIR_ABRTE (0x0400)
|
||||
#define MCF_QSPI_QIR_WCEFE (0x0800)
|
||||
#define MCF_QSPI_QIR_ABRTL (0x1000)
|
||||
#define MCF_QSPI_QIR_ABRTB (0x4000)
|
||||
#define MCF_QSPI_QIR_WCEFB (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QAR */
|
||||
#define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_QSPI_H__ */
|
||||
|
|
|
|||
|
|
@ -1,42 +1,42 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_rcm.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_RCM_H__
|
||||
#define __MCF523X_RCM_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Reset Configuration Module (RCM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_RCM_RCR (*(vuint8 *)(void*)(&__IPSBAR[0x110000]))
|
||||
#define MCF_RCM_RSR (*(vuint8 *)(void*)(&__IPSBAR[0x110001]))
|
||||
|
||||
/* Bit definitions and macros for MCF_RCM_RCR */
|
||||
#define MCF_RCM_RCR_FRCRSTOUT (0x40)
|
||||
#define MCF_RCM_RCR_SOFTRST (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_RCM_RSR */
|
||||
#define MCF_RCM_RSR_LOL (0x01)
|
||||
#define MCF_RCM_RSR_LOC (0x02)
|
||||
#define MCF_RCM_RSR_EXT (0x04)
|
||||
#define MCF_RCM_RSR_POR (0x08)
|
||||
#define MCF_RCM_RSR_WDR (0x10)
|
||||
#define MCF_RCM_RSR_SOFT (0x20)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_RCM_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_rcm.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_RCM_H__
|
||||
#define __MCF523X_RCM_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Reset Configuration Module (RCM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_RCM_RCR (*(vuint8 *)(void*)(&__IPSBAR[0x110000]))
|
||||
#define MCF_RCM_RSR (*(vuint8 *)(void*)(&__IPSBAR[0x110001]))
|
||||
|
||||
/* Bit definitions and macros for MCF_RCM_RCR */
|
||||
#define MCF_RCM_RCR_FRCRSTOUT (0x40)
|
||||
#define MCF_RCM_RCR_SOFTRST (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_RCM_RSR */
|
||||
#define MCF_RCM_RSR_LOL (0x01)
|
||||
#define MCF_RCM_RSR_LOC (0x02)
|
||||
#define MCF_RCM_RSR_EXT (0x04)
|
||||
#define MCF_RCM_RSR_POR (0x08)
|
||||
#define MCF_RCM_RSR_WDR (0x10)
|
||||
#define MCF_RCM_RSR_SOFT (0x20)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_RCM_H__ */
|
||||
|
|
|
|||
|
|
@ -1,46 +1,46 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_rng.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_RNG_H__
|
||||
#define __MCF523X_RNG_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Random Number Generator (RNG)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_RNG_RNGCR (*(vuint32*)(void*)(&__IPSBAR[0x1A0000]))
|
||||
#define MCF_RNG_RNGSR (*(vuint32*)(void*)(&__IPSBAR[0x1A0004]))
|
||||
#define MCF_RNG_RNGER (*(vuint32*)(void*)(&__IPSBAR[0x1A0008]))
|
||||
#define MCF_RNG_RNGOUT (*(vuint32*)(void*)(&__IPSBAR[0x1A000C]))
|
||||
|
||||
/* Bit definitions and macros for MCF_RNG_RNGCR */
|
||||
#define MCF_RNG_RNGCR_GO (0x00000001)
|
||||
#define MCF_RNG_RNGCR_HA (0x00000002)
|
||||
#define MCF_RNG_RNGCR_IM (0x00000004)
|
||||
#define MCF_RNG_RNGCR_CI (0x00000008)
|
||||
|
||||
/* Bit definitions and macros for MCF_RNG_RNGSR */
|
||||
#define MCF_RNG_RNGSR_SV (0x00000001)
|
||||
#define MCF_RNG_RNGSR_LRS (0x00000002)
|
||||
#define MCF_RNG_RNGSR_FUF (0x00000004)
|
||||
#define MCF_RNG_RNGSR_EI (0x00000008)
|
||||
#define MCF_RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8)
|
||||
#define MCF_RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_RNG_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_rng.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_RNG_H__
|
||||
#define __MCF523X_RNG_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Random Number Generator (RNG)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_RNG_RNGCR (*(vuint32*)(void*)(&__IPSBAR[0x1A0000]))
|
||||
#define MCF_RNG_RNGSR (*(vuint32*)(void*)(&__IPSBAR[0x1A0004]))
|
||||
#define MCF_RNG_RNGER (*(vuint32*)(void*)(&__IPSBAR[0x1A0008]))
|
||||
#define MCF_RNG_RNGOUT (*(vuint32*)(void*)(&__IPSBAR[0x1A000C]))
|
||||
|
||||
/* Bit definitions and macros for MCF_RNG_RNGCR */
|
||||
#define MCF_RNG_RNGCR_GO (0x00000001)
|
||||
#define MCF_RNG_RNGCR_HA (0x00000002)
|
||||
#define MCF_RNG_RNGCR_IM (0x00000004)
|
||||
#define MCF_RNG_RNGCR_CI (0x00000008)
|
||||
|
||||
/* Bit definitions and macros for MCF_RNG_RNGSR */
|
||||
#define MCF_RNG_RNGSR_SV (0x00000001)
|
||||
#define MCF_RNG_RNGSR_LRS (0x00000002)
|
||||
#define MCF_RNG_RNGSR_FUF (0x00000004)
|
||||
#define MCF_RNG_RNGSR_EI (0x00000008)
|
||||
#define MCF_RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8)
|
||||
#define MCF_RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_RNG_H__ */
|
||||
|
|
|
|||
|
|
@ -1,150 +1,150 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_scm.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_SCM_H__
|
||||
#define __MCF523X_SCM_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* System Control Module (SCM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SCM_IPSBAR (*(vuint32*)(void*)(&__IPSBAR[0x000000]))
|
||||
#define MCF_SCM_RAMBAR (*(vuint32*)(void*)(&__IPSBAR[0x000008]))
|
||||
#define MCF_SCM_CRSR (*(vuint8 *)(void*)(&__IPSBAR[0x000010]))
|
||||
#define MCF_SCM_CWCR (*(vuint8 *)(void*)(&__IPSBAR[0x000011]))
|
||||
#define MCF_SCM_LPICR (*(vuint8 *)(void*)(&__IPSBAR[0x000012]))
|
||||
#define MCF_SCM_CWSR (*(vuint8 *)(void*)(&__IPSBAR[0x000013]))
|
||||
#define MCF_SCM_DMAREQC (*(vuint32*)(void*)(&__IPSBAR[0x000014]))
|
||||
#define MCF_SCM_MPARK (*(vuint32*)(void*)(&__IPSBAR[0x00001C]))
|
||||
#define MCF_SCM_MPR (*(vuint8 *)(void*)(&__IPSBAR[0x000020]))
|
||||
#define MCF_SCM_PACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000024]))
|
||||
#define MCF_SCM_PACR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000025]))
|
||||
#define MCF_SCM_PACR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000026]))
|
||||
#define MCF_SCM_PACR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000027]))
|
||||
#define MCF_SCM_PACR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000028]))
|
||||
#define MCF_SCM_PACR5 (*(vuint8 *)(void*)(&__IPSBAR[0x00002A]))
|
||||
#define MCF_SCM_PACR6 (*(vuint8 *)(void*)(&__IPSBAR[0x00002B]))
|
||||
#define MCF_SCM_PACR7 (*(vuint8 *)(void*)(&__IPSBAR[0x00002C]))
|
||||
#define MCF_SCM_PACR8 (*(vuint8 *)(void*)(&__IPSBAR[0x00002E]))
|
||||
#define MCF_SCM_GPACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000030]))
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_IPSBAR */
|
||||
#define MCF_SCM_IPSBAR_V (0x00000001)
|
||||
#define MCF_SCM_IPSBAR_BA(x) (((x)&0x00000003)<<30)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_RAMBAR */
|
||||
#define MCF_SCM_RAMBAR_BDE (0x00000200)
|
||||
#define MCF_SCM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_CRSR */
|
||||
#define MCF_SCM_CRSR_CWDR (0x20)
|
||||
#define MCF_SCM_CRSR_EXT (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_CWCR */
|
||||
#define MCF_SCM_CWCR_CWTIC (0x01)
|
||||
#define MCF_SCM_CWCR_CWTAVAL (0x02)
|
||||
#define MCF_SCM_CWCR_CWTA (0x04)
|
||||
#define MCF_SCM_CWCR_CWT(x) (((x)&0x07)<<3)
|
||||
#define MCF_SCM_CWCR_CWRI (0x40)
|
||||
#define MCF_SCM_CWCR_CWE (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_LPICR */
|
||||
#define MCF_SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_LPICR_ENBSTOP (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_DMAREQC */
|
||||
#define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0)
|
||||
#define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4)
|
||||
#define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8)
|
||||
#define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_MPARK */
|
||||
#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8)
|
||||
#define MCF_SCM_MPARK_PRKLAST (0x00001000)
|
||||
#define MCF_SCM_MPARK_TIMEOUT (0x00002000)
|
||||
#define MCF_SCM_MPARK_FIXED (0x00004000)
|
||||
#define MCF_SCM_MPARK_M1_PRTY(x) (((x)&0x00000003)<<16)
|
||||
#define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x00000003)<<18)
|
||||
#define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x00000003)<<20)
|
||||
#define MCF_SCM_MPARK_M3_PRTY(x) (((x)&0x00000003)<<22)
|
||||
#define MCF_SCM_MPARK_BCR24BIT (0x01000000)
|
||||
#define MCF_SCM_MPARK_M2_P_EN (0x02000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_MPR */
|
||||
#define MCF_SCM_MPR_MPR(x) (((x)&0x0F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR0 */
|
||||
#define MCF_SCM_PACR0_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR0_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR0_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR0_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR1 */
|
||||
#define MCF_SCM_PACR1_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR1_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR1_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR1_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR2 */
|
||||
#define MCF_SCM_PACR2_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR2_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR2_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR2_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR3 */
|
||||
#define MCF_SCM_PACR3_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR3_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR3_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR3_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR4 */
|
||||
#define MCF_SCM_PACR4_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR4_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR4_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR4_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR5 */
|
||||
#define MCF_SCM_PACR5_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR5_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR5_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR5_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR6 */
|
||||
#define MCF_SCM_PACR6_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR6_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR6_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR6_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR7 */
|
||||
#define MCF_SCM_PACR7_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR7_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR7_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR7_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR8 */
|
||||
#define MCF_SCM_PACR8_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR8_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR8_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR8_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_GPACR0 */
|
||||
#define MCF_SCM_GPACR0_ACCESS_CTRL(x) (((x)&0x0F)<<0)
|
||||
#define MCF_SCM_GPACR0_LOCK (0x80)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_SCM_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_scm.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_SCM_H__
|
||||
#define __MCF523X_SCM_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* System Control Module (SCM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SCM_IPSBAR (*(vuint32*)(void*)(&__IPSBAR[0x000000]))
|
||||
#define MCF_SCM_RAMBAR (*(vuint32*)(void*)(&__IPSBAR[0x000008]))
|
||||
#define MCF_SCM_CRSR (*(vuint8 *)(void*)(&__IPSBAR[0x000010]))
|
||||
#define MCF_SCM_CWCR (*(vuint8 *)(void*)(&__IPSBAR[0x000011]))
|
||||
#define MCF_SCM_LPICR (*(vuint8 *)(void*)(&__IPSBAR[0x000012]))
|
||||
#define MCF_SCM_CWSR (*(vuint8 *)(void*)(&__IPSBAR[0x000013]))
|
||||
#define MCF_SCM_DMAREQC (*(vuint32*)(void*)(&__IPSBAR[0x000014]))
|
||||
#define MCF_SCM_MPARK (*(vuint32*)(void*)(&__IPSBAR[0x00001C]))
|
||||
#define MCF_SCM_MPR (*(vuint8 *)(void*)(&__IPSBAR[0x000020]))
|
||||
#define MCF_SCM_PACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000024]))
|
||||
#define MCF_SCM_PACR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000025]))
|
||||
#define MCF_SCM_PACR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000026]))
|
||||
#define MCF_SCM_PACR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000027]))
|
||||
#define MCF_SCM_PACR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000028]))
|
||||
#define MCF_SCM_PACR5 (*(vuint8 *)(void*)(&__IPSBAR[0x00002A]))
|
||||
#define MCF_SCM_PACR6 (*(vuint8 *)(void*)(&__IPSBAR[0x00002B]))
|
||||
#define MCF_SCM_PACR7 (*(vuint8 *)(void*)(&__IPSBAR[0x00002C]))
|
||||
#define MCF_SCM_PACR8 (*(vuint8 *)(void*)(&__IPSBAR[0x00002E]))
|
||||
#define MCF_SCM_GPACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000030]))
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_IPSBAR */
|
||||
#define MCF_SCM_IPSBAR_V (0x00000001)
|
||||
#define MCF_SCM_IPSBAR_BA(x) (((x)&0x00000003)<<30)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_RAMBAR */
|
||||
#define MCF_SCM_RAMBAR_BDE (0x00000200)
|
||||
#define MCF_SCM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_CRSR */
|
||||
#define MCF_SCM_CRSR_CWDR (0x20)
|
||||
#define MCF_SCM_CRSR_EXT (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_CWCR */
|
||||
#define MCF_SCM_CWCR_CWTIC (0x01)
|
||||
#define MCF_SCM_CWCR_CWTAVAL (0x02)
|
||||
#define MCF_SCM_CWCR_CWTA (0x04)
|
||||
#define MCF_SCM_CWCR_CWT(x) (((x)&0x07)<<3)
|
||||
#define MCF_SCM_CWCR_CWRI (0x40)
|
||||
#define MCF_SCM_CWCR_CWE (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_LPICR */
|
||||
#define MCF_SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_LPICR_ENBSTOP (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_DMAREQC */
|
||||
#define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0)
|
||||
#define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4)
|
||||
#define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8)
|
||||
#define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_MPARK */
|
||||
#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8)
|
||||
#define MCF_SCM_MPARK_PRKLAST (0x00001000)
|
||||
#define MCF_SCM_MPARK_TIMEOUT (0x00002000)
|
||||
#define MCF_SCM_MPARK_FIXED (0x00004000)
|
||||
#define MCF_SCM_MPARK_M1_PRTY(x) (((x)&0x00000003)<<16)
|
||||
#define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x00000003)<<18)
|
||||
#define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x00000003)<<20)
|
||||
#define MCF_SCM_MPARK_M3_PRTY(x) (((x)&0x00000003)<<22)
|
||||
#define MCF_SCM_MPARK_BCR24BIT (0x01000000)
|
||||
#define MCF_SCM_MPARK_M2_P_EN (0x02000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_MPR */
|
||||
#define MCF_SCM_MPR_MPR(x) (((x)&0x0F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR0 */
|
||||
#define MCF_SCM_PACR0_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR0_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR0_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR0_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR1 */
|
||||
#define MCF_SCM_PACR1_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR1_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR1_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR1_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR2 */
|
||||
#define MCF_SCM_PACR2_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR2_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR2_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR2_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR3 */
|
||||
#define MCF_SCM_PACR3_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR3_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR3_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR3_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR4 */
|
||||
#define MCF_SCM_PACR4_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR4_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR4_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR4_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR5 */
|
||||
#define MCF_SCM_PACR5_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR5_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR5_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR5_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR6 */
|
||||
#define MCF_SCM_PACR6_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR6_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR6_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR6_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR7 */
|
||||
#define MCF_SCM_PACR7_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR7_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR7_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR7_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR8 */
|
||||
#define MCF_SCM_PACR8_ACCESS_CTRL0(x) (((x)&0x07)<<0)
|
||||
#define MCF_SCM_PACR8_LOCK0 (0x08)
|
||||
#define MCF_SCM_PACR8_ACCESS_CTRL1(x) (((x)&0x07)<<4)
|
||||
#define MCF_SCM_PACR8_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_GPACR0 */
|
||||
#define MCF_SCM_GPACR0_ACCESS_CTRL(x) (((x)&0x0F)<<0)
|
||||
#define MCF_SCM_GPACR0_LOCK (0x80)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_SCM_H__ */
|
||||
|
|
|
|||
|
|
@ -1,94 +1,94 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_sdramc.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_SDRAMC_H__
|
||||
#define __MCF523X_SDRAMC_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* SDRAM Controller (SDRAMC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SDRAMC_DCR (*(vuint16*)(void*)(&__IPSBAR[0x000040]))
|
||||
#define MCF_SDRAMC_DACR0 (*(vuint32*)(void*)(&__IPSBAR[0x000048]))
|
||||
#define MCF_SDRAMC_DMR0 (*(vuint32*)(void*)(&__IPSBAR[0x00004C]))
|
||||
#define MCF_SDRAMC_DACR1 (*(vuint32*)(void*)(&__IPSBAR[0x000050]))
|
||||
#define MCF_SDRAMC_DMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000054]))
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_DCR */
|
||||
#define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0)
|
||||
#define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9)
|
||||
#define MCF_SDRAMC_DCR_IS (0x0800)
|
||||
#define MCF_SDRAMC_DCR_COC (0x1000)
|
||||
#define MCF_SDRAMC_DCR_NAM (0x2000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_DACR0 */
|
||||
#define MCF_SDRAMC_DACR0_IP (0x00000008)
|
||||
#define MCF_SDRAMC_DACR0_PS(x) (((x)&0x00000003)<<4)
|
||||
#define MCF_SDRAMC_DACR0_MRS (0x00000040)
|
||||
#define MCF_SDRAMC_DACR0_CBM(x) (((x)&0x00000007)<<8)
|
||||
#define MCF_SDRAMC_DACR0_CASL(x) (((x)&0x00000003)<<12)
|
||||
#define MCF_SDRAMC_DACR0_RE (0x00008000)
|
||||
#define MCF_SDRAMC_DACR0_BA(x) (((x)&0x00003FFF)<<18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_DMR0 */
|
||||
#define MCF_SDRAMC_DMR0_V (0x00000001)
|
||||
#define MCF_SDRAMC_DMR0_WP (0x00000100)
|
||||
#define MCF_SDRAMC_DMR0_BAM(x) (((x)&0x00003FFF)<<18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_DACR1 */
|
||||
#define MCF_SDRAMC_DACR1_IP (0x00000008)
|
||||
#define MCF_SDRAMC_DACR1_PS(x) (((x)&0x00000003)<<4)
|
||||
#define MCF_SDRAMC_DACR1_MRS (0x00000040)
|
||||
#define MCF_SDRAMC_DACR1_CBM(x) (((x)&0x00000007)<<8)
|
||||
#define MCF_SDRAMC_DACR1_CASL(x) (((x)&0x00000003)<<12)
|
||||
#define MCF_SDRAMC_DACR1_RE (0x00008000)
|
||||
#define MCF_SDRAMC_DACR1_BA(x) (((x)&0x00003FFF)<<18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_DMR1 */
|
||||
#define MCF_SDRAMC_DMR1_V (0x00000001)
|
||||
#define MCF_SDRAMC_DMR1_WP (0x00000100)
|
||||
#define MCF_SDRAMC_DMR1_BAM(x) (((x)&0x00003FFF)<<18)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#define MCF_SDRAMC_DMR_BAM_4G (0xFFFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_2G (0x7FFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_1G (0x3FFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_1024M (0x3FFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_512M (0x1FFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_256M (0x0FFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_128M (0x07FC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_64M (0x03FC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_32M (0x01FC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_16M (0x00FC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_8M (0x007C0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_4M (0x003C0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_2M (0x001C0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_1M (0x000C0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_1024K (0x000C0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_512K (0x00040000)
|
||||
#define MCF_SDRAMC_DMR_BAM_256K (0x00000000)
|
||||
#define MCF_SDRAMC_DMR_WP (0x00000100)
|
||||
#define MCF_SDRAMC_DMR_CI (0x00000040)
|
||||
#define MCF_SDRAMC_DMR_AM (0x00000020)
|
||||
#define MCF_SDRAMC_DMR_SC (0x00000010)
|
||||
#define MCF_SDRAMC_DMR_SD (0x00000008)
|
||||
#define MCF_SDRAMC_DMR_UC (0x00000004)
|
||||
#define MCF_SDRAMC_DMR_UD (0x00000002)
|
||||
#define MCF_SDRAMC_DMR_V (0x00000001)
|
||||
|
||||
#endif /* __MCF523X_SDRAMC_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_sdramc.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_SDRAMC_H__
|
||||
#define __MCF523X_SDRAMC_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* SDRAM Controller (SDRAMC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SDRAMC_DCR (*(vuint16*)(void*)(&__IPSBAR[0x000040]))
|
||||
#define MCF_SDRAMC_DACR0 (*(vuint32*)(void*)(&__IPSBAR[0x000048]))
|
||||
#define MCF_SDRAMC_DMR0 (*(vuint32*)(void*)(&__IPSBAR[0x00004C]))
|
||||
#define MCF_SDRAMC_DACR1 (*(vuint32*)(void*)(&__IPSBAR[0x000050]))
|
||||
#define MCF_SDRAMC_DMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000054]))
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_DCR */
|
||||
#define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0)
|
||||
#define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9)
|
||||
#define MCF_SDRAMC_DCR_IS (0x0800)
|
||||
#define MCF_SDRAMC_DCR_COC (0x1000)
|
||||
#define MCF_SDRAMC_DCR_NAM (0x2000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_DACR0 */
|
||||
#define MCF_SDRAMC_DACR0_IP (0x00000008)
|
||||
#define MCF_SDRAMC_DACR0_PS(x) (((x)&0x00000003)<<4)
|
||||
#define MCF_SDRAMC_DACR0_MRS (0x00000040)
|
||||
#define MCF_SDRAMC_DACR0_CBM(x) (((x)&0x00000007)<<8)
|
||||
#define MCF_SDRAMC_DACR0_CASL(x) (((x)&0x00000003)<<12)
|
||||
#define MCF_SDRAMC_DACR0_RE (0x00008000)
|
||||
#define MCF_SDRAMC_DACR0_BA(x) (((x)&0x00003FFF)<<18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_DMR0 */
|
||||
#define MCF_SDRAMC_DMR0_V (0x00000001)
|
||||
#define MCF_SDRAMC_DMR0_WP (0x00000100)
|
||||
#define MCF_SDRAMC_DMR0_BAM(x) (((x)&0x00003FFF)<<18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_DACR1 */
|
||||
#define MCF_SDRAMC_DACR1_IP (0x00000008)
|
||||
#define MCF_SDRAMC_DACR1_PS(x) (((x)&0x00000003)<<4)
|
||||
#define MCF_SDRAMC_DACR1_MRS (0x00000040)
|
||||
#define MCF_SDRAMC_DACR1_CBM(x) (((x)&0x00000007)<<8)
|
||||
#define MCF_SDRAMC_DACR1_CASL(x) (((x)&0x00000003)<<12)
|
||||
#define MCF_SDRAMC_DACR1_RE (0x00008000)
|
||||
#define MCF_SDRAMC_DACR1_BA(x) (((x)&0x00003FFF)<<18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_DMR1 */
|
||||
#define MCF_SDRAMC_DMR1_V (0x00000001)
|
||||
#define MCF_SDRAMC_DMR1_WP (0x00000100)
|
||||
#define MCF_SDRAMC_DMR1_BAM(x) (((x)&0x00003FFF)<<18)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#define MCF_SDRAMC_DMR_BAM_4G (0xFFFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_2G (0x7FFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_1G (0x3FFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_1024M (0x3FFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_512M (0x1FFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_256M (0x0FFC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_128M (0x07FC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_64M (0x03FC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_32M (0x01FC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_16M (0x00FC0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_8M (0x007C0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_4M (0x003C0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_2M (0x001C0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_1M (0x000C0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_1024K (0x000C0000)
|
||||
#define MCF_SDRAMC_DMR_BAM_512K (0x00040000)
|
||||
#define MCF_SDRAMC_DMR_BAM_256K (0x00000000)
|
||||
#define MCF_SDRAMC_DMR_WP (0x00000100)
|
||||
#define MCF_SDRAMC_DMR_CI (0x00000040)
|
||||
#define MCF_SDRAMC_DMR_AM (0x00000020)
|
||||
#define MCF_SDRAMC_DMR_SC (0x00000010)
|
||||
#define MCF_SDRAMC_DMR_SD (0x00000008)
|
||||
#define MCF_SDRAMC_DMR_UC (0x00000004)
|
||||
#define MCF_SDRAMC_DMR_UD (0x00000002)
|
||||
#define MCF_SDRAMC_DMR_V (0x00000001)
|
||||
|
||||
#endif /* __MCF523X_SDRAMC_H__ */
|
||||
|
|
|
|||
|
|
@ -1,120 +1,120 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_skha.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_SKHA_H__
|
||||
#define __MCF523X_SKHA_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Symmetric Key Hardware Accelerator (SKHA)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SKHA_SKMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0000]))
|
||||
#define MCF_SKHA_SKCR (*(vuint32*)(void*)(&__IPSBAR[0x1B0004]))
|
||||
#define MCF_SKHA_SKCMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0008]))
|
||||
#define MCF_SKHA_SKSR (*(vuint32*)(void*)(&__IPSBAR[0x1B000C]))
|
||||
#define MCF_SKHA_SKIR (*(vuint32*)(void*)(&__IPSBAR[0x1B0010]))
|
||||
#define MCF_SKHA_SKIMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0014]))
|
||||
#define MCF_SKHA_SKKSR (*(vuint32*)(void*)(&__IPSBAR[0x1B0018]))
|
||||
#define MCF_SKHA_SKDSR (*(vuint32*)(void*)(&__IPSBAR[0x1B001C]))
|
||||
#define MCF_SKHA_SKIN (*(vuint32*)(void*)(&__IPSBAR[0x1B0020]))
|
||||
#define MCF_SKHA_SKOUT (*(vuint32*)(void*)(&__IPSBAR[0x1B0024]))
|
||||
#define MCF_SKHA_SKKDR0 (*(vuint32*)(void*)(&__IPSBAR[0x1B0030]))
|
||||
#define MCF_SKHA_SKKDR1 (*(vuint32*)(void*)(&__IPSBAR[0x1B0034]))
|
||||
#define MCF_SKHA_SKKDR2 (*(vuint32*)(void*)(&__IPSBAR[0x1B0038]))
|
||||
#define MCF_SKHA_SKKDR3 (*(vuint32*)(void*)(&__IPSBAR[0x1B003C]))
|
||||
#define MCF_SKHA_SKKDR4 (*(vuint32*)(void*)(&__IPSBAR[0x1B0040]))
|
||||
#define MCF_SKHA_SKKDR5 (*(vuint32*)(void*)(&__IPSBAR[0x1B0044]))
|
||||
#define MCF_SKHA_SKKDRn(x) (*(vuint32*)(void*)(&__IPSBAR[0x1B0030+((x)*0x004)]))
|
||||
#define MCF_SKHA_SKCR0 (*(vuint32*)(void*)(&__IPSBAR[0x1B0070]))
|
||||
#define MCF_SKHA_SKCR1 (*(vuint32*)(void*)(&__IPSBAR[0x1B0074]))
|
||||
#define MCF_SKHA_SKCR2 (*(vuint32*)(void*)(&__IPSBAR[0x1B0078]))
|
||||
#define MCF_SKHA_SKCR3 (*(vuint32*)(void*)(&__IPSBAR[0x1B007C]))
|
||||
#define MCF_SKHA_SKCR4 (*(vuint32*)(void*)(&__IPSBAR[0x1B0080]))
|
||||
#define MCF_SKHA_SKCR5 (*(vuint32*)(void*)(&__IPSBAR[0x1B0084]))
|
||||
#define MCF_SKHA_SKCR6 (*(vuint32*)(void*)(&__IPSBAR[0x1B0088]))
|
||||
#define MCF_SKHA_SKCR7 (*(vuint32*)(void*)(&__IPSBAR[0x1B008C]))
|
||||
#define MCF_SKHA_SKCR8 (*(vuint32*)(void*)(&__IPSBAR[0x1B0090]))
|
||||
#define MCF_SKHA_SKCR9 (*(vuint32*)(void*)(&__IPSBAR[0x1B0094]))
|
||||
#define MCF_SKHA_SKCR10 (*(vuint32*)(void*)(&__IPSBAR[0x1B0098]))
|
||||
#define MCF_SKHA_SKCR11 (*(vuint32*)(void*)(&__IPSBAR[0x1B009C]))
|
||||
#define MCF_SKHA_SKCRn(x) (*(vuint32*)(void*)(&__IPSBAR[0x1B0070+((x)*0x004)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKMR */
|
||||
#define MCF_SKHA_SKMR_ALG(x) (((x)&0x00000003)<<0)
|
||||
#define MCF_SKHA_SKMR_DIR (0x00000004)
|
||||
#define MCF_SKHA_SKMR_CM(x) (((x)&0x00000003)<<3)
|
||||
#define MCF_SKHA_SKMR_DKP (0x00000100)
|
||||
#define MCF_SKHA_SKMR_CTRM(x) (((x)&0x0000000F)<<9)
|
||||
#define MCF_SKHA_SKMR_CM_ECB (0x00000000)
|
||||
#define MCF_SKHA_SKMR_CM_CBC (0x00000008)
|
||||
#define MCF_SKHA_SKMR_CM_CTR (0x00000018)
|
||||
#define MCF_SKHA_SKMR_DIR_DEC (0x00000000)
|
||||
#define MCF_SKHA_SKMR_DIR_ENC (0x00000004)
|
||||
#define MCF_SKHA_SKMR_ALG_AES (0x00000000)
|
||||
#define MCF_SKHA_SKMR_ALG_DES (0x00000001)
|
||||
#define MCF_SKHA_SKMR_ALG_TDES (0x00000002)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKCR */
|
||||
#define MCF_SKHA_SKCR_IE (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKCMR */
|
||||
#define MCF_SKHA_SKCMR_SWR (0x00000001)
|
||||
#define MCF_SKHA_SKCMR_RI (0x00000002)
|
||||
#define MCF_SKHA_SKCMR_CI (0x00000004)
|
||||
#define MCF_SKHA_SKCMR_GO (0x00000008)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKSR */
|
||||
#define MCF_SKHA_SKSR_INT (0x00000001)
|
||||
#define MCF_SKHA_SKSR_DONE (0x00000002)
|
||||
#define MCF_SKHA_SKSR_ERR (0x00000004)
|
||||
#define MCF_SKHA_SKSR_RD (0x00000008)
|
||||
#define MCF_SKHA_SKSR_BUSY (0x00000010)
|
||||
#define MCF_SKHA_SKSR_IFL(x) (((x)&0x000000FF)<<16)
|
||||
#define MCF_SKHA_SKSR_OFL(x) (((x)&0x000000FF)<<24)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKIR */
|
||||
#define MCF_SKHA_SKIR_IFO (0x00000001)
|
||||
#define MCF_SKHA_SKIR_OFU (0x00000002)
|
||||
#define MCF_SKHA_SKIR_NEIF (0x00000004)
|
||||
#define MCF_SKHA_SKIR_NEOF (0x00000008)
|
||||
#define MCF_SKHA_SKIR_IME (0x00000010)
|
||||
#define MCF_SKHA_SKIR_DSE (0x00000020)
|
||||
#define MCF_SKHA_SKIR_KSE (0x00000040)
|
||||
#define MCF_SKHA_SKIR_RMDP (0x00000080)
|
||||
#define MCF_SKHA_SKIR_ERE (0x00000100)
|
||||
#define MCF_SKHA_SKIR_KPE (0x00000200)
|
||||
#define MCF_SKHA_SKIR_KRE (0x00000400)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKIMR */
|
||||
#define MCF_SKHA_SKIMR_IFO (0x00000001)
|
||||
#define MCF_SKHA_SKIMR_OFU (0x00000002)
|
||||
#define MCF_SKHA_SKIMR_NEIF (0x00000004)
|
||||
#define MCF_SKHA_SKIMR_NEOF (0x00000008)
|
||||
#define MCF_SKHA_SKIMR_IME (0x00000010)
|
||||
#define MCF_SKHA_SKIMR_DSE (0x00000020)
|
||||
#define MCF_SKHA_SKIMR_KSE (0x00000040)
|
||||
#define MCF_SKHA_SKIMR_RMDP (0x00000080)
|
||||
#define MCF_SKHA_SKIMR_ERE (0x00000100)
|
||||
#define MCF_SKHA_SKIMR_KPE (0x00000200)
|
||||
#define MCF_SKHA_SKIMR_KRE (0x00000400)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKKSR */
|
||||
#define MCF_SKHA_SKKSR_KEYSIZE(x) (((x)&0x0000003F)<<0)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_SKHA_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_skha.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_SKHA_H__
|
||||
#define __MCF523X_SKHA_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Symmetric Key Hardware Accelerator (SKHA)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SKHA_SKMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0000]))
|
||||
#define MCF_SKHA_SKCR (*(vuint32*)(void*)(&__IPSBAR[0x1B0004]))
|
||||
#define MCF_SKHA_SKCMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0008]))
|
||||
#define MCF_SKHA_SKSR (*(vuint32*)(void*)(&__IPSBAR[0x1B000C]))
|
||||
#define MCF_SKHA_SKIR (*(vuint32*)(void*)(&__IPSBAR[0x1B0010]))
|
||||
#define MCF_SKHA_SKIMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0014]))
|
||||
#define MCF_SKHA_SKKSR (*(vuint32*)(void*)(&__IPSBAR[0x1B0018]))
|
||||
#define MCF_SKHA_SKDSR (*(vuint32*)(void*)(&__IPSBAR[0x1B001C]))
|
||||
#define MCF_SKHA_SKIN (*(vuint32*)(void*)(&__IPSBAR[0x1B0020]))
|
||||
#define MCF_SKHA_SKOUT (*(vuint32*)(void*)(&__IPSBAR[0x1B0024]))
|
||||
#define MCF_SKHA_SKKDR0 (*(vuint32*)(void*)(&__IPSBAR[0x1B0030]))
|
||||
#define MCF_SKHA_SKKDR1 (*(vuint32*)(void*)(&__IPSBAR[0x1B0034]))
|
||||
#define MCF_SKHA_SKKDR2 (*(vuint32*)(void*)(&__IPSBAR[0x1B0038]))
|
||||
#define MCF_SKHA_SKKDR3 (*(vuint32*)(void*)(&__IPSBAR[0x1B003C]))
|
||||
#define MCF_SKHA_SKKDR4 (*(vuint32*)(void*)(&__IPSBAR[0x1B0040]))
|
||||
#define MCF_SKHA_SKKDR5 (*(vuint32*)(void*)(&__IPSBAR[0x1B0044]))
|
||||
#define MCF_SKHA_SKKDRn(x) (*(vuint32*)(void*)(&__IPSBAR[0x1B0030+((x)*0x004)]))
|
||||
#define MCF_SKHA_SKCR0 (*(vuint32*)(void*)(&__IPSBAR[0x1B0070]))
|
||||
#define MCF_SKHA_SKCR1 (*(vuint32*)(void*)(&__IPSBAR[0x1B0074]))
|
||||
#define MCF_SKHA_SKCR2 (*(vuint32*)(void*)(&__IPSBAR[0x1B0078]))
|
||||
#define MCF_SKHA_SKCR3 (*(vuint32*)(void*)(&__IPSBAR[0x1B007C]))
|
||||
#define MCF_SKHA_SKCR4 (*(vuint32*)(void*)(&__IPSBAR[0x1B0080]))
|
||||
#define MCF_SKHA_SKCR5 (*(vuint32*)(void*)(&__IPSBAR[0x1B0084]))
|
||||
#define MCF_SKHA_SKCR6 (*(vuint32*)(void*)(&__IPSBAR[0x1B0088]))
|
||||
#define MCF_SKHA_SKCR7 (*(vuint32*)(void*)(&__IPSBAR[0x1B008C]))
|
||||
#define MCF_SKHA_SKCR8 (*(vuint32*)(void*)(&__IPSBAR[0x1B0090]))
|
||||
#define MCF_SKHA_SKCR9 (*(vuint32*)(void*)(&__IPSBAR[0x1B0094]))
|
||||
#define MCF_SKHA_SKCR10 (*(vuint32*)(void*)(&__IPSBAR[0x1B0098]))
|
||||
#define MCF_SKHA_SKCR11 (*(vuint32*)(void*)(&__IPSBAR[0x1B009C]))
|
||||
#define MCF_SKHA_SKCRn(x) (*(vuint32*)(void*)(&__IPSBAR[0x1B0070+((x)*0x004)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKMR */
|
||||
#define MCF_SKHA_SKMR_ALG(x) (((x)&0x00000003)<<0)
|
||||
#define MCF_SKHA_SKMR_DIR (0x00000004)
|
||||
#define MCF_SKHA_SKMR_CM(x) (((x)&0x00000003)<<3)
|
||||
#define MCF_SKHA_SKMR_DKP (0x00000100)
|
||||
#define MCF_SKHA_SKMR_CTRM(x) (((x)&0x0000000F)<<9)
|
||||
#define MCF_SKHA_SKMR_CM_ECB (0x00000000)
|
||||
#define MCF_SKHA_SKMR_CM_CBC (0x00000008)
|
||||
#define MCF_SKHA_SKMR_CM_CTR (0x00000018)
|
||||
#define MCF_SKHA_SKMR_DIR_DEC (0x00000000)
|
||||
#define MCF_SKHA_SKMR_DIR_ENC (0x00000004)
|
||||
#define MCF_SKHA_SKMR_ALG_AES (0x00000000)
|
||||
#define MCF_SKHA_SKMR_ALG_DES (0x00000001)
|
||||
#define MCF_SKHA_SKMR_ALG_TDES (0x00000002)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKCR */
|
||||
#define MCF_SKHA_SKCR_IE (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKCMR */
|
||||
#define MCF_SKHA_SKCMR_SWR (0x00000001)
|
||||
#define MCF_SKHA_SKCMR_RI (0x00000002)
|
||||
#define MCF_SKHA_SKCMR_CI (0x00000004)
|
||||
#define MCF_SKHA_SKCMR_GO (0x00000008)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKSR */
|
||||
#define MCF_SKHA_SKSR_INT (0x00000001)
|
||||
#define MCF_SKHA_SKSR_DONE (0x00000002)
|
||||
#define MCF_SKHA_SKSR_ERR (0x00000004)
|
||||
#define MCF_SKHA_SKSR_RD (0x00000008)
|
||||
#define MCF_SKHA_SKSR_BUSY (0x00000010)
|
||||
#define MCF_SKHA_SKSR_IFL(x) (((x)&0x000000FF)<<16)
|
||||
#define MCF_SKHA_SKSR_OFL(x) (((x)&0x000000FF)<<24)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKIR */
|
||||
#define MCF_SKHA_SKIR_IFO (0x00000001)
|
||||
#define MCF_SKHA_SKIR_OFU (0x00000002)
|
||||
#define MCF_SKHA_SKIR_NEIF (0x00000004)
|
||||
#define MCF_SKHA_SKIR_NEOF (0x00000008)
|
||||
#define MCF_SKHA_SKIR_IME (0x00000010)
|
||||
#define MCF_SKHA_SKIR_DSE (0x00000020)
|
||||
#define MCF_SKHA_SKIR_KSE (0x00000040)
|
||||
#define MCF_SKHA_SKIR_RMDP (0x00000080)
|
||||
#define MCF_SKHA_SKIR_ERE (0x00000100)
|
||||
#define MCF_SKHA_SKIR_KPE (0x00000200)
|
||||
#define MCF_SKHA_SKIR_KRE (0x00000400)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKIMR */
|
||||
#define MCF_SKHA_SKIMR_IFO (0x00000001)
|
||||
#define MCF_SKHA_SKIMR_OFU (0x00000002)
|
||||
#define MCF_SKHA_SKIMR_NEIF (0x00000004)
|
||||
#define MCF_SKHA_SKIMR_NEOF (0x00000008)
|
||||
#define MCF_SKHA_SKIMR_IME (0x00000010)
|
||||
#define MCF_SKHA_SKIMR_DSE (0x00000020)
|
||||
#define MCF_SKHA_SKIMR_KSE (0x00000040)
|
||||
#define MCF_SKHA_SKIMR_RMDP (0x00000080)
|
||||
#define MCF_SKHA_SKIMR_ERE (0x00000100)
|
||||
#define MCF_SKHA_SKIMR_KPE (0x00000200)
|
||||
#define MCF_SKHA_SKIMR_KRE (0x00000400)
|
||||
|
||||
/* Bit definitions and macros for MCF_SKHA_SKKSR */
|
||||
#define MCF_SKHA_SKKSR_KEYSIZE(x) (((x)&0x0000003F)<<0)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_SKHA_H__ */
|
||||
|
|
|
|||
|
|
@ -1,42 +1,42 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_sram.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_SRAM_H__
|
||||
#define __MCF523X_SRAM_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* 64KByte System SRAM (SRAM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SRAM_RAMBAR (*(vuint32*)(void*)(&__IPSBAR[0x20000000]))
|
||||
|
||||
/* Bit definitions and macros for MCF_SRAM_RAMBAR */
|
||||
#define MCF_SRAM_RAMBAR_V (0x00000001)
|
||||
#define MCF_SRAM_RAMBAR_UD (0x00000002)
|
||||
#define MCF_SRAM_RAMBAR_UC (0x00000004)
|
||||
#define MCF_SRAM_RAMBAR_SD (0x00000008)
|
||||
#define MCF_SRAM_RAMBAR_SC (0x00000010)
|
||||
#define MCF_SRAM_RAMBAR_CI (0x00000020)
|
||||
#define MCF_SRAM_RAMBAR_WP (0x00000100)
|
||||
#define MCF_SRAM_RAMBAR_SPV (0x00000200)
|
||||
#define MCF_SRAM_RAMBAR_PRI2 (0x00000400)
|
||||
#define MCF_SRAM_RAMBAR_PRI1 (0x00000800)
|
||||
#define MCF_SRAM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_SRAM_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_sram.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_SRAM_H__
|
||||
#define __MCF523X_SRAM_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* 64KByte System SRAM (SRAM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SRAM_RAMBAR (*(vuint32*)(void*)(&__IPSBAR[0x20000000]))
|
||||
|
||||
/* Bit definitions and macros for MCF_SRAM_RAMBAR */
|
||||
#define MCF_SRAM_RAMBAR_V (0x00000001)
|
||||
#define MCF_SRAM_RAMBAR_UD (0x00000002)
|
||||
#define MCF_SRAM_RAMBAR_UC (0x00000004)
|
||||
#define MCF_SRAM_RAMBAR_SD (0x00000008)
|
||||
#define MCF_SRAM_RAMBAR_SC (0x00000010)
|
||||
#define MCF_SRAM_RAMBAR_CI (0x00000020)
|
||||
#define MCF_SRAM_RAMBAR_WP (0x00000100)
|
||||
#define MCF_SRAM_RAMBAR_SPV (0x00000200)
|
||||
#define MCF_SRAM_RAMBAR_PRI2 (0x00000400)
|
||||
#define MCF_SRAM_RAMBAR_PRI1 (0x00000800)
|
||||
#define MCF_SRAM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_SRAM_H__ */
|
||||
|
|
|
|||
|
|
@ -1,83 +1,83 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_timer.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_TIMER_H__
|
||||
#define __MCF523X_TIMER_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* DMA Timers (TIMER)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_TIMER_DTMR0 (*(vuint16*)(void*)(&__IPSBAR[0x000400]))
|
||||
#define MCF_TIMER_DTXMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000402]))
|
||||
#define MCF_TIMER_DTER0 (*(vuint8 *)(void*)(&__IPSBAR[0x000403]))
|
||||
#define MCF_TIMER_DTRR0 (*(vuint32*)(void*)(&__IPSBAR[0x000404]))
|
||||
#define MCF_TIMER_DTCR0 (*(vuint32*)(void*)(&__IPSBAR[0x000408]))
|
||||
#define MCF_TIMER_DTCN0 (*(vuint32*)(void*)(&__IPSBAR[0x00040C]))
|
||||
#define MCF_TIMER_DTMR1 (*(vuint16*)(void*)(&__IPSBAR[0x000440]))
|
||||
#define MCF_TIMER_DTXMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000442]))
|
||||
#define MCF_TIMER_DTER1 (*(vuint8 *)(void*)(&__IPSBAR[0x000443]))
|
||||
#define MCF_TIMER_DTRR1 (*(vuint32*)(void*)(&__IPSBAR[0x000444]))
|
||||
#define MCF_TIMER_DTCR1 (*(vuint32*)(void*)(&__IPSBAR[0x000448]))
|
||||
#define MCF_TIMER_DTCN1 (*(vuint32*)(void*)(&__IPSBAR[0x00044C]))
|
||||
#define MCF_TIMER_DTMR2 (*(vuint16*)(void*)(&__IPSBAR[0x000480]))
|
||||
#define MCF_TIMER_DTXMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000482]))
|
||||
#define MCF_TIMER_DTER2 (*(vuint8 *)(void*)(&__IPSBAR[0x000483]))
|
||||
#define MCF_TIMER_DTRR2 (*(vuint32*)(void*)(&__IPSBAR[0x000484]))
|
||||
#define MCF_TIMER_DTCR2 (*(vuint32*)(void*)(&__IPSBAR[0x000488]))
|
||||
#define MCF_TIMER_DTCN2 (*(vuint32*)(void*)(&__IPSBAR[0x00048C]))
|
||||
#define MCF_TIMER_DTMR3 (*(vuint16*)(void*)(&__IPSBAR[0x0004C0]))
|
||||
#define MCF_TIMER_DTXMR3 (*(vuint8 *)(void*)(&__IPSBAR[0x0004C2]))
|
||||
#define MCF_TIMER_DTER3 (*(vuint8 *)(void*)(&__IPSBAR[0x0004C3]))
|
||||
#define MCF_TIMER_DTRR3 (*(vuint32*)(void*)(&__IPSBAR[0x0004C4]))
|
||||
#define MCF_TIMER_DTCR3 (*(vuint32*)(void*)(&__IPSBAR[0x0004C8]))
|
||||
#define MCF_TIMER_DTCN3 (*(vuint32*)(void*)(&__IPSBAR[0x0004CC]))
|
||||
#define MCF_TIMER_DTMR(x) (*(vuint16*)(void*)(&__IPSBAR[0x000400+((x)*0x040)]))
|
||||
#define MCF_TIMER_DTXMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000402+((x)*0x040)]))
|
||||
#define MCF_TIMER_DTER(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000403+((x)*0x040)]))
|
||||
#define MCF_TIMER_DTRR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000404+((x)*0x040)]))
|
||||
#define MCF_TIMER_DTCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000408+((x)*0x040)]))
|
||||
#define MCF_TIMER_DTCN(x) (*(vuint32*)(void*)(&__IPSBAR[0x00040C+((x)*0x040)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_TIMER_DTMR */
|
||||
#define MCF_TIMER_DTMR_RST (0x0001)
|
||||
#define MCF_TIMER_DTMR_CLK(x) (((x)&0x0003)<<1)
|
||||
#define MCF_TIMER_DTMR_FRR (0x0008)
|
||||
#define MCF_TIMER_DTMR_ORRI (0x0010)
|
||||
#define MCF_TIMER_DTMR_OM (0x0020)
|
||||
#define MCF_TIMER_DTMR_CE(x) (((x)&0x0003)<<6)
|
||||
#define MCF_TIMER_DTMR_PS(x) (((x)&0x00FF)<<8)
|
||||
#define MCF_TIMER_DTMR_CE_ANY (0x00C0)
|
||||
#define MCF_TIMER_DTMR_CE_FALL (0x0080)
|
||||
#define MCF_TIMER_DTMR_CE_RISE (0x0040)
|
||||
#define MCF_TIMER_DTMR_CE_NONE (0x0000)
|
||||
#define MCF_TIMER_DTMR_CLK_DTIN (0x0006)
|
||||
#define MCF_TIMER_DTMR_CLK_DIV16 (0x0004)
|
||||
#define MCF_TIMER_DTMR_CLK_DIV1 (0x0002)
|
||||
#define MCF_TIMER_DTMR_CLK_STOP (0x0000)
|
||||
|
||||
/* Bit definitions and macros for MCF_TIMER_DTXMR */
|
||||
#define MCF_TIMER_DTXMR_MODE16 (0x01)
|
||||
#define MCF_TIMER_DTXMR_DMAEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_TIMER_DTER */
|
||||
#define MCF_TIMER_DTER_CAP (0x01)
|
||||
#define MCF_TIMER_DTER_REF (0x02)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_TIMER_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_timer.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_TIMER_H__
|
||||
#define __MCF523X_TIMER_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* DMA Timers (TIMER)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_TIMER_DTMR0 (*(vuint16*)(void*)(&__IPSBAR[0x000400]))
|
||||
#define MCF_TIMER_DTXMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000402]))
|
||||
#define MCF_TIMER_DTER0 (*(vuint8 *)(void*)(&__IPSBAR[0x000403]))
|
||||
#define MCF_TIMER_DTRR0 (*(vuint32*)(void*)(&__IPSBAR[0x000404]))
|
||||
#define MCF_TIMER_DTCR0 (*(vuint32*)(void*)(&__IPSBAR[0x000408]))
|
||||
#define MCF_TIMER_DTCN0 (*(vuint32*)(void*)(&__IPSBAR[0x00040C]))
|
||||
#define MCF_TIMER_DTMR1 (*(vuint16*)(void*)(&__IPSBAR[0x000440]))
|
||||
#define MCF_TIMER_DTXMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000442]))
|
||||
#define MCF_TIMER_DTER1 (*(vuint8 *)(void*)(&__IPSBAR[0x000443]))
|
||||
#define MCF_TIMER_DTRR1 (*(vuint32*)(void*)(&__IPSBAR[0x000444]))
|
||||
#define MCF_TIMER_DTCR1 (*(vuint32*)(void*)(&__IPSBAR[0x000448]))
|
||||
#define MCF_TIMER_DTCN1 (*(vuint32*)(void*)(&__IPSBAR[0x00044C]))
|
||||
#define MCF_TIMER_DTMR2 (*(vuint16*)(void*)(&__IPSBAR[0x000480]))
|
||||
#define MCF_TIMER_DTXMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000482]))
|
||||
#define MCF_TIMER_DTER2 (*(vuint8 *)(void*)(&__IPSBAR[0x000483]))
|
||||
#define MCF_TIMER_DTRR2 (*(vuint32*)(void*)(&__IPSBAR[0x000484]))
|
||||
#define MCF_TIMER_DTCR2 (*(vuint32*)(void*)(&__IPSBAR[0x000488]))
|
||||
#define MCF_TIMER_DTCN2 (*(vuint32*)(void*)(&__IPSBAR[0x00048C]))
|
||||
#define MCF_TIMER_DTMR3 (*(vuint16*)(void*)(&__IPSBAR[0x0004C0]))
|
||||
#define MCF_TIMER_DTXMR3 (*(vuint8 *)(void*)(&__IPSBAR[0x0004C2]))
|
||||
#define MCF_TIMER_DTER3 (*(vuint8 *)(void*)(&__IPSBAR[0x0004C3]))
|
||||
#define MCF_TIMER_DTRR3 (*(vuint32*)(void*)(&__IPSBAR[0x0004C4]))
|
||||
#define MCF_TIMER_DTCR3 (*(vuint32*)(void*)(&__IPSBAR[0x0004C8]))
|
||||
#define MCF_TIMER_DTCN3 (*(vuint32*)(void*)(&__IPSBAR[0x0004CC]))
|
||||
#define MCF_TIMER_DTMR(x) (*(vuint16*)(void*)(&__IPSBAR[0x000400+((x)*0x040)]))
|
||||
#define MCF_TIMER_DTXMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000402+((x)*0x040)]))
|
||||
#define MCF_TIMER_DTER(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000403+((x)*0x040)]))
|
||||
#define MCF_TIMER_DTRR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000404+((x)*0x040)]))
|
||||
#define MCF_TIMER_DTCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000408+((x)*0x040)]))
|
||||
#define MCF_TIMER_DTCN(x) (*(vuint32*)(void*)(&__IPSBAR[0x00040C+((x)*0x040)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_TIMER_DTMR */
|
||||
#define MCF_TIMER_DTMR_RST (0x0001)
|
||||
#define MCF_TIMER_DTMR_CLK(x) (((x)&0x0003)<<1)
|
||||
#define MCF_TIMER_DTMR_FRR (0x0008)
|
||||
#define MCF_TIMER_DTMR_ORRI (0x0010)
|
||||
#define MCF_TIMER_DTMR_OM (0x0020)
|
||||
#define MCF_TIMER_DTMR_CE(x) (((x)&0x0003)<<6)
|
||||
#define MCF_TIMER_DTMR_PS(x) (((x)&0x00FF)<<8)
|
||||
#define MCF_TIMER_DTMR_CE_ANY (0x00C0)
|
||||
#define MCF_TIMER_DTMR_CE_FALL (0x0080)
|
||||
#define MCF_TIMER_DTMR_CE_RISE (0x0040)
|
||||
#define MCF_TIMER_DTMR_CE_NONE (0x0000)
|
||||
#define MCF_TIMER_DTMR_CLK_DTIN (0x0006)
|
||||
#define MCF_TIMER_DTMR_CLK_DIV16 (0x0004)
|
||||
#define MCF_TIMER_DTMR_CLK_DIV1 (0x0002)
|
||||
#define MCF_TIMER_DTMR_CLK_STOP (0x0000)
|
||||
|
||||
/* Bit definitions and macros for MCF_TIMER_DTXMR */
|
||||
#define MCF_TIMER_DTXMR_MODE16 (0x01)
|
||||
#define MCF_TIMER_DTXMR_DMAEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_TIMER_DTER */
|
||||
#define MCF_TIMER_DTER_CAP (0x01)
|
||||
#define MCF_TIMER_DTER_REF (0x02)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_TIMER_H__ */
|
||||
|
|
|
|||
|
|
@ -1,186 +1,186 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_uart.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_UART_H__
|
||||
#define __MCF523X_UART_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Universal Asynchronous Receiver Transmitter (UART)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_UART_UMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000200]))
|
||||
#define MCF_UART_USR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000204]))
|
||||
#define MCF_UART_UCSR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000204]))
|
||||
#define MCF_UART_UCR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000208]))
|
||||
#define MCF_UART_URB0 (*(vuint8 *)(void*)(&__IPSBAR[0x00020C]))
|
||||
#define MCF_UART_UTB0 (*(vuint8 *)(void*)(&__IPSBAR[0x00020C]))
|
||||
#define MCF_UART_UIPCR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000210]))
|
||||
#define MCF_UART_UACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000210]))
|
||||
#define MCF_UART_UISR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000214]))
|
||||
#define MCF_UART_UIMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000214]))
|
||||
#define MCF_UART_UBG10 (*(vuint8 *)(void*)(&__IPSBAR[0x000218]))
|
||||
#define MCF_UART_UBG20 (*(vuint8 *)(void*)(&__IPSBAR[0x00021C]))
|
||||
#define MCF_UART_UIP0 (*(vuint8 *)(void*)(&__IPSBAR[0x000234]))
|
||||
#define MCF_UART_UOP10 (*(vuint8 *)(void*)(&__IPSBAR[0x000238]))
|
||||
#define MCF_UART_UOP00 (*(vuint8 *)(void*)(&__IPSBAR[0x00023C]))
|
||||
#define MCF_UART_UMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000240]))
|
||||
#define MCF_UART_USR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000244]))
|
||||
#define MCF_UART_UCSR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000244]))
|
||||
#define MCF_UART_UCR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000248]))
|
||||
#define MCF_UART_URB1 (*(vuint8 *)(void*)(&__IPSBAR[0x00024C]))
|
||||
#define MCF_UART_UTB1 (*(vuint8 *)(void*)(&__IPSBAR[0x00024C]))
|
||||
#define MCF_UART_UIPCR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000250]))
|
||||
#define MCF_UART_UACR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000250]))
|
||||
#define MCF_UART_UISR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000254]))
|
||||
#define MCF_UART_UIMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000254]))
|
||||
#define MCF_UART_UBG11 (*(vuint8 *)(void*)(&__IPSBAR[0x000258]))
|
||||
#define MCF_UART_UBG21 (*(vuint8 *)(void*)(&__IPSBAR[0x00025C]))
|
||||
#define MCF_UART_UIP1 (*(vuint8 *)(void*)(&__IPSBAR[0x000274]))
|
||||
#define MCF_UART_UOP11 (*(vuint8 *)(void*)(&__IPSBAR[0x000278]))
|
||||
#define MCF_UART_UOP01 (*(vuint8 *)(void*)(&__IPSBAR[0x00027C]))
|
||||
#define MCF_UART_UMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000280]))
|
||||
#define MCF_UART_USR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000284]))
|
||||
#define MCF_UART_UCSR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000284]))
|
||||
#define MCF_UART_UCR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000288]))
|
||||
#define MCF_UART_URB2 (*(vuint8 *)(void*)(&__IPSBAR[0x00028C]))
|
||||
#define MCF_UART_UTB2 (*(vuint8 *)(void*)(&__IPSBAR[0x00028C]))
|
||||
#define MCF_UART_UIPCR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000290]))
|
||||
#define MCF_UART_UACR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000290]))
|
||||
#define MCF_UART_UISR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000294]))
|
||||
#define MCF_UART_UIMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000294]))
|
||||
#define MCF_UART_UBG12 (*(vuint8 *)(void*)(&__IPSBAR[0x000298]))
|
||||
#define MCF_UART_UBG22 (*(vuint8 *)(void*)(&__IPSBAR[0x00029C]))
|
||||
#define MCF_UART_UIP2 (*(vuint8 *)(void*)(&__IPSBAR[0x0002B4]))
|
||||
#define MCF_UART_UOP12 (*(vuint8 *)(void*)(&__IPSBAR[0x0002B8]))
|
||||
#define MCF_UART_UOP02 (*(vuint8 *)(void*)(&__IPSBAR[0x0002BC]))
|
||||
#define MCF_UART_UMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000200+((x)*0x040)]))
|
||||
#define MCF_UART_USR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)]))
|
||||
#define MCF_UART_UCSR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)]))
|
||||
#define MCF_UART_UCR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000208+((x)*0x040)]))
|
||||
#define MCF_UART_URB(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)]))
|
||||
#define MCF_UART_UTB(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)]))
|
||||
#define MCF_UART_UIPCR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)]))
|
||||
#define MCF_UART_UACR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)]))
|
||||
#define MCF_UART_UISR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)]))
|
||||
#define MCF_UART_UIMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)]))
|
||||
#define MCF_UART_UBG1(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000218+((x)*0x040)]))
|
||||
#define MCF_UART_UBG2(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00021C+((x)*0x040)]))
|
||||
#define MCF_UART_UIP(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000234+((x)*0x040)]))
|
||||
#define MCF_UART_UOP1(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000238+((x)*0x040)]))
|
||||
#define MCF_UART_UOP0(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00023C+((x)*0x040)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UMR */
|
||||
#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0)
|
||||
#define MCF_UART_UMR_PT (0x04)
|
||||
#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3)
|
||||
#define MCF_UART_UMR_ERR (0x20)
|
||||
#define MCF_UART_UMR_RXIRQ (0x40)
|
||||
#define MCF_UART_UMR_RXRTS (0x80)
|
||||
#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0)
|
||||
#define MCF_UART_UMR_TXCTS (0x10)
|
||||
#define MCF_UART_UMR_TXRTS (0x20)
|
||||
#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6)
|
||||
#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C)
|
||||
#define MCF_UART_UMR_PM_MULTI_DATA (0x18)
|
||||
#define MCF_UART_UMR_PM_NONE (0x10)
|
||||
#define MCF_UART_UMR_PM_FORCE_HI (0x0C)
|
||||
#define MCF_UART_UMR_PM_FORCE_LO (0x08)
|
||||
#define MCF_UART_UMR_PM_ODD (0x04)
|
||||
#define MCF_UART_UMR_PM_EVEN (0x00)
|
||||
#define MCF_UART_UMR_BC_5 (0x00)
|
||||
#define MCF_UART_UMR_BC_6 (0x01)
|
||||
#define MCF_UART_UMR_BC_7 (0x02)
|
||||
#define MCF_UART_UMR_BC_8 (0x03)
|
||||
#define MCF_UART_UMR_CM_NORMAL (0x00)
|
||||
#define MCF_UART_UMR_CM_ECHO (0x40)
|
||||
#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80)
|
||||
#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0)
|
||||
#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07)
|
||||
#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08)
|
||||
#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_USR */
|
||||
#define MCF_UART_USR_RXRDY (0x01)
|
||||
#define MCF_UART_USR_FFULL (0x02)
|
||||
#define MCF_UART_USR_TXRDY (0x04)
|
||||
#define MCF_UART_USR_TXEMP (0x08)
|
||||
#define MCF_UART_USR_OE (0x10)
|
||||
#define MCF_UART_USR_PE (0x20)
|
||||
#define MCF_UART_USR_FE (0x40)
|
||||
#define MCF_UART_USR_RB (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UCSR */
|
||||
#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0)
|
||||
#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4)
|
||||
#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0)
|
||||
#define MCF_UART_UCSR_RCS_CTM16 (0xE0)
|
||||
#define MCF_UART_UCSR_RCS_CTM (0xF0)
|
||||
#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D)
|
||||
#define MCF_UART_UCSR_TCS_CTM16 (0x0E)
|
||||
#define MCF_UART_UCSR_TCS_CTM (0x0F)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UCR */
|
||||
#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0)
|
||||
#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2)
|
||||
#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4)
|
||||
#define MCF_UART_UCR_NONE (0x00)
|
||||
#define MCF_UART_UCR_STOP_BREAK (0x70)
|
||||
#define MCF_UART_UCR_START_BREAK (0x60)
|
||||
#define MCF_UART_UCR_BKCHGINT (0x50)
|
||||
#define MCF_UART_UCR_RESET_ERROR (0x40)
|
||||
#define MCF_UART_UCR_RESET_TX (0x30)
|
||||
#define MCF_UART_UCR_RESET_RX (0x20)
|
||||
#define MCF_UART_UCR_RESET_MR (0x10)
|
||||
#define MCF_UART_UCR_TX_DISABLED (0x08)
|
||||
#define MCF_UART_UCR_TX_ENABLED (0x04)
|
||||
#define MCF_UART_UCR_RX_DISABLED (0x02)
|
||||
#define MCF_UART_UCR_RX_ENABLED (0x01)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UIPCR */
|
||||
#define MCF_UART_UIPCR_CTS (0x01)
|
||||
#define MCF_UART_UIPCR_COS (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UACR */
|
||||
#define MCF_UART_UACR_IEC (0x01)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UISR */
|
||||
#define MCF_UART_UISR_TXRDY (0x01)
|
||||
#define MCF_UART_UISR_RXRDY_FU (0x02)
|
||||
#define MCF_UART_UISR_DB (0x04)
|
||||
#define MCF_UART_UISR_RXFTO (0x08)
|
||||
#define MCF_UART_UISR_TXFIFO (0x10)
|
||||
#define MCF_UART_UISR_RXFIFO (0x20)
|
||||
#define MCF_UART_UISR_COS (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UIMR */
|
||||
#define MCF_UART_UIMR_TXRDY (0x01)
|
||||
#define MCF_UART_UIMR_RXRDY_FU (0x02)
|
||||
#define MCF_UART_UIMR_DB (0x04)
|
||||
#define MCF_UART_UIMR_COS (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UIP */
|
||||
#define MCF_UART_UIP_CTS (0x01)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UOP1 */
|
||||
#define MCF_UART_UOP1_RTS (0x01)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UOP0 */
|
||||
#define MCF_UART_UOP0_RTS (0x01)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_UART_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_uart.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_UART_H__
|
||||
#define __MCF523X_UART_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Universal Asynchronous Receiver Transmitter (UART)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_UART_UMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000200]))
|
||||
#define MCF_UART_USR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000204]))
|
||||
#define MCF_UART_UCSR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000204]))
|
||||
#define MCF_UART_UCR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000208]))
|
||||
#define MCF_UART_URB0 (*(vuint8 *)(void*)(&__IPSBAR[0x00020C]))
|
||||
#define MCF_UART_UTB0 (*(vuint8 *)(void*)(&__IPSBAR[0x00020C]))
|
||||
#define MCF_UART_UIPCR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000210]))
|
||||
#define MCF_UART_UACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000210]))
|
||||
#define MCF_UART_UISR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000214]))
|
||||
#define MCF_UART_UIMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000214]))
|
||||
#define MCF_UART_UBG10 (*(vuint8 *)(void*)(&__IPSBAR[0x000218]))
|
||||
#define MCF_UART_UBG20 (*(vuint8 *)(void*)(&__IPSBAR[0x00021C]))
|
||||
#define MCF_UART_UIP0 (*(vuint8 *)(void*)(&__IPSBAR[0x000234]))
|
||||
#define MCF_UART_UOP10 (*(vuint8 *)(void*)(&__IPSBAR[0x000238]))
|
||||
#define MCF_UART_UOP00 (*(vuint8 *)(void*)(&__IPSBAR[0x00023C]))
|
||||
#define MCF_UART_UMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000240]))
|
||||
#define MCF_UART_USR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000244]))
|
||||
#define MCF_UART_UCSR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000244]))
|
||||
#define MCF_UART_UCR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000248]))
|
||||
#define MCF_UART_URB1 (*(vuint8 *)(void*)(&__IPSBAR[0x00024C]))
|
||||
#define MCF_UART_UTB1 (*(vuint8 *)(void*)(&__IPSBAR[0x00024C]))
|
||||
#define MCF_UART_UIPCR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000250]))
|
||||
#define MCF_UART_UACR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000250]))
|
||||
#define MCF_UART_UISR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000254]))
|
||||
#define MCF_UART_UIMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000254]))
|
||||
#define MCF_UART_UBG11 (*(vuint8 *)(void*)(&__IPSBAR[0x000258]))
|
||||
#define MCF_UART_UBG21 (*(vuint8 *)(void*)(&__IPSBAR[0x00025C]))
|
||||
#define MCF_UART_UIP1 (*(vuint8 *)(void*)(&__IPSBAR[0x000274]))
|
||||
#define MCF_UART_UOP11 (*(vuint8 *)(void*)(&__IPSBAR[0x000278]))
|
||||
#define MCF_UART_UOP01 (*(vuint8 *)(void*)(&__IPSBAR[0x00027C]))
|
||||
#define MCF_UART_UMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000280]))
|
||||
#define MCF_UART_USR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000284]))
|
||||
#define MCF_UART_UCSR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000284]))
|
||||
#define MCF_UART_UCR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000288]))
|
||||
#define MCF_UART_URB2 (*(vuint8 *)(void*)(&__IPSBAR[0x00028C]))
|
||||
#define MCF_UART_UTB2 (*(vuint8 *)(void*)(&__IPSBAR[0x00028C]))
|
||||
#define MCF_UART_UIPCR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000290]))
|
||||
#define MCF_UART_UACR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000290]))
|
||||
#define MCF_UART_UISR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000294]))
|
||||
#define MCF_UART_UIMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000294]))
|
||||
#define MCF_UART_UBG12 (*(vuint8 *)(void*)(&__IPSBAR[0x000298]))
|
||||
#define MCF_UART_UBG22 (*(vuint8 *)(void*)(&__IPSBAR[0x00029C]))
|
||||
#define MCF_UART_UIP2 (*(vuint8 *)(void*)(&__IPSBAR[0x0002B4]))
|
||||
#define MCF_UART_UOP12 (*(vuint8 *)(void*)(&__IPSBAR[0x0002B8]))
|
||||
#define MCF_UART_UOP02 (*(vuint8 *)(void*)(&__IPSBAR[0x0002BC]))
|
||||
#define MCF_UART_UMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000200+((x)*0x040)]))
|
||||
#define MCF_UART_USR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)]))
|
||||
#define MCF_UART_UCSR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)]))
|
||||
#define MCF_UART_UCR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000208+((x)*0x040)]))
|
||||
#define MCF_UART_URB(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)]))
|
||||
#define MCF_UART_UTB(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)]))
|
||||
#define MCF_UART_UIPCR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)]))
|
||||
#define MCF_UART_UACR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)]))
|
||||
#define MCF_UART_UISR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)]))
|
||||
#define MCF_UART_UIMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)]))
|
||||
#define MCF_UART_UBG1(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000218+((x)*0x040)]))
|
||||
#define MCF_UART_UBG2(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00021C+((x)*0x040)]))
|
||||
#define MCF_UART_UIP(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000234+((x)*0x040)]))
|
||||
#define MCF_UART_UOP1(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000238+((x)*0x040)]))
|
||||
#define MCF_UART_UOP0(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00023C+((x)*0x040)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UMR */
|
||||
#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0)
|
||||
#define MCF_UART_UMR_PT (0x04)
|
||||
#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3)
|
||||
#define MCF_UART_UMR_ERR (0x20)
|
||||
#define MCF_UART_UMR_RXIRQ (0x40)
|
||||
#define MCF_UART_UMR_RXRTS (0x80)
|
||||
#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0)
|
||||
#define MCF_UART_UMR_TXCTS (0x10)
|
||||
#define MCF_UART_UMR_TXRTS (0x20)
|
||||
#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6)
|
||||
#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C)
|
||||
#define MCF_UART_UMR_PM_MULTI_DATA (0x18)
|
||||
#define MCF_UART_UMR_PM_NONE (0x10)
|
||||
#define MCF_UART_UMR_PM_FORCE_HI (0x0C)
|
||||
#define MCF_UART_UMR_PM_FORCE_LO (0x08)
|
||||
#define MCF_UART_UMR_PM_ODD (0x04)
|
||||
#define MCF_UART_UMR_PM_EVEN (0x00)
|
||||
#define MCF_UART_UMR_BC_5 (0x00)
|
||||
#define MCF_UART_UMR_BC_6 (0x01)
|
||||
#define MCF_UART_UMR_BC_7 (0x02)
|
||||
#define MCF_UART_UMR_BC_8 (0x03)
|
||||
#define MCF_UART_UMR_CM_NORMAL (0x00)
|
||||
#define MCF_UART_UMR_CM_ECHO (0x40)
|
||||
#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80)
|
||||
#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0)
|
||||
#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07)
|
||||
#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08)
|
||||
#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_USR */
|
||||
#define MCF_UART_USR_RXRDY (0x01)
|
||||
#define MCF_UART_USR_FFULL (0x02)
|
||||
#define MCF_UART_USR_TXRDY (0x04)
|
||||
#define MCF_UART_USR_TXEMP (0x08)
|
||||
#define MCF_UART_USR_OE (0x10)
|
||||
#define MCF_UART_USR_PE (0x20)
|
||||
#define MCF_UART_USR_FE (0x40)
|
||||
#define MCF_UART_USR_RB (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UCSR */
|
||||
#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0)
|
||||
#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4)
|
||||
#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0)
|
||||
#define MCF_UART_UCSR_RCS_CTM16 (0xE0)
|
||||
#define MCF_UART_UCSR_RCS_CTM (0xF0)
|
||||
#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D)
|
||||
#define MCF_UART_UCSR_TCS_CTM16 (0x0E)
|
||||
#define MCF_UART_UCSR_TCS_CTM (0x0F)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UCR */
|
||||
#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0)
|
||||
#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2)
|
||||
#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4)
|
||||
#define MCF_UART_UCR_NONE (0x00)
|
||||
#define MCF_UART_UCR_STOP_BREAK (0x70)
|
||||
#define MCF_UART_UCR_START_BREAK (0x60)
|
||||
#define MCF_UART_UCR_BKCHGINT (0x50)
|
||||
#define MCF_UART_UCR_RESET_ERROR (0x40)
|
||||
#define MCF_UART_UCR_RESET_TX (0x30)
|
||||
#define MCF_UART_UCR_RESET_RX (0x20)
|
||||
#define MCF_UART_UCR_RESET_MR (0x10)
|
||||
#define MCF_UART_UCR_TX_DISABLED (0x08)
|
||||
#define MCF_UART_UCR_TX_ENABLED (0x04)
|
||||
#define MCF_UART_UCR_RX_DISABLED (0x02)
|
||||
#define MCF_UART_UCR_RX_ENABLED (0x01)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UIPCR */
|
||||
#define MCF_UART_UIPCR_CTS (0x01)
|
||||
#define MCF_UART_UIPCR_COS (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UACR */
|
||||
#define MCF_UART_UACR_IEC (0x01)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UISR */
|
||||
#define MCF_UART_UISR_TXRDY (0x01)
|
||||
#define MCF_UART_UISR_RXRDY_FU (0x02)
|
||||
#define MCF_UART_UISR_DB (0x04)
|
||||
#define MCF_UART_UISR_RXFTO (0x08)
|
||||
#define MCF_UART_UISR_TXFIFO (0x10)
|
||||
#define MCF_UART_UISR_RXFIFO (0x20)
|
||||
#define MCF_UART_UISR_COS (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UIMR */
|
||||
#define MCF_UART_UIMR_TXRDY (0x01)
|
||||
#define MCF_UART_UIMR_RXRDY_FU (0x02)
|
||||
#define MCF_UART_UIMR_DB (0x04)
|
||||
#define MCF_UART_UIMR_COS (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UIP */
|
||||
#define MCF_UART_UIP_CTS (0x01)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UOP1 */
|
||||
#define MCF_UART_UOP1_RTS (0x01)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UOP0 */
|
||||
#define MCF_UART_UOP0_RTS (0x01)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_UART_H__ */
|
||||
|
|
|
|||
|
|
@ -1,92 +1,92 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_wtm.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_WTM_H__
|
||||
#define __MCF523X_WTM_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Watchdog Timer Modules (WTM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_WTM_WCR (*(vuint16*)(void*)(&__IPSBAR[0x140000]))
|
||||
#define MCF_WTM_WMR (*(vuint16*)(void*)(&__IPSBAR[0x140002]))
|
||||
#define MCF_WTM_WCNTR (*(vuint16*)(void*)(&__IPSBAR[0x140004]))
|
||||
#define MCF_WTM_WSR (*(vuint16*)(void*)(&__IPSBAR[0x140006]))
|
||||
|
||||
/* Bit definitions and macros for MCF_WTM_WCR */
|
||||
#define MCF_WTM_WCR_EN (0x0001)
|
||||
#define MCF_WTM_WCR_HALTED (0x0002)
|
||||
#define MCF_WTM_WCR_DOZE (0x0004)
|
||||
#define MCF_WTM_WCR_WAIT (0x0008)
|
||||
|
||||
/* Bit definitions and macros for MCF_WTM_WMR */
|
||||
#define MCF_WTM_WMR_WM0 (0x0001)
|
||||
#define MCF_WTM_WMR_WM1 (0x0002)
|
||||
#define MCF_WTM_WMR_WM2 (0x0004)
|
||||
#define MCF_WTM_WMR_WM3 (0x0008)
|
||||
#define MCF_WTM_WMR_WM4 (0x0010)
|
||||
#define MCF_WTM_WMR_WM5 (0x0020)
|
||||
#define MCF_WTM_WMR_WM6 (0x0040)
|
||||
#define MCF_WTM_WMR_WM7 (0x0080)
|
||||
#define MCF_WTM_WMR_WM8 (0x0100)
|
||||
#define MCF_WTM_WMR_WM9 (0x0200)
|
||||
#define MCF_WTM_WMR_WM10 (0x0400)
|
||||
#define MCF_WTM_WMR_WM11 (0x0800)
|
||||
#define MCF_WTM_WMR_WM12 (0x1000)
|
||||
#define MCF_WTM_WMR_WM13 (0x2000)
|
||||
#define MCF_WTM_WMR_WM14 (0x4000)
|
||||
#define MCF_WTM_WMR_WM15 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_WTM_WCNTR */
|
||||
#define MCF_WTM_WCNTR_WC0 (0x0001)
|
||||
#define MCF_WTM_WCNTR_WC1 (0x0002)
|
||||
#define MCF_WTM_WCNTR_WC2 (0x0004)
|
||||
#define MCF_WTM_WCNTR_WC3 (0x0008)
|
||||
#define MCF_WTM_WCNTR_WC4 (0x0010)
|
||||
#define MCF_WTM_WCNTR_WC5 (0x0020)
|
||||
#define MCF_WTM_WCNTR_WC6 (0x0040)
|
||||
#define MCF_WTM_WCNTR_WC7 (0x0080)
|
||||
#define MCF_WTM_WCNTR_WC8 (0x0100)
|
||||
#define MCF_WTM_WCNTR_WC9 (0x0200)
|
||||
#define MCF_WTM_WCNTR_WC10 (0x0400)
|
||||
#define MCF_WTM_WCNTR_WC11 (0x0800)
|
||||
#define MCF_WTM_WCNTR_WC12 (0x1000)
|
||||
#define MCF_WTM_WCNTR_WC13 (0x2000)
|
||||
#define MCF_WTM_WCNTR_WC14 (0x4000)
|
||||
#define MCF_WTM_WCNTR_WC15 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_WTM_WSR */
|
||||
#define MCF_WTM_WSR_WS0 (0x0001)
|
||||
#define MCF_WTM_WSR_WS1 (0x0002)
|
||||
#define MCF_WTM_WSR_WS2 (0x0004)
|
||||
#define MCF_WTM_WSR_WS3 (0x0008)
|
||||
#define MCF_WTM_WSR_WS4 (0x0010)
|
||||
#define MCF_WTM_WSR_WS5 (0x0020)
|
||||
#define MCF_WTM_WSR_WS6 (0x0040)
|
||||
#define MCF_WTM_WSR_WS7 (0x0080)
|
||||
#define MCF_WTM_WSR_WS8 (0x0100)
|
||||
#define MCF_WTM_WSR_WS9 (0x0200)
|
||||
#define MCF_WTM_WSR_WS10 (0x0400)
|
||||
#define MCF_WTM_WSR_WS11 (0x0800)
|
||||
#define MCF_WTM_WSR_WS12 (0x1000)
|
||||
#define MCF_WTM_WSR_WS13 (0x2000)
|
||||
#define MCF_WTM_WSR_WS14 (0x4000)
|
||||
#define MCF_WTM_WSR_WS15 (0x8000)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_WTM_H__ */
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf523x_wtm.h
|
||||
* Purpose: Register and bit definitions for the MCF523X
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MCF523X_WTM_H__
|
||||
#define __MCF523X_WTM_H__
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Watchdog Timer Modules (WTM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_WTM_WCR (*(vuint16*)(void*)(&__IPSBAR[0x140000]))
|
||||
#define MCF_WTM_WMR (*(vuint16*)(void*)(&__IPSBAR[0x140002]))
|
||||
#define MCF_WTM_WCNTR (*(vuint16*)(void*)(&__IPSBAR[0x140004]))
|
||||
#define MCF_WTM_WSR (*(vuint16*)(void*)(&__IPSBAR[0x140006]))
|
||||
|
||||
/* Bit definitions and macros for MCF_WTM_WCR */
|
||||
#define MCF_WTM_WCR_EN (0x0001)
|
||||
#define MCF_WTM_WCR_HALTED (0x0002)
|
||||
#define MCF_WTM_WCR_DOZE (0x0004)
|
||||
#define MCF_WTM_WCR_WAIT (0x0008)
|
||||
|
||||
/* Bit definitions and macros for MCF_WTM_WMR */
|
||||
#define MCF_WTM_WMR_WM0 (0x0001)
|
||||
#define MCF_WTM_WMR_WM1 (0x0002)
|
||||
#define MCF_WTM_WMR_WM2 (0x0004)
|
||||
#define MCF_WTM_WMR_WM3 (0x0008)
|
||||
#define MCF_WTM_WMR_WM4 (0x0010)
|
||||
#define MCF_WTM_WMR_WM5 (0x0020)
|
||||
#define MCF_WTM_WMR_WM6 (0x0040)
|
||||
#define MCF_WTM_WMR_WM7 (0x0080)
|
||||
#define MCF_WTM_WMR_WM8 (0x0100)
|
||||
#define MCF_WTM_WMR_WM9 (0x0200)
|
||||
#define MCF_WTM_WMR_WM10 (0x0400)
|
||||
#define MCF_WTM_WMR_WM11 (0x0800)
|
||||
#define MCF_WTM_WMR_WM12 (0x1000)
|
||||
#define MCF_WTM_WMR_WM13 (0x2000)
|
||||
#define MCF_WTM_WMR_WM14 (0x4000)
|
||||
#define MCF_WTM_WMR_WM15 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_WTM_WCNTR */
|
||||
#define MCF_WTM_WCNTR_WC0 (0x0001)
|
||||
#define MCF_WTM_WCNTR_WC1 (0x0002)
|
||||
#define MCF_WTM_WCNTR_WC2 (0x0004)
|
||||
#define MCF_WTM_WCNTR_WC3 (0x0008)
|
||||
#define MCF_WTM_WCNTR_WC4 (0x0010)
|
||||
#define MCF_WTM_WCNTR_WC5 (0x0020)
|
||||
#define MCF_WTM_WCNTR_WC6 (0x0040)
|
||||
#define MCF_WTM_WCNTR_WC7 (0x0080)
|
||||
#define MCF_WTM_WCNTR_WC8 (0x0100)
|
||||
#define MCF_WTM_WCNTR_WC9 (0x0200)
|
||||
#define MCF_WTM_WCNTR_WC10 (0x0400)
|
||||
#define MCF_WTM_WCNTR_WC11 (0x0800)
|
||||
#define MCF_WTM_WCNTR_WC12 (0x1000)
|
||||
#define MCF_WTM_WCNTR_WC13 (0x2000)
|
||||
#define MCF_WTM_WCNTR_WC14 (0x4000)
|
||||
#define MCF_WTM_WCNTR_WC15 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_WTM_WSR */
|
||||
#define MCF_WTM_WSR_WS0 (0x0001)
|
||||
#define MCF_WTM_WSR_WS1 (0x0002)
|
||||
#define MCF_WTM_WSR_WS2 (0x0004)
|
||||
#define MCF_WTM_WSR_WS3 (0x0008)
|
||||
#define MCF_WTM_WSR_WS4 (0x0010)
|
||||
#define MCF_WTM_WSR_WS5 (0x0020)
|
||||
#define MCF_WTM_WSR_WS6 (0x0040)
|
||||
#define MCF_WTM_WSR_WS7 (0x0080)
|
||||
#define MCF_WTM_WSR_WS8 (0x0100)
|
||||
#define MCF_WTM_WSR_WS9 (0x0200)
|
||||
#define MCF_WTM_WSR_WS10 (0x0400)
|
||||
#define MCF_WTM_WSR_WS11 (0x0800)
|
||||
#define MCF_WTM_WSR_WS12 (0x1000)
|
||||
#define MCF_WTM_WSR_WS13 (0x2000)
|
||||
#define MCF_WTM_WSR_WS14 (0x4000)
|
||||
#define MCF_WTM_WSR_WS15 (0x8000)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* __MCF523X_WTM_H__ */
|
||||
|
|
|
|||
|
|
@ -1,196 +1,196 @@
|
|||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf5xxx.h
|
||||
* Purpose: Definitions common to all ColdFire processors
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _CPU_MCF5XXX_H
|
||||
#define _CPU_MCF5XXX_H
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* Misc. Defines
|
||||
*/
|
||||
|
||||
#ifdef FALSE
|
||||
#undef FALSE
|
||||
#endif
|
||||
#define FALSE (0)
|
||||
|
||||
#ifdef TRUE
|
||||
#undef TRUE
|
||||
#endif
|
||||
#define TRUE (1)
|
||||
|
||||
#ifdef NULL
|
||||
#undef NULL
|
||||
#endif
|
||||
#define NULL (0)
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* The basic data types
|
||||
*/
|
||||
|
||||
typedef unsigned char uint8; /* 8 bits */
|
||||
typedef unsigned short int uint16; /* 16 bits */
|
||||
typedef unsigned long int uint32; /* 32 bits */
|
||||
|
||||
typedef signed char int8; /* 8 bits */
|
||||
typedef signed short int int16; /* 16 bits */
|
||||
typedef signed long int int32; /* 32 bits */
|
||||
|
||||
typedef volatile uint8 vuint8; /* 8 bits */
|
||||
typedef volatile uint16 vuint16; /* 16 bits */
|
||||
typedef volatile uint32 vuint32; /* 32 bits */
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* Common M68K & ColdFire definitions
|
||||
*/
|
||||
|
||||
#define ADDRESS uint32
|
||||
#define INSTRUCTION uint16
|
||||
#define ILLEGAL 0x4AFC
|
||||
#define CPU_WORD_SIZE 16
|
||||
|
||||
#define MCF5XXX_SR_T (0x8000)
|
||||
#define MCF5XXX_SR_S (0x2000)
|
||||
#define MCF5XXX_SR_M (0x1000)
|
||||
#define MCF5XXX_SR_IPL (0x0700)
|
||||
#define MCF5XXX_SR_IPL_0 (0x0000)
|
||||
#define MCF5XXX_SR_IPL_1 (0x0100)
|
||||
#define MCF5XXX_SR_IPL_2 (0x0200)
|
||||
#define MCF5XXX_SR_IPL_3 (0x0300)
|
||||
#define MCF5XXX_SR_IPL_4 (0x0400)
|
||||
#define MCF5XXX_SR_IPL_5 (0x0500)
|
||||
#define MCF5XXX_SR_IPL_6 (0x0600)
|
||||
#define MCF5XXX_SR_IPL_7 (0x0700)
|
||||
#define MCF5XXX_SR_X (0x0010)
|
||||
#define MCF5XXX_SR_N (0x0008)
|
||||
#define MCF5XXX_SR_Z (0x0004)
|
||||
#define MCF5XXX_SR_V (0x0002)
|
||||
#define MCF5XXX_SR_C (0x0001)
|
||||
|
||||
#define MCF5XXX_CACR_CENB (0x80000000)
|
||||
#define MCF5XXX_CACR_CPDI (0x10000000)
|
||||
#define MCF5XXX_CACR_CPD (0x10000000)
|
||||
#define MCF5XXX_CACR_CFRZ (0x08000000)
|
||||
#define MCF5XXX_CACR_CINV (0x01000000)
|
||||
#define MCF5XXX_CACR_DIDI (0x00800000)
|
||||
#define MCF5XXX_CACR_DISD (0x00400000)
|
||||
#define MCF5XXX_CACR_INVI (0x00200000)
|
||||
#define MCF5XXX_CACR_INVD (0x00100000)
|
||||
#define MCF5XXX_CACR_CEIB (0x00000400)
|
||||
#define MCF5XXX_CACR_DCM_WR (0x00000000)
|
||||
#define MCF5XXX_CACR_DCM_CB (0x00000100)
|
||||
#define MCF5XXX_CACR_DCM_IP (0x00000200)
|
||||
#define MCF5XXX_CACR_DCM (0x00000200)
|
||||
#define MCF5XXX_CACR_DCM_II (0x00000300)
|
||||
#define MCF5XXX_CACR_DBWE (0x00000100)
|
||||
#define MCF5XXX_CACR_DWP (0x00000020)
|
||||
#define MCF5XXX_CACR_EUST (0x00000010)
|
||||
#define MCF5XXX_CACR_CLNF_00 (0x00000000)
|
||||
#define MCF5XXX_CACR_CLNF_01 (0x00000002)
|
||||
#define MCF5XXX_CACR_CLNF_10 (0x00000004)
|
||||
#define MCF5XXX_CACR_CLNF_11 (0x00000006)
|
||||
|
||||
#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000)
|
||||
#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8)
|
||||
#define MCF5XXX_ACR_EN (0x00008000)
|
||||
#define MCF5XXX_ACR_SM_USER (0x00000000)
|
||||
#define MCF5XXX_ACR_SM_SUPER (0x00002000)
|
||||
#define MCF5XXX_ACR_SM_IGNORE (0x00006000)
|
||||
#define MCF5XXX_ACR_ENIB (0x00000080)
|
||||
#define MCF5XXX_ACR_CM (0x00000040)
|
||||
#define MCF5XXX_ACR_DCM_WR (0x00000000)
|
||||
#define MCF5XXX_ACR_DCM_CB (0x00000020)
|
||||
#define MCF5XXX_ACR_DCM_IP (0x00000040)
|
||||
#define MCF5XXX_ACR_DCM_II (0x00000060)
|
||||
#define MCF5XXX_ACR_CM (0x00000040)
|
||||
#define MCF5XXX_ACR_BWE (0x00000020)
|
||||
#define MCF5XXX_ACR_WP (0x00000004)
|
||||
|
||||
#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000)
|
||||
#define MCF5XXX_RAMBAR_PRI_00 (0x00000000)
|
||||
#define MCF5XXX_RAMBAR_PRI_01 (0x00004000)
|
||||
#define MCF5XXX_RAMBAR_PRI_10 (0x00008000)
|
||||
#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000)
|
||||
#define MCF5XXX_RAMBAR_WP (0x00000100)
|
||||
#define MCF5XXX_RAMBAR_CI (0x00000020)
|
||||
#define MCF5XXX_RAMBAR_SC (0x00000010)
|
||||
#define MCF5XXX_RAMBAR_SD (0x00000008)
|
||||
#define MCF5XXX_RAMBAR_UC (0x00000004)
|
||||
#define MCF5XXX_RAMBAR_UD (0x00000002)
|
||||
#define MCF5XXX_RAMBAR_V (0x00000001)
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* The ColdFire family of processors has a simplified exception stack
|
||||
* frame that looks like the following:
|
||||
*
|
||||
* 3322222222221111 111111
|
||||
* 1098765432109876 5432109876543210
|
||||
* 8 +----------------+----------------+
|
||||
* | Program Counter |
|
||||
* 4 +----------------+----------------+
|
||||
* |FS/Fmt/Vector/FS| SR |
|
||||
* SP --> 0 +----------------+----------------+
|
||||
*
|
||||
* The stack self-aligns to a 4-byte boundary at an exception, with
|
||||
* the FS/Fmt/Vector/FS field indicating the size of the adjustment
|
||||
* (SP += 0,1,2,3 bytes).
|
||||
*/
|
||||
|
||||
#define MCF5XXX_RD_SF_FORMAT(PTR) \
|
||||
((*((uint16 *)(PTR)) >> 12) & 0x00FF)
|
||||
|
||||
#define MCF5XXX_RD_SF_VECTOR(PTR) \
|
||||
((*((uint16 *)(PTR)) >> 2) & 0x00FF)
|
||||
|
||||
#define MCF5XXX_RD_SF_FS(PTR) \
|
||||
( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) )
|
||||
|
||||
#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1)
|
||||
#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1)
|
||||
|
||||
/********************************************************************/
|
||||
/*
|
||||
* Functions provided by mcf5xxx.s
|
||||
*/
|
||||
|
||||
int asm_set_ipl (uint32);
|
||||
void mcf5xxx_wr_cacr (uint32);
|
||||
void mcf5xxx_wr_acr0 (uint32);
|
||||
void mcf5xxx_wr_acr1 (uint32);
|
||||
void mcf5xxx_wr_acr2 (uint32);
|
||||
void mcf5xxx_wr_acr3 (uint32);
|
||||
void mcf5xxx_wr_other_a7 (uint32);
|
||||
void mcf5xxx_wr_other_sp (uint32);
|
||||
void mcf5xxx_wr_vbr (uint32);
|
||||
void mcf5xxx_wr_macsr (uint32);
|
||||
void mcf5xxx_wr_mask (uint32);
|
||||
void mcf5xxx_wr_acc0 (uint32);
|
||||
void mcf5xxx_wr_accext01 (uint32);
|
||||
void mcf5xxx_wr_accext23 (uint32);
|
||||
void mcf5xxx_wr_acc1 (uint32);
|
||||
void mcf5xxx_wr_acc2 (uint32);
|
||||
void mcf5xxx_wr_acc3 (uint32);
|
||||
void mcf5xxx_wr_sr (uint32);
|
||||
void mcf5xxx_wr_rambar0 (uint32);
|
||||
void mcf5xxx_wr_rambar1 (uint32);
|
||||
void mcf5xxx_wr_mbar (uint32);
|
||||
void mcf5xxx_wr_mbar0 (uint32);
|
||||
void mcf5xxx_wr_mbar1 (uint32);
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* _CPU_MCF5XXX_H */
|
||||
|
||||
/*
|
||||
* These files are taken from the MCF523X source code example package
|
||||
* which is available on the Freescale website. Freescale explicitly
|
||||
* grants the redistribution and modification of these source files.
|
||||
* The complete licensing information is available in the file
|
||||
* LICENSE_FREESCALE.TXT.
|
||||
*
|
||||
* File: mcf5xxx.h
|
||||
* Purpose: Definitions common to all ColdFire processors
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _CPU_MCF5XXX_H
|
||||
#define _CPU_MCF5XXX_H
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* Misc. Defines
|
||||
*/
|
||||
|
||||
#ifdef FALSE
|
||||
#undef FALSE
|
||||
#endif
|
||||
#define FALSE (0)
|
||||
|
||||
#ifdef TRUE
|
||||
#undef TRUE
|
||||
#endif
|
||||
#define TRUE (1)
|
||||
|
||||
#ifdef NULL
|
||||
#undef NULL
|
||||
#endif
|
||||
#define NULL (0)
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* The basic data types
|
||||
*/
|
||||
|
||||
typedef unsigned char uint8; /* 8 bits */
|
||||
typedef unsigned short int uint16; /* 16 bits */
|
||||
typedef unsigned long int uint32; /* 32 bits */
|
||||
|
||||
typedef signed char int8; /* 8 bits */
|
||||
typedef signed short int int16; /* 16 bits */
|
||||
typedef signed long int int32; /* 32 bits */
|
||||
|
||||
typedef volatile uint8 vuint8; /* 8 bits */
|
||||
typedef volatile uint16 vuint16; /* 16 bits */
|
||||
typedef volatile uint32 vuint32; /* 32 bits */
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* Common M68K & ColdFire definitions
|
||||
*/
|
||||
|
||||
#define ADDRESS uint32
|
||||
#define INSTRUCTION uint16
|
||||
#define ILLEGAL 0x4AFC
|
||||
#define CPU_WORD_SIZE 16
|
||||
|
||||
#define MCF5XXX_SR_T (0x8000)
|
||||
#define MCF5XXX_SR_S (0x2000)
|
||||
#define MCF5XXX_SR_M (0x1000)
|
||||
#define MCF5XXX_SR_IPL (0x0700)
|
||||
#define MCF5XXX_SR_IPL_0 (0x0000)
|
||||
#define MCF5XXX_SR_IPL_1 (0x0100)
|
||||
#define MCF5XXX_SR_IPL_2 (0x0200)
|
||||
#define MCF5XXX_SR_IPL_3 (0x0300)
|
||||
#define MCF5XXX_SR_IPL_4 (0x0400)
|
||||
#define MCF5XXX_SR_IPL_5 (0x0500)
|
||||
#define MCF5XXX_SR_IPL_6 (0x0600)
|
||||
#define MCF5XXX_SR_IPL_7 (0x0700)
|
||||
#define MCF5XXX_SR_X (0x0010)
|
||||
#define MCF5XXX_SR_N (0x0008)
|
||||
#define MCF5XXX_SR_Z (0x0004)
|
||||
#define MCF5XXX_SR_V (0x0002)
|
||||
#define MCF5XXX_SR_C (0x0001)
|
||||
|
||||
#define MCF5XXX_CACR_CENB (0x80000000)
|
||||
#define MCF5XXX_CACR_CPDI (0x10000000)
|
||||
#define MCF5XXX_CACR_CPD (0x10000000)
|
||||
#define MCF5XXX_CACR_CFRZ (0x08000000)
|
||||
#define MCF5XXX_CACR_CINV (0x01000000)
|
||||
#define MCF5XXX_CACR_DIDI (0x00800000)
|
||||
#define MCF5XXX_CACR_DISD (0x00400000)
|
||||
#define MCF5XXX_CACR_INVI (0x00200000)
|
||||
#define MCF5XXX_CACR_INVD (0x00100000)
|
||||
#define MCF5XXX_CACR_CEIB (0x00000400)
|
||||
#define MCF5XXX_CACR_DCM_WR (0x00000000)
|
||||
#define MCF5XXX_CACR_DCM_CB (0x00000100)
|
||||
#define MCF5XXX_CACR_DCM_IP (0x00000200)
|
||||
#define MCF5XXX_CACR_DCM (0x00000200)
|
||||
#define MCF5XXX_CACR_DCM_II (0x00000300)
|
||||
#define MCF5XXX_CACR_DBWE (0x00000100)
|
||||
#define MCF5XXX_CACR_DWP (0x00000020)
|
||||
#define MCF5XXX_CACR_EUST (0x00000010)
|
||||
#define MCF5XXX_CACR_CLNF_00 (0x00000000)
|
||||
#define MCF5XXX_CACR_CLNF_01 (0x00000002)
|
||||
#define MCF5XXX_CACR_CLNF_10 (0x00000004)
|
||||
#define MCF5XXX_CACR_CLNF_11 (0x00000006)
|
||||
|
||||
#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000)
|
||||
#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8)
|
||||
#define MCF5XXX_ACR_EN (0x00008000)
|
||||
#define MCF5XXX_ACR_SM_USER (0x00000000)
|
||||
#define MCF5XXX_ACR_SM_SUPER (0x00002000)
|
||||
#define MCF5XXX_ACR_SM_IGNORE (0x00006000)
|
||||
#define MCF5XXX_ACR_ENIB (0x00000080)
|
||||
#define MCF5XXX_ACR_CM (0x00000040)
|
||||
#define MCF5XXX_ACR_DCM_WR (0x00000000)
|
||||
#define MCF5XXX_ACR_DCM_CB (0x00000020)
|
||||
#define MCF5XXX_ACR_DCM_IP (0x00000040)
|
||||
#define MCF5XXX_ACR_DCM_II (0x00000060)
|
||||
#define MCF5XXX_ACR_CM (0x00000040)
|
||||
#define MCF5XXX_ACR_BWE (0x00000020)
|
||||
#define MCF5XXX_ACR_WP (0x00000004)
|
||||
|
||||
#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000)
|
||||
#define MCF5XXX_RAMBAR_PRI_00 (0x00000000)
|
||||
#define MCF5XXX_RAMBAR_PRI_01 (0x00004000)
|
||||
#define MCF5XXX_RAMBAR_PRI_10 (0x00008000)
|
||||
#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000)
|
||||
#define MCF5XXX_RAMBAR_WP (0x00000100)
|
||||
#define MCF5XXX_RAMBAR_CI (0x00000020)
|
||||
#define MCF5XXX_RAMBAR_SC (0x00000010)
|
||||
#define MCF5XXX_RAMBAR_SD (0x00000008)
|
||||
#define MCF5XXX_RAMBAR_UC (0x00000004)
|
||||
#define MCF5XXX_RAMBAR_UD (0x00000002)
|
||||
#define MCF5XXX_RAMBAR_V (0x00000001)
|
||||
|
||||
/***********************************************************************/
|
||||
/*
|
||||
* The ColdFire family of processors has a simplified exception stack
|
||||
* frame that looks like the following:
|
||||
*
|
||||
* 3322222222221111 111111
|
||||
* 1098765432109876 5432109876543210
|
||||
* 8 +----------------+----------------+
|
||||
* | Program Counter |
|
||||
* 4 +----------------+----------------+
|
||||
* |FS/Fmt/Vector/FS| SR |
|
||||
* SP --> 0 +----------------+----------------+
|
||||
*
|
||||
* The stack self-aligns to a 4-byte boundary at an exception, with
|
||||
* the FS/Fmt/Vector/FS field indicating the size of the adjustment
|
||||
* (SP += 0,1,2,3 bytes).
|
||||
*/
|
||||
|
||||
#define MCF5XXX_RD_SF_FORMAT(PTR) \
|
||||
((*((uint16 *)(PTR)) >> 12) & 0x00FF)
|
||||
|
||||
#define MCF5XXX_RD_SF_VECTOR(PTR) \
|
||||
((*((uint16 *)(PTR)) >> 2) & 0x00FF)
|
||||
|
||||
#define MCF5XXX_RD_SF_FS(PTR) \
|
||||
( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) )
|
||||
|
||||
#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1)
|
||||
#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1)
|
||||
|
||||
/********************************************************************/
|
||||
/*
|
||||
* Functions provided by mcf5xxx.s
|
||||
*/
|
||||
|
||||
int asm_set_ipl (uint32);
|
||||
void mcf5xxx_wr_cacr (uint32);
|
||||
void mcf5xxx_wr_acr0 (uint32);
|
||||
void mcf5xxx_wr_acr1 (uint32);
|
||||
void mcf5xxx_wr_acr2 (uint32);
|
||||
void mcf5xxx_wr_acr3 (uint32);
|
||||
void mcf5xxx_wr_other_a7 (uint32);
|
||||
void mcf5xxx_wr_other_sp (uint32);
|
||||
void mcf5xxx_wr_vbr (uint32);
|
||||
void mcf5xxx_wr_macsr (uint32);
|
||||
void mcf5xxx_wr_mask (uint32);
|
||||
void mcf5xxx_wr_acc0 (uint32);
|
||||
void mcf5xxx_wr_accext01 (uint32);
|
||||
void mcf5xxx_wr_accext23 (uint32);
|
||||
void mcf5xxx_wr_acc1 (uint32);
|
||||
void mcf5xxx_wr_acc2 (uint32);
|
||||
void mcf5xxx_wr_acc3 (uint32);
|
||||
void mcf5xxx_wr_sr (uint32);
|
||||
void mcf5xxx_wr_rambar0 (uint32);
|
||||
void mcf5xxx_wr_rambar1 (uint32);
|
||||
void mcf5xxx_wr_mbar (uint32);
|
||||
void mcf5xxx_wr_mbar0 (uint32);
|
||||
void mcf5xxx_wr_mbar1 (uint32);
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* _CPU_MCF5XXX_H */
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue