mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-09-01 11:53:53 -04:00
Update to V4.3.0 as described in http://www.FreeRTOS.org/History.txt
This commit is contained in:
Richard Barry
parent
5a3272cdca
commit
014d7f5b8f
77 changed files with 4275 additions and 842 deletions
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@ -1,5 +1,5 @@
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/*
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FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.
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FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.
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||||
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||||
This file is part of the FreeRTOS.org distribution.
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@ -1,4 +1,4 @@
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# FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.
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# FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.
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#
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# This file is part of the FreeRTOS.org distribution.
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#
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@ -1,5 +1,5 @@
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/*
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FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.
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FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.
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||||
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This file is part of the FreeRTOS.org distribution.
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||||
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@ -1,121 +1,121 @@
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//*-----------------------------------------------------------------------------
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//* ATMEL Microcontroller Software Support - ROUSSET -
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//*-----------------------------------------------------------------------------
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//* The software is delivered "AS IS" without warranty or condition of any
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||||
//* kind, either express, implied or statutory. This includes without
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//* limitation any warranty or condition with respect to merchantability or
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||||
//* fitness for any particular purpose, or against the infringements of
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//* intellectual property rights of others.
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||||
//*-----------------------------------------------------------------------------
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||||
//* File Name : ebi.h
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//* Object : External Bus Interface Definition File
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//* Translator : ARM Software Development Toolkit V2.11a
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||||
//*
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//* 1.0 03/11/97 JCZ : Creation
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//* 2.0 21/10/98 JCZ : Clean up
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//*-----------------------------------------------------------------------------
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#ifndef ebi_h
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#define ebi_h
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/*----------------------------------------*/
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/* Memory Controller Interface Definition */
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/*----------------------------------------*/
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typedef struct
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{
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at91_reg EBI_CSR[8] ; /* Chip Select Register */
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at91_reg EBI_RCR ; /* Remap Control Register */
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at91_reg EBI_MCR ; /* Memory Control Register */
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} StructEBI ;
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/*-----------------------*/
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/* Chip Select Registers */
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/*-----------------------*/
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/* Data Bus Width */
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#define DataBus16 (1<<0)
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#define DataBus8 (2<<0)
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#define DBW (3<<0)
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/* Number of Wait States */
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#define B_NWS 2
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#define WaitState1 (0<<B_NWS)
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#define WaitState2 (1<<B_NWS)
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#define WaitState3 (2<<B_NWS)
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#define WaitState4 (3<<B_NWS)
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#define WaitState5 (4<<B_NWS)
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#define WaitState6 (5<<B_NWS)
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#define WaitState7 (6<<B_NWS)
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#define WaitState8 (7<<B_NWS)
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#define NWS (7<<B_NWS)
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/* Wait State Enable */
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#define WaitStateDisable (0<<5)
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#define WaitStateEnable (1<<5)
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#define WSE (1<<5)
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/* Page size */
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#define PageSize1M (0<<7)
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#define PageSize4M (1<<7)
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#define PageSize16M (2<<7)
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#define PageSize64M (3<<7)
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#define PAGES (3<<7)
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/* Number of Data Float Output Time Clock Cycle */
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#define B_TDF 9
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#define tDF_0cycle (0<<B_TDF)
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#define tDF_1cycle (1<<B_TDF)
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#define tDF_2cycle (2<<B_TDF)
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#define tDF_3cycle (3<<B_TDF)
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#define tDF_4cycle (4<<B_TDF)
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#define tDF_5cycle (5<<B_TDF)
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#define tDF_6cycle (6<<B_TDF)
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#define tDF_7cycle (7<<B_TDF)
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#define TDF (7<<B_TDF)
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/* Byte Access Type */
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#define ByteWriteAccessType (0<<12)
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#define ByteSelectAccessType (1<<12)
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#define BAT 1<<12)
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/* Chip Select Enable */
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#define CSEnable (1<<13)
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#define CSDisable (0<<13)
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#define CSE (1<<13)
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#define BA ((u_int)(0xFFF)<<20)
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/*-------------------------*/
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/* Memory Control Register */
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/*-------------------------*/
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/* Address Line Enable */
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#define ALE (7<<0)
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#define BankSize16M (0<<0)
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#define BankSize8M (4<<0)
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#define BankSize4M (5<<0)
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#define BankSize2M (6<<0)
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#define BankSize1M (7<<0)
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/* Data Read Protocol */
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#define StandardReadProtocol (0<<4)
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#define EarlyReadProtocol (1<<4)
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#define DRP (1<<4)
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/*------------------------*/
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/* Remap Control Register */
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/*------------------------*/
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#define RCB (1<<0)
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/*--------------------------------*/
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/* Device Dependancies Definition */
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/*--------------------------------*/
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#ifdef AT91M40400
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/* External Bus Interface User Interface BAse Address */
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#define EBI_BASE ((StructEBI *) 0xFFE00000)
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#endif
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#endif /* ebi_h */
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//*-----------------------------------------------------------------------------
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//* ATMEL Microcontroller Software Support - ROUSSET -
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//*-----------------------------------------------------------------------------
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//* The software is delivered "AS IS" without warranty or condition of any
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||||
//* kind, either express, implied or statutory. This includes without
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//* limitation any warranty or condition with respect to merchantability or
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//* fitness for any particular purpose, or against the infringements of
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//* intellectual property rights of others.
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//*-----------------------------------------------------------------------------
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//* File Name : ebi.h
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//* Object : External Bus Interface Definition File
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//* Translator : ARM Software Development Toolkit V2.11a
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//*
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//* 1.0 03/11/97 JCZ : Creation
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//* 2.0 21/10/98 JCZ : Clean up
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//*-----------------------------------------------------------------------------
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#ifndef ebi_h
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#define ebi_h
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/*----------------------------------------*/
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/* Memory Controller Interface Definition */
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/*----------------------------------------*/
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typedef struct
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{
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at91_reg EBI_CSR[8] ; /* Chip Select Register */
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at91_reg EBI_RCR ; /* Remap Control Register */
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at91_reg EBI_MCR ; /* Memory Control Register */
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} StructEBI ;
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/*-----------------------*/
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/* Chip Select Registers */
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/*-----------------------*/
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/* Data Bus Width */
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#define DataBus16 (1<<0)
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#define DataBus8 (2<<0)
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#define DBW (3<<0)
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/* Number of Wait States */
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#define B_NWS 2
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#define WaitState1 (0<<B_NWS)
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#define WaitState2 (1<<B_NWS)
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#define WaitState3 (2<<B_NWS)
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#define WaitState4 (3<<B_NWS)
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#define WaitState5 (4<<B_NWS)
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#define WaitState6 (5<<B_NWS)
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#define WaitState7 (6<<B_NWS)
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#define WaitState8 (7<<B_NWS)
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#define NWS (7<<B_NWS)
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/* Wait State Enable */
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#define WaitStateDisable (0<<5)
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#define WaitStateEnable (1<<5)
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#define WSE (1<<5)
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/* Page size */
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#define PageSize1M (0<<7)
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#define PageSize4M (1<<7)
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#define PageSize16M (2<<7)
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#define PageSize64M (3<<7)
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#define PAGES (3<<7)
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/* Number of Data Float Output Time Clock Cycle */
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#define B_TDF 9
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#define tDF_0cycle (0<<B_TDF)
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#define tDF_1cycle (1<<B_TDF)
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#define tDF_2cycle (2<<B_TDF)
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#define tDF_3cycle (3<<B_TDF)
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#define tDF_4cycle (4<<B_TDF)
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#define tDF_5cycle (5<<B_TDF)
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#define tDF_6cycle (6<<B_TDF)
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#define tDF_7cycle (7<<B_TDF)
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#define TDF (7<<B_TDF)
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/* Byte Access Type */
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#define ByteWriteAccessType (0<<12)
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#define ByteSelectAccessType (1<<12)
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#define BAT 1<<12)
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/* Chip Select Enable */
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#define CSEnable (1<<13)
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#define CSDisable (0<<13)
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#define CSE (1<<13)
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#define BA ((u_int)(0xFFF)<<20)
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/*-------------------------*/
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/* Memory Control Register */
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/*-------------------------*/
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/* Address Line Enable */
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#define ALE (7<<0)
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#define BankSize16M (0<<0)
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#define BankSize8M (4<<0)
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#define BankSize4M (5<<0)
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#define BankSize2M (6<<0)
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#define BankSize1M (7<<0)
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/* Data Read Protocol */
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#define StandardReadProtocol (0<<4)
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#define EarlyReadProtocol (1<<4)
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#define DRP (1<<4)
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/*------------------------*/
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/* Remap Control Register */
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/*------------------------*/
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#define RCB (1<<0)
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/*--------------------------------*/
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/* Device Dependancies Definition */
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/*--------------------------------*/
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#ifdef AT91M40400
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/* External Bus Interface User Interface BAse Address */
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#define EBI_BASE ((StructEBI *) 0xFFE00000)
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#endif
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#endif /* ebi_h */
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@ -1,5 +1,5 @@
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/*
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FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.
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FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.
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This file is part of the FreeRTOS.org distribution.
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|
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@ -1,149 +1,149 @@
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//*---------------------------------------------------------------------------
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//* ATMEL Microcontroller Software Support - ROUSSET -
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//*---------------------------------------------------------------------------
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||||
//* The software is delivered "AS IS" without warranty or condition of any
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||||
//* kind, either express, implied or statutory. This includes without
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||||
//* limitation any warranty or condition with respect to merchantability or
|
||||
//* fitness for any particular purpose, or against the infringements of
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//* intellectual property rights of others.
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//*-----------------------------------------------------------------------------
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//* File Name : pio.h
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//* Object : Parallel I/O Definition File
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//* Translator : ARM Software Development Toolkit V2.11a
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//*
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//* 1.0 20/10/97 JCZ : Creation
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//* 2.0 21/10/98 JCZ : Clean up
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//*---------------------------------------------------------------------------
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#ifndef pio_h
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#define pio_h
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/*---------------------------------------------*/
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/* Parallel I/O Interface Structure Definition */
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/*---------------------------------------------*/
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typedef struct
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{
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at91_reg PIO_PER ; /* PIO Enable Register */
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at91_reg PIO_PDR ; /* PIO Disable Register */
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at91_reg PIO_PSR ; /* PIO Status Register */
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at91_reg Reserved0 ;
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at91_reg PIO_OER ; /* Output Enable Register */
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at91_reg PIO_ODR ; /* Output Disable Register */
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at91_reg PIO_OSR ; /* Output Status Register */
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at91_reg Reserved1 ;
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at91_reg PIO_IFER ; /* Input Filter Enable Register */
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at91_reg PIO_IFDR ; /* Input Filter Disable Register */
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at91_reg PIO_IFSR ; /* Input Filter Status Register */
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at91_reg Reserved2 ;
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at91_reg PIO_SODR ; /* Set Output Data Register */
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at91_reg PIO_CODR ; /* Clear Output Data Register */
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at91_reg PIO_ODSR ; /* Output Data Status Register */
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at91_reg PIO_PDSR ; /* Pin Data Status Register */
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at91_reg PIO_IER ; /* Interrupt Enable Register */
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at91_reg PIO_IDR ; /* Interrupt Disable Register */
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at91_reg PIO_IMR ; /* Interrupt Mask Register */
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at91_reg PIO_ISR ; /* Interrupt Status Register */
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} StructPIO ;
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/*-----------------------------*/
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/* PIO Handler type definition */
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/*-----------------------------*/
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//typedef void (*TypePIOHandler) ( StructPIO *pio_pt, u_int pio_mask ) ;
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/*--------------------------------*/
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/* Device Dependancies Definition */
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/*--------------------------------*/
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/* Number of PIO Controller */
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#define NB_PIO_CTRL 1
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/* Base Address */
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#define PIO_BASE ((StructPIO *) 0xFFFF0000 )
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/* Number of PIO Lines */
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#define NB_PIO 32
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/* Parallel I/O Bits Definition */
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#define P0 (1<<0)
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#define P1 (1<<1)
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#define P2 (1<<2)
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#define P3 (1<<3)
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#define P4 (1<<4)
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#define P5 (1<<5)
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#define P6 (1<<6)
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#define P7 (1<<7)
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#define P8 (1<<8)
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#define P9 (1<<9)
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#define P10 (1<<10)
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#define P11 (1<<11)
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#define P12 (1<<12)
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#define P13 (1<<13)
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#define P14 (1<<14)
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#define P15 (1<<15)
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#define P16 (1<<16)
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#define P17 (1<<17)
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#define P18 (1<<18)
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#define P19 (1<<19)
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#define P20 (1<<20)
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#define P21 (1<<21)
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#define P22 (1<<22)
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#define P23 (1<<23)
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#define P24 (1<<24)
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#define P25 (1<<25)
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#define P26 (1<<26)
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#define P27 (1<<27)
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#define P28 (1<<28)
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#define P29 (1<<29)
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#define P30 (1<<30)
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#define P31 (1<<31)
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/* PIO Multiplexing Definition */
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/* There is only one PIO Controller */
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#define PIO_CTRL 0
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#define PIO_TC0 PIO_CTRL
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#define TCLK0 P0
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#define TIOA0 P1
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#define TIOB0 P2
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#define PIN_TC0 (TIOA0|TIOB0|TCLK0)
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#define PIO_TC1 PIO_CTRL
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#define TCLK1 P3
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#define TIOA1 P4
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#define TIOB1 P5
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#define PIN_TC1 (TIOA1|TIOB1|TCLK1)
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#define PIO_TC2 PIO_CTRL
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#define TCLK2 P6
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#define TIOA2 P7
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#define TIOB2 P8
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#define PIN_TC2 (TIOA2|TIOB2|TCLK2)
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#define PIO_EXT_IRQ PIO_CTRL
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#define PIN_IRQ0 P9
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#define PIN_IRQ1 P10
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#define PIN_IRQ2 P11
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#define PIN_FIQ P12
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#define PIO_USART0 PIO_CTRL
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#define SCK0 P13
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#define TXD0 P14
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#define RXD0 P15
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#define PIN_USART0 (SCK0|TXD0|RXD0)
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#define PIO_USART1 PIO_CTRL
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#define SCK1 P20
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#define TXD1 P21
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#define RXD1 P22
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#define PIN_USART1 (SCK1|TXD1|RXD1)
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#define MCKO P25
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#define CS2 P26
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#define CS3 P27
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#define CS4 P31
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#define CS5 P30
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#define CS6 P29
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#define CS7 P28
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#endif /* pio_h */
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||||
//*---------------------------------------------------------------------------
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||||
//* ATMEL Microcontroller Software Support - ROUSSET -
|
||||
//*---------------------------------------------------------------------------
|
||||
//* The software is delivered "AS IS" without warranty or condition of any
|
||||
//* kind, either express, implied or statutory. This includes without
|
||||
//* limitation any warranty or condition with respect to merchantability or
|
||||
//* fitness for any particular purpose, or against the infringements of
|
||||
//* intellectual property rights of others.
|
||||
//*-----------------------------------------------------------------------------
|
||||
//* File Name : pio.h
|
||||
//* Object : Parallel I/O Definition File
|
||||
//* Translator : ARM Software Development Toolkit V2.11a
|
||||
//*
|
||||
//* 1.0 20/10/97 JCZ : Creation
|
||||
//* 2.0 21/10/98 JCZ : Clean up
|
||||
//*---------------------------------------------------------------------------
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||||
|
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#ifndef pio_h
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#define pio_h
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|
||||
/*---------------------------------------------*/
|
||||
/* Parallel I/O Interface Structure Definition */
|
||||
/*---------------------------------------------*/
|
||||
|
||||
typedef struct
|
||||
{
|
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at91_reg PIO_PER ; /* PIO Enable Register */
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at91_reg PIO_PDR ; /* PIO Disable Register */
|
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at91_reg PIO_PSR ; /* PIO Status Register */
|
||||
at91_reg Reserved0 ;
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||||
at91_reg PIO_OER ; /* Output Enable Register */
|
||||
at91_reg PIO_ODR ; /* Output Disable Register */
|
||||
at91_reg PIO_OSR ; /* Output Status Register */
|
||||
at91_reg Reserved1 ;
|
||||
at91_reg PIO_IFER ; /* Input Filter Enable Register */
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||||
at91_reg PIO_IFDR ; /* Input Filter Disable Register */
|
||||
at91_reg PIO_IFSR ; /* Input Filter Status Register */
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||||
at91_reg Reserved2 ;
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||||
at91_reg PIO_SODR ; /* Set Output Data Register */
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||||
at91_reg PIO_CODR ; /* Clear Output Data Register */
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||||
at91_reg PIO_ODSR ; /* Output Data Status Register */
|
||||
at91_reg PIO_PDSR ; /* Pin Data Status Register */
|
||||
at91_reg PIO_IER ; /* Interrupt Enable Register */
|
||||
at91_reg PIO_IDR ; /* Interrupt Disable Register */
|
||||
at91_reg PIO_IMR ; /* Interrupt Mask Register */
|
||||
at91_reg PIO_ISR ; /* Interrupt Status Register */
|
||||
} StructPIO ;
|
||||
|
||||
/*-----------------------------*/
|
||||
/* PIO Handler type definition */
|
||||
/*-----------------------------*/
|
||||
|
||||
//typedef void (*TypePIOHandler) ( StructPIO *pio_pt, u_int pio_mask ) ;
|
||||
|
||||
/*--------------------------------*/
|
||||
/* Device Dependancies Definition */
|
||||
/*--------------------------------*/
|
||||
|
||||
/* Number of PIO Controller */
|
||||
#define NB_PIO_CTRL 1
|
||||
/* Base Address */
|
||||
#define PIO_BASE ((StructPIO *) 0xFFFF0000 )
|
||||
/* Number of PIO Lines */
|
||||
#define NB_PIO 32
|
||||
|
||||
/* Parallel I/O Bits Definition */
|
||||
#define P0 (1<<0)
|
||||
#define P1 (1<<1)
|
||||
#define P2 (1<<2)
|
||||
#define P3 (1<<3)
|
||||
#define P4 (1<<4)
|
||||
#define P5 (1<<5)
|
||||
#define P6 (1<<6)
|
||||
#define P7 (1<<7)
|
||||
#define P8 (1<<8)
|
||||
#define P9 (1<<9)
|
||||
#define P10 (1<<10)
|
||||
#define P11 (1<<11)
|
||||
#define P12 (1<<12)
|
||||
#define P13 (1<<13)
|
||||
#define P14 (1<<14)
|
||||
#define P15 (1<<15)
|
||||
#define P16 (1<<16)
|
||||
#define P17 (1<<17)
|
||||
#define P18 (1<<18)
|
||||
#define P19 (1<<19)
|
||||
#define P20 (1<<20)
|
||||
#define P21 (1<<21)
|
||||
#define P22 (1<<22)
|
||||
#define P23 (1<<23)
|
||||
#define P24 (1<<24)
|
||||
#define P25 (1<<25)
|
||||
#define P26 (1<<26)
|
||||
#define P27 (1<<27)
|
||||
#define P28 (1<<28)
|
||||
#define P29 (1<<29)
|
||||
#define P30 (1<<30)
|
||||
#define P31 (1<<31)
|
||||
|
||||
/* PIO Multiplexing Definition */
|
||||
|
||||
/* There is only one PIO Controller */
|
||||
#define PIO_CTRL 0
|
||||
|
||||
#define PIO_TC0 PIO_CTRL
|
||||
#define TCLK0 P0
|
||||
#define TIOA0 P1
|
||||
#define TIOB0 P2
|
||||
#define PIN_TC0 (TIOA0|TIOB0|TCLK0)
|
||||
|
||||
#define PIO_TC1 PIO_CTRL
|
||||
#define TCLK1 P3
|
||||
#define TIOA1 P4
|
||||
#define TIOB1 P5
|
||||
#define PIN_TC1 (TIOA1|TIOB1|TCLK1)
|
||||
|
||||
#define PIO_TC2 PIO_CTRL
|
||||
#define TCLK2 P6
|
||||
#define TIOA2 P7
|
||||
#define TIOB2 P8
|
||||
#define PIN_TC2 (TIOA2|TIOB2|TCLK2)
|
||||
|
||||
#define PIO_EXT_IRQ PIO_CTRL
|
||||
#define PIN_IRQ0 P9
|
||||
#define PIN_IRQ1 P10
|
||||
#define PIN_IRQ2 P11
|
||||
#define PIN_FIQ P12
|
||||
|
||||
#define PIO_USART0 PIO_CTRL
|
||||
#define SCK0 P13
|
||||
#define TXD0 P14
|
||||
#define RXD0 P15
|
||||
#define PIN_USART0 (SCK0|TXD0|RXD0)
|
||||
|
||||
#define PIO_USART1 PIO_CTRL
|
||||
#define SCK1 P20
|
||||
#define TXD1 P21
|
||||
#define RXD1 P22
|
||||
#define PIN_USART1 (SCK1|TXD1|RXD1)
|
||||
|
||||
#define MCKO P25
|
||||
#define CS2 P26
|
||||
#define CS3 P27
|
||||
#define CS4 P31
|
||||
#define CS5 P30
|
||||
#define CS6 P29
|
||||
#define CS7 P28
|
||||
|
||||
#endif /* pio_h */
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.
|
||||
FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.
|
||||
FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS.org distribution.
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue