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Add demo project for Polarfire board (#679)

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Add the demo project for PolarFire SoC

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
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Gaurav-Aggarwal-AWS 2021-09-02 14:02:46 -07:00 • committed by GitHub
parent a40172758a
commit 008affa7bf
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136 changed files with 61497 additions and 2 deletions
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<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
</storageModule>
</cproject>

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FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/.gitignore vendored Normal file
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/LIM-Debug/
.settings/
/eNVM-Release/

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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>FreeRTOSDemo</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
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<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
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<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources>
<link>
<name>FreeRTOS</name>
<type>2</type>
<locationURI>FREERTOS_ROOT/Source</locationURI>
</link>
<link>
<name>full_demo/Demo_Tasks</name>
<type>2</type>
<locationURI>FREERTOS_ROOT/Demo/Common</locationURI>
</link>
</linkedResources>
<filteredResources>
<filter>
<id>1629933517646</id>
<name>FreeRTOS</name>
<type>5</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-*.c</arguments>
</matcher>
</filter>
<filter>
<id>1629934227060</id>
<name>FreeRTOS/portable</name>
<type>9</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-MemMang</arguments>
</matcher>
</filter>
<filter>
<id>1629934227063</id>
<name>FreeRTOS/portable</name>
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<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-GCC</arguments>
</matcher>
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<filter>
<id>1629933822134</id>
<name>full_demo/Demo_Tasks</name>
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<arguments>1.0-name-matches-false-false-include</arguments>
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<name>full_demo/Demo_Tasks</name>
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<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-Minimal</arguments>
</matcher>
</filter>
<filter>
<id>1629934267996</id>
<name>FreeRTOS/portable/GCC</name>
<type>9</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-RISC-V</arguments>
</matcher>
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<name>FreeRTOS/portable/MemMang</name>
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<type>6</type>
<matcher>
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<arguments>1.0-name-matches-false-false-comtest_strings.c</arguments>
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<type>6</type>
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<arguments>1.0-name-matches-false-false-crhook.c</arguments>
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<arguments>1.0-name-matches-false-false-flash_timer.c</arguments>
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</matcher>
</filter>
<filter>
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<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-RISCV_MTIME_CLINT_no_extensions</arguments>
</matcher>
</filter>
</filteredResources>
<variableList>
<variable>
<name>FREERTOS_ROOT</name>
<value>$%7BPARENT-2-PROJECT_LOC%7D</value>
</variable>
</variableList>
</projectDescription>

138
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/FreeRTOSConfig.h Normal file
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/*
* FreeRTOS V202107.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/* PolarFire HAL includes. */
#include "mpfs_hal/mss_hal.h"
#include "drivers/mss/mss_mmuart/mss_uart.h"
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
#define CLINT_CTRL_ADDR ( 0x02000000UL )
#define configMTIME_BASE_ADDRESS ( CLINT_CTRL_ADDR + 0xBFF8UL )
#define configMTIMECMP_BASE_ADDRESS ( CLINT_CTRL_ADDR + 0x4000UL )
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 1
#define configCPU_CLOCK_HZ ( 32768 )
#define configTICK_RATE_HZ ( ( TickType_t ) 1000 )
#define configMAX_PRIORITIES ( 7 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 256 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 90 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 0
#define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 8
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_MALLOC_FAILED_HOOK 1
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_COUNTING_SEMAPHORES 1
#define configGENERATE_RUN_TIME_STATS 0
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#define configUSE_QUEUE_SETS 1
#define configTASK_NOTIFICATION_ARRAY_ENTRIES 3
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
#define configTIMER_QUEUE_LENGTH 8
#define configTIMER_TASK_STACK_DEPTH ( 160 )
/* Task priorities. Allow these to be overridden. */
#ifndef uartPRIMARY_PRIORITY
#define uartPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 )
#endif
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_eTaskGetState 1
#define INCLUDE_xTimerPendFunctionCall 1
#define INCLUDE_xTaskAbortDelay 1
#define INCLUDE_xTaskGetHandle 1
#define INCLUDE_xSemaphoreGetMutexHolder 1
/* Normal assert() semantics without relying on the provision of an assert.h
header file. */
void vAssertCalled( void );
#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled()
/* Map to the platform write function. */
#define configPRINT_STRING( pcString ) MSS_UART_polled_tx_string( &( g_mss_uart0_lo ), pcString )
/* Test configurations. */
#define configSTART_TASK_NOTIFY_TESTS 1
#define configSTART_TASK_NOTIFY_ARRAY_TESTS 1
#define configSTART_BLOCKING_QUEUE_TESTS 1
#define configSTART_SEMAPHORE_TESTS 1
#define configSTART_POLLED_QUEUE_TESTS 1
#define configSTART_INTEGER_MATH_TESTS 1
#define configSTART_GENERIC_QUEUE_TESTS 1
#define configSTART_PEEK_QUEUE_TESTS 1
/* Cannot run math tests as E51 does not have floating point unit. */
#define configSTART_MATH_TESTS 0
#define configSTART_RECURSIVE_MUTEX_TESTS 1
#define configSTART_COUNTING_SEMAPHORE_TESTS 1
#define configSTART_QUEUE_SET_TESTS 1
#define configSTART_QUEUE_OVERWRITE_TESTS 0
#define configSTART_EVENT_GROUP_TESTS 0
#define configSTART_INTERRUPT_SEMAPHORE_TESTS 0
#define configSTART_QUEUE_SET_POLLING_TESTS 0
#define configSTART_BLOCK_TIME_TESTS 0
#define configSTART_ABORT_DELAY_TESTS 0
#define configSTART_MESSAGE_BUFFER_TESTS 0
#define configSTART_STREAM_BUFFER_TESTS 0
#define configSTART_STREAM_BUFFER_INTERRUPT_TESTS 0
#define configSTART_TIMER_TESTS 0
#define configSTART_REGISTER_TESTS 0
#define configSTART_DELETE_SELF_TESTS 0
#endif /* FREERTOS_CONFIG_H */

61
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/FreeRTOSDemo_Debug.launch Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#13;&#10;set $target_riscv=1&#13;&#10;set architecture riscv:rv64&#13;&#10;file ${config_name:FreeRTOSDemo}/FreeRTOSDemo.elf"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/>
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="--command &quot;set DEVICE MPFS&quot;&#13;&#10;--file board/microsemi-riscv.cfg"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value="thread apply all set $pc=_start"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="init"/>
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="false"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="e51"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${config_name:FreeRTOSDemo}/FreeRTOSDemo.elf"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="FreeRTOSDemo"/>
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/FreeRTOSDemo"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#10;"/>
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
</launchConfiguration>

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## UART configuration
On connecting Icicle kit J11 to the host PC, you should see four COM port
interfaces connected. This example project uses MMUART0. To use this
project the host PC must connect to the COM port interface0 using a terminal
emulator such as HyperTerminal or PuTTY configured as follows:
- 115200 baud.
- 8 data bits.
- 1 stop bit.
- no parity.
- no flow control.
## Target hardware
This example project is targeted at the Icicle kit.
Details are available at the following link: https://www.microsemi.com/existing-parts/parts/152514
## SoftConsole details
SoftConsole version used to test this project is available at link below:
https://www.microsemi.com/product-directory/design-tools/4879-softconsole#downloads

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/*
* FreeRTOS V202107.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/******************************************************************************
* NOTE 1: This project provides two demo applications. A simple blinky
* style project, and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
* between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
* in main.c. This file implements the simply blinky style version.
*
* NOTE 2: This file only contains the source code that is specific to the
* blinky demo. Generic functions, such FreeRTOS hook functions, and functions
* required to configure the hardware are defined in main.c.
******************************************************************************
*
* main_blinky() creates one queue, and two tasks. It then starts the
* scheduler.
*
* The Queue Send Task:
* The queue send task is implemented by the prvQueueSendTask() function in
* this file. prvQueueSendTask() sits in a loop that causes it to repeatedly
* block for 1000 milliseconds, before sending the value 100 to the queue that
* was created within main_blinky(). Once the value is sent, the task loops
* back around to block for another 1000 milliseconds...and so on.
*
* The Queue Receive Task:
* The queue receive task is implemented by the prvQueueReceiveTask() function
* in this file. prvQueueReceiveTask() sits in a loop where it repeatedly
* blocks on attempts to read data from the queue that was created within
* main_blinky(). When data is received, the task checks the value of the
* data, and if the value equals the expected 100, toggles an LED. The 'block
* time' parameter passed to the queue receive function specifies that the task
* should be held in the Blocked state indefinitely to wait for data to be
* available on the queue. The queue receive task will only leave the Blocked
* state when the queue send task writes to the queue. As the queue send task
* writes to the queue every 1000 milliseconds, the queue receive task leaves
* the Blocked state every 1000 milliseconds, and therefore toggles the LED
* every 200 milliseconds.
*/
/* Standard includes. */
#include <stdio.h>
#include <string.h>
#include <unistd.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
/* Priorities used by the tasks. */
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* The rate at which data is sent to the queue. The 3000ms value is converted
to ticks using the pdMS_TO_TICKS() macro. */
#define mainQUEUE_SEND_FREQUENCY_MS pdMS_TO_TICKS( 3000 )
/* The maximum number items the queue can hold. The priority of the receiving
task is above the priority of the sending task, so the receiving task will
preempt the sending task and remove the queue items each time the sending task
writes to the queue. Therefore the queue will never have more than one item in
it at any time, and even with a queue length of 1, the sending task will never
find the queue full. */
#define mainQUEUE_LENGTH ( 1 )
/*-----------------------------------------------------------*/
/*
* Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in
* main.c.
*/
void main_blinky( void );
/*
* The tasks as described in the comments at the top of this file.
*/
static void prvQueueReceiveTask( void *pvParameters );
static void prvQueueSendTask( void *pvParameters );
/*-----------------------------------------------------------*/
/* The queue used by both tasks. */
static QueueHandle_t xQueue = NULL;
/*-----------------------------------------------------------*/
void main_blinky( void )
{
/* Create the queue. */
xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
if( xQueue != NULL )
{
/* Start the two tasks as described in the comments at the top of this
file. */
xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
"Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */
NULL, /* The parameter passed to the task - not used in this case. */
mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
NULL ); /* The task handle is not required, so NULL is passed. */
xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
/* Start the tasks and timer running. */
vTaskStartScheduler();
}
/* If all is well, the scheduler will now be running, and the following
line will never be reached. If the following line does execute, then
there was insufficient FreeRTOS heap memory available for the Idle and/or
timer tasks to be created. See the memory management section on the
FreeRTOS web site for more details on the FreeRTOS heap
http://www.freertos.org/a00111.html. */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvQueueSendTask( void *pvParameters )
{
TickType_t xNextWakeTime;
const unsigned long ulValueToSend = 100UL;
BaseType_t xReturned;
/* Remove compiler warning about unused parameter. */
( void ) pvParameters;
/* Initialise xNextWakeTime - this only needs to be done once. */
xNextWakeTime = xTaskGetTickCount();
for( ;; )
{
/* Place this task in the blocked state until it is time to run again. */
vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
/* Send to the queue - causing the queue receive task to unblock and
toggle the LED. 0 is used as the block time so the sending operation
will not block - it shouldn't need to block as the queue should always
be empty at this point in the code. */
xReturned = xQueueSend( xQueue, &ulValueToSend, 0U );
configASSERT( xReturned == pdPASS );
}
}
/*-----------------------------------------------------------*/
static void prvQueueReceiveTask( void *pvParameters )
{
unsigned long ulReceivedValue;
const unsigned long ulExpectedValue = 100UL;
extern void vToggleLED( void );
TickType_t tickCount;
/* Remove compiler warning about unused parameter. */
( void ) pvParameters;
for( ;; )
{
/* Wait until something arrives in the queue - this task will block
indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
FreeRTOSConfig.h. */
xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
/* To get here something must have been received from the queue, but
is it the expected value? If it is, toggle the LED. */
if( ulReceivedValue == ulExpectedValue )
{
tickCount = xTaskGetTickCount();
vToggleLED();
ulReceivedValue = 0U;
}
}
}
/*-----------------------------------------------------------*/

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# Create a Test Project
## Initial Setup
1. Create a new directory in the [FreeRTOS Partner Supported Demos Repository](https://github.com/FreeRTOS/FreeRTOS-Partner-Supported-Demos/tree/main)
or [FreeRTOS Community Supported Demos Repository](https://github.com/FreeRTOS/FreeRTOS-Community-Supported-Demos/tree/main).
The suggested name for the directory is `<hardware_name>_<compiler_name>`.
2. Create a project for your hardware and tool-chain in this directory.
3. Copy all the files in the [FreeRTOS/Demo/ThirdParty/Template](https://github.com/FreeRTOS/FreeRTOS/tree/main/FreeRTOS/Demo/ThirdParty/Template)
directory to your project directory:
* `IntQueueTimer.h`
* `IntQueueTimer.c`
* `TestRunner.h`
* `TestRunner.c`
* `RegTests.h`
* `RegTests.c`
## Project Configuration
1. Compile the following additional files in your project:
* All files in the [FreeRTOS/Demo/Common/Minimal](https://github.com/FreeRTOS/FreeRTOS/tree/main/FreeRTOS/Demo/Common/Minimal) directory except
`comtest_strings.c`, `crhook.c` , `comtest.c` ,`crflash.c`,`flash.c`, `flash_timer.c` and `sp_flop.c`.
2. Add the following paths to your include search path:
* `FreeRTOS/Demo/Common/include`.
3. Call the `void vStartTests( void )` function from your `main` function after
doing all the hardware initialization. Note that this function starts the
scheduler and therefore, never returns.
```c
#include "TestRunner.h"
void main( void )
{
/* Startup and Hardware initialization. */
/* Start tests. */
vStartTests();
/* Should never reach here. */
for( ; ; );
}
```
## Set up FreeRTOSConfig.h
1. Enable tick hook by adding the following line in your `FreeRTOSConfig.h`:
```c
#define configUSE_TICK_HOOK 1
```
2. Set the task notification array size to 3 by adding the following line in
your `FreeRTOSConfig.h`:
```c
#define configTASK_NOTIFICATION_ARRAY_ENTRIES 3
```
3. Enable printing by mapping `configPRINTF` to your print function. Note that
`configPRINTF` calls are wrapped in double parentheses to support C89. If you
have a thread-safe `printf` function, the following is what should be added
in your `FreeRTOSConfig.h`:
```c
#define configPRINTF( X ) printf X
```
4. Add the following defines in your `FreeRTOSConfig.h`:
```c
#define configSTART_TASK_NOTIFY_TESTS 0
#define configSTART_TASK_NOTIFY_ARRAY_TESTS 0
#define configSTART_BLOCKING_QUEUE_TESTS 0
#define configSTART_SEMAPHORE_TESTS 0
#define configSTART_POLLED_QUEUE_TESTS 0
#define configSTART_INTEGER_MATH_TESTS 0
#define configSTART_GENERIC_QUEUE_TESTS 0
#define configSTART_PEEK_QUEUE_TESTS 0
#define configSTART_MATH_TESTS 0
#define configSTART_RECURSIVE_MUTEX_TESTS 0
#define configSTART_COUNTING_SEMAPHORE_TESTS 0
#define configSTART_QUEUE_SET_TESTS 0
#define configSTART_QUEUE_OVERWRITE_TESTS 0
#define configSTART_EVENT_GROUP_TESTS 0
#define configSTART_INTERRUPT_SEMAPHORE_TESTS 0
#define configSTART_QUEUE_SET_POLLING_TESTS 0
#define configSTART_BLOCK_TIME_TESTS 0
#define configSTART_ABORT_DELAY_TESTS 0
#define configSTART_MESSAGE_BUFFER_TESTS 0
#define configSTART_STREAM_BUFFER_TESTS 0
#define configSTART_STREAM_BUFFER_INTERRUPT_TESTS 0
#define configSTART_TIMER_TESTS 0
#define configSTART_INTERRUPT_QUEUE_TESTS 0
#define configSTART_REGISTER_TESTS 0
#define configSTART_DELETE_SELF_TESTS 0
```
## Create and Run Register Tests
1. Fill the definitions of the following functions in the `RegTests.c` file
copied in the [Initial Setup](#Initial-Setup) step:
* `prvRegisterTest1Task`
* `prvRegisterTest2Task`
* `prvRegisterTest3Task`
* `prvRegisterTest4Task`
2. Define `configSTART_REGISTER_TESTS` to `1` in your `FreeRTOSConfig.h`:
```c
#define configSTART_REGISTER_TESTS 1
```
3. Build and run the register tests. The output should look like the following:
```
No errors
No errors
No errors
No errors
```
## Setup and Run Interrupt Nesting Tests
1. If your hardware **does not** support interrupt nesting, skip this section.
2. Fill the `void vInitialiseTimerForIntQueueTest( void )` function in the
`IntQueueTimer.c` file copied in the [Initial Setup](#Initial-Setup) step to
initialize and start a hardware timer. Make sure that the timer interrupt
runs at a logical priority less than or equal to `configMAX_SYSCALL_INTERRUPT_PRIORITY`.
The following is an example for ARM MPS2 which starts TIM0 timer:
```c
void vInitialiseTimerForIntQueueTest( void )
{
/* Clear interrupt. */
CMSDK_TIMER0->INTCLEAR = ( 1ul << 0 );
/* Reload value is slightly offset from the other timer. */
CMSDK_TIMER0->RELOAD = ( configCPU_CLOCK_HZ / tmrTIMER_0_FREQUENCY ) + 1UL;
CMSDK_TIMER0->CTRL = ( ( 1ul << 3 ) | ( 1ul << 0 ) );
NVIC_SetPriority( TIMER0_IRQn, configMAX_SYSCALL_INTERRUPT_PRIORITY );
NVIC_EnableIRQ( TIMER0_IRQn );
}
```
3. Either install `void IntQueueTestTimerHandler( void )` function as the timer
interrupt handler or call it from the timer interrupt handler of the above
timer. The following is an example for ARM MPS2 which calls
`IntQueueTestTimerHandler` from the TIM0 handler:
```c
void TIMER0_Handler( void )
{
/* Clear interrupt. */
CMSDK_TIMER0->INTCLEAR = ( 1ul << 0 );
IntQueueTestTimerHandler();
}
```
4. Define `configSTART_INTERRUPT_QUEUE_TESTS` to `1` in your `FreeRTOSConfig.h`:
```c
#define configSTART_INTERRUPT_QUEUE_TESTS 1
```
5. Build and run the tests. The output should look like the following:
```
No errors
No errors
No errors
No errors
```
## Running All Tests
1. Define all the `configSTART_<Test_Name>_TESTS` macros to `1` in your
`FreeRTOSConfig.h`.
2. Build and run the tests. The output should look like the following:
```
No errors
No errors
No errors
No errors
```
3. If you cannot fit all the tests in one binary because of Flash or RAM space,
you can run tests one by one or in groups by defining
`configSTART_<Test_Name>_TESTS` macros to `0` or `1` as needed.
## Add README
Add a `README.md` file in the project directory with the following information:
* Link to the hardware page.
* How to setup tool-chain.
* How to build and run the project.
* Any other relevant information.

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/*
* FreeRTOS V202107.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
.extern ulRegisterTest1Counter
.extern ulRegisterTest2Counter
.global vRegTest1Implementation
.global vRegTest2Implementation
/*-----------------------------------------------------------*/
/*
* The register check tasks are described in the comments at the top of
* main_full.c.
*/
.align( 4 )
vRegTest1Implementation:
/* Fill the core registers with known values. */
li x5, 0x5
li x6, 0x6
li x7, 0x7
li x8, 0x8
li x9, 0x9
li x10, 0xa
li x11, 0xb
li x12, 0xc
li x13, 0xd
li x14, 0xe
li x15, 0xf
li x16, 0x10
li x17, 0x11
li x18, 0x12
li x19, 0x13
li x20, 0x14
li x21, 0x15
li x22, 0x16
li x23, 0x17
li x24, 0x18
li x25, 0x19
li x26, 0x1a
li x27, 0x1b
li x28, 0x1c
li x29, 0x1d
li x30, 0x1e
reg1_loop:
/* Check each register still contains the expected known value.
vRegTest1Implementation uses x31 as the temporary, vRegTest2Implementation
uses x5 as the temporary. */
li x31, 0x5
bne x31, x5, reg1_error_loop
li x31, 0x6
bne x31, x6, reg1_error_loop
li x31, 0x7
bne x31, x7, reg1_error_loop
li x31, 0x8
bne x31, x8, reg1_error_loop
li x31, 0x9
bne x31, x9, reg1_error_loop
li x31, 0xa
bne x31, x10, reg1_error_loop
li x31, 0xb
bne x31, x11, reg1_error_loop
li x31, 0xc
bne x31, x12, reg1_error_loop
li x31, 0xd
bne x31, x13, reg1_error_loop
li x31, 0xe
bne x31, x14, reg1_error_loop
li x31, 0xf
bne x31, x15, reg1_error_loop
li x31, 0x10
bne x31, x16, reg1_error_loop
li x31, 0x11
bne x31, x17, reg1_error_loop
li x31, 0x12
bne x31, x18, reg1_error_loop
li x31, 0x13
bne x31, x19, reg1_error_loop
li x31, 0x14
bne x31, x20, reg1_error_loop
li x31, 0x15
bne x31, x21, reg1_error_loop
li x31, 0x16
bne x31, x22, reg1_error_loop
li x31, 0x17
bne x31, x23, reg1_error_loop
li x31, 0x18
bne x31, x24, reg1_error_loop
li x31, 0x19
bne x31, x25, reg1_error_loop
li x31, 0x1a
bne x31, x26, reg1_error_loop
li x31, 0x1b
bne x31, x27, reg1_error_loop
li x31, 0x1c
bne x31, x28, reg1_error_loop
li x31, 0x1d
bne x31, x29, reg1_error_loop
li x31, 0x1e
bne x31, x30, reg1_error_loop
/* Everything passed, increment the loop counter. */
lw x31, ulRegisterTest1CounterConst
lw x30, 0(x31)
addi x30, x30, 1
sw x30, 0(x31)
/* Restore clobbered register reading for next loop. */
li x30, 0x1e
/* Yield to increase code coverage. */
ecall
/* Start again. */
jal reg1_loop
reg1_error_loop:
/* Jump here if a register contains an uxpected value. This stops the loop
counter being incremented so the check task knows an error was found. */
ebreak
jal reg1_error_loop
.align( 4 )
ulRegisterTest1CounterConst: .word ulRegisterTest1Counter
/*-----------------------------------------------------------*/
.align( 4 )
vRegTest2Implementation:
/* Fill the core registers with known values. */
li x6, 0x61
li x7, 0x71
li x8, 0x81
li x9, 0x91
li x10, 0xa1
li x11, 0xb1
li x12, 0xc1
li x13, 0xd1
li x14, 0xe1
li x15, 0xf1
li x16, 0x20
li x17, 0x21
li x18, 0x22
li x19, 0x23
li x20, 0x24
li x21, 0x25
li x22, 0x26
li x23, 0x27
li x24, 0x28
li x25, 0x29
li x26, 0x2a
li x27, 0x2b
li x28, 0x2c
li x29, 0x2d
li x30, 0x2e
li x31, 0x2f
Reg2_loop:
/* Check each register still contains the expected known value.
vRegTest2Implementation uses x5 as the temporary, vRegTest1Implementation
uses x31 as the temporary. */
li x5, 0x61
bne x5, x6, reg2_error_loop
li x5, 0x71
bne x5, x7, reg2_error_loop
li x5, 0x81
bne x5, x8, reg2_error_loop
li x5, 0x91
bne x5, x9, reg2_error_loop
li x5, 0xa1
bne x5, x10, reg2_error_loop
li x5, 0xb1
bne x5, x11, reg2_error_loop
li x5, 0xc1
bne x5, x12, reg2_error_loop
li x5, 0xd1
bne x5, x13, reg2_error_loop
li x5, 0xe1
bne x5, x14, reg2_error_loop
li x5, 0xf1
bne x5, x15, reg2_error_loop
li x5, 0x20
bne x5, x16, reg2_error_loop
li x5, 0x21
bne x5, x17, reg2_error_loop
li x5, 0x22
bne x5, x18, reg2_error_loop
li x5, 0x23
bne x5, x19, reg2_error_loop
li x5, 0x24
bne x5, x20, reg2_error_loop
li x5, 0x25
bne x5, x21, reg2_error_loop
li x5, 0x26
bne x5, x22, reg2_error_loop
li x5, 0x27
bne x5, x23, reg2_error_loop
li x5, 0x28
bne x5, x24, reg2_error_loop
li x5, 0x29
bne x5, x25, reg2_error_loop
li x5, 0x2a
bne x5, x26, reg2_error_loop
li x5, 0x2b
bne x5, x27, reg2_error_loop
li x5, 0x2c
bne x5, x28, reg2_error_loop
li x5, 0x2d
bne x5, x29, reg2_error_loop
li x5, 0x2e
bne x5, x30, reg2_error_loop
li x5, 0x2f
bne x5, x31, reg2_error_loop
/* Everything passed, increment the loop counter. */
lw x5, ulRegisterTest2CounterConst
lw x6, 0(x5)
addi x6, x6, 1
sw x6, 0(x5)
/* Restore clobbered register reading for next loop. */
li x6, 0x61
/* Start again. */
jal Reg2_loop
reg2_error_loop:
/* Jump here if a register contains an uxpected value. This stops the loop
counter being incremented so the check task knows an error was found. */
ebreak
jal reg2_error_loop
.align( 4 )
ulRegisterTest2CounterConst: .word ulRegisterTest2Counter

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/*
* FreeRTOS V202104.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
/* Interface include files. */
#include "RegTests.h"
/* Parameters that are passed into the register check tasks solely for the
* purpose of ensuring parameters are passed into tasks correctly. */
#define REG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 )
#define REG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 )
/*-----------------------------------------------------------*/
/* Tasks that implement register tests. */
static void prvRegisterTest1Task( void *pvParameters );
static void prvRegisterTest2Task( void *pvParameters );
extern void vRegTest1Implementation( void );
extern void vRegTest2Implementation( void );
/* Flag that will be latched to pdTRUE should any unexpected behaviour be
detected in any of the tasks. */
static volatile BaseType_t xErrorDetected = pdFALSE;
/* Counters that are incremented on each cycle of a test. This is used to
detect a stalled task - a test that is no longer running. */
volatile uint32_t ulRegisterTest1Counter = 0;
volatile uint32_t ulRegisterTest2Counter = 0;
/*-----------------------------------------------------------*/
static void prvRegisterTest1Task( void *pvParameters )
{
/* Although the regtest task is written in assembler, its entry point is
* written in C for convenience of checking the task parameter is being
* passed in correctly. */
if( pvParameters == REG_TEST_TASK_1_PARAMETER )
{
/* Start the part of the test that is written in assembler. */
vRegTest1Implementation();
}
/* The following line will only execute if the task parameter is found to
* be incorrect. The check task will detect that the regtest loop counter
* is not being incremented and flag an error. */
vTaskDelete( NULL );
}
/*-----------------------------------------------------------*/
static void prvRegisterTest2Task( void *pvParameters )
{
/* Although the regtest task is written in assembler, its entry point is
* written in C for convenience of checking the task parameter is being
* passed in correctly. */
if( pvParameters == REG_TEST_TASK_2_PARAMETER )
{
/* Start the part of the test that is written in assembler. */
vRegTest2Implementation();
}
/* The following line will only execute if the task parameter is found to
* be incorrect. The check task will detect that the regtest loop counter
* is not being incremented and flag an error. */
vTaskDelete( NULL );
}
/*-----------------------------------------------------------*/
void vStartRegisterTasks( UBaseType_t uxPriority )
{
BaseType_t ret;
ret = xTaskCreate( prvRegisterTest1Task,
"RegTest1",
configMINIMAL_STACK_SIZE,
REG_TEST_TASK_1_PARAMETER,
uxPriority,
NULL );
configASSERT( ret == pdPASS );
ret = xTaskCreate( prvRegisterTest2Task,
"RegTest2",
configMINIMAL_STACK_SIZE,
REG_TEST_TASK_2_PARAMETER,
uxPriority,
NULL );
configASSERT( ret == pdPASS );
}
/*-----------------------------------------------------------*/
BaseType_t xAreRegisterTasksStillRunning( void )
{
static uint32_t ulLastRegisterTest1Counter = 0, ulLastRegisterTest2Counter = 0;
/* If the register test task is still running then we expect the loop
* counters to have incremented since this function was last called. */
if( ulLastRegisterTest1Counter == ulRegisterTest1Counter )
{
xErrorDetected = pdTRUE;
}
if( ulLastRegisterTest2Counter == ulRegisterTest2Counter )
{
xErrorDetected = pdTRUE;
}
ulLastRegisterTest1Counter = ulRegisterTest1Counter;
ulLastRegisterTest2Counter = ulRegisterTest2Counter;
/* Errors detected in the task itself will have latched xErrorDetected
* to true. */
return ( BaseType_t ) !xErrorDetected;
}
/*-----------------------------------------------------------*/

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/*
* FreeRTOS V202104.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef REG_TEST_H
#define REG_TEST_H
void vStartRegisterTasks( UBaseType_t uxPriority );
BaseType_t xAreRegisterTasksStillRunning( void );
#endif /* REG_TEST_H */

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/*
* FreeRTOS V202104.00
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/* Standard includes. */
#include <stdio.h>
#include <stdlib.h>
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "timers.h"
#include "semphr.h"
/* Various test includes. */
#include "BlockQ.h"
#include "integer.h"
#include "semtest.h"
#include "PollQ.h"
#include "GenQTest.h"
#include "QPeek.h"
#include "recmutex.h"
#include "flop.h"
#include "TimerDemo.h"
#include "countsem.h"
#include "death.h"
#include "QueueSet.h"
#include "QueueOverwrite.h"
#include "EventGroupsDemo.h"
#include "IntSemTest.h"
#include "IntQueue.h"
#include "TaskNotify.h"
#include "TaskNotifyArray.h"
#include "QueueSetPolling.h"
#include "StaticAllocation.h"
#include "blocktim.h"
#include "AbortDelay.h"
#include "MessageBufferDemo.h"
#include "StreamBufferDemo.h"
#include "StreamBufferInterrupt.h"
#include "RegTests.h"
/**
* Priorities at which the tasks are created.
*/
#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 2 )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY )
#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )
#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY )
#define mainREGISTER_TEST_PRIORITY ( tskIDLE_PRIORITY )
/* The period of the check task, in ms, converted to ticks using the
pdMS_TO_TICKS() macro. mainNO_ERROR_CHECK_TASK_PERIOD is used if no errors have
been found, mainERROR_CHECK_TASK_PERIOD is used if an error has been found. */
#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 3000UL )
#define mainERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( 500UL )
/**
* Period used in timer tests.
*/
#define mainTIMER_TEST_PERIOD ( 50 )
/**
* Success output messages. This is used by the CI - do not change.
*/
#define mainDEMO_SUCCESS_MESSAGE "FreeRTOS Demo SUCCESS\r\n"
/*-----------------------------------------------------------*/
/**
* The task that periodically checks that all the standard demo tasks are
* still executing and error free.
*/
static void prvCheckTask( void *pvParameters );
/**
* Called by main() to run the full demo (as opposed to the blinky demo) when
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
*/
void main_full( void );
/**
* Tick hook used by the full demo, which includes code that interacts with
* some of the tests.
*/
void vFullDemoTickHook( void );
/*-----------------------------------------------------------*/
void main_full( void )
{
BaseType_t xResult;
xResult = xTaskCreate( prvCheckTask,
"Check",
configMINIMAL_STACK_SIZE,
NULL,
mainCHECK_TASK_PRIORITY,
NULL );
if( xResult == pdPASS )
{
#if( configSTART_TASK_NOTIFY_TESTS == 1 )
{
vStartTaskNotifyTask();
}
#endif /* configSTART_TASK_NOTIFY_TESTS */
#if( configSTART_TASK_NOTIFY_ARRAY_TESTS == 1 )
{
vStartTaskNotifyArrayTask();
}
#endif /* configSTART_TASK_NOTIFY_ARRAY_TESTS */
#if( configSTART_BLOCKING_QUEUE_TESTS == 1 )
{
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
}
#endif /* configSTART_BLOCKING_QUEUE_TESTS */
#if( configSTART_SEMAPHORE_TESTS == 1 )
{
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
}
#endif /* configSTART_SEMAPHORE_TESTS */
#if( configSTART_POLLED_QUEUE_TESTS == 1 )
{
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
}
#endif /* configSTART_POLLED_QUEUE_TESTS */
#if( configSTART_INTEGER_MATH_TESTS == 1 )
{
vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY );
}
#endif /* configSTART_INTEGER_MATH_TESTS */
#if( configSTART_GENERIC_QUEUE_TESTS == 1 )
{
vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );
}
#endif /* configSTART_GENERIC_QUEUE_TESTS */
#if( configSTART_PEEK_QUEUE_TESTS == 1 )
{
vStartQueuePeekTasks();
}
#endif /* configSTART_PEEK_QUEUE_TESTS */
#if( configSTART_MATH_TESTS == 1 )
{
vStartMathTasks( mainFLOP_TASK_PRIORITY );
}
#endif /* configSTART_MATH_TESTS */
#if( configSTART_RECURSIVE_MUTEX_TESTS == 1 )
{
vStartRecursiveMutexTasks();
}
#endif /* configSTART_RECURSIVE_MUTEX_TESTS */
#if( configSTART_COUNTING_SEMAPHORE_TESTS == 1 )
{
vStartCountingSemaphoreTasks();
}
#endif /* configSTART_COUNTING_SEMAPHORE_TESTS */
#if( configSTART_QUEUE_SET_TESTS == 1 )
{
vStartQueueSetTasks();
}
#endif /* configSTART_QUEUE_SET_TESTS */
#if( configSTART_QUEUE_OVERWRITE_TESTS == 1 )
{
vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY );
}
#endif /* configSTART_QUEUE_OVERWRITE_TESTS */
#if( configSTART_EVENT_GROUP_TESTS == 1 )
{
vStartEventGroupTasks();
}
#endif /* configSTART_EVENT_GROUP_TESTS */
#if( configSTART_INTERRUPT_SEMAPHORE_TESTS == 1 )
{
vStartInterruptSemaphoreTasks();
}
#endif /* configSTART_INTERRUPT_SEMAPHORE_TESTS */
#if( configSTART_QUEUE_SET_POLLING_TESTS == 1 )
{
vStartQueueSetPollingTask();
}
#endif /* configSTART_QUEUE_SET_POLLING_TESTS */
#if( configSTART_BLOCK_TIME_TESTS == 1 )
{
vCreateBlockTimeTasks();
}
#endif /* configSTART_BLOCK_TIME_TESTS */
#if( configSTART_ABORT_DELAY_TESTS == 1 )
{
vCreateAbortDelayTasks();
}
#endif /* configSTART_ABORT_DELAY_TESTS */
#if( configSTART_MESSAGE_BUFFER_TESTS == 1 )
{
vStartMessageBufferTasks( configMINIMAL_STACK_SIZE );
}
#endif /* configSTART_MESSAGE_BUFFER_TESTS */
#if(configSTART_STREAM_BUFFER_TESTS == 1 )
{
vStartStreamBufferTasks();
}
#endif /* configSTART_STREAM_BUFFER_TESTS */
#if( configSTART_STREAM_BUFFER_INTERRUPT_TESTS == 1 )
{
vStartStreamBufferInterruptDemo();
}
#endif /* configSTART_STREAM_BUFFER_INTERRUPT_TESTS */
#if( ( configSTART_TIMER_TESTS == 1 ) && ( configUSE_PREEMPTION != 0 ) )
{
/* Don't expect these tasks to pass when preemption is not used. */
vStartTimerDemoTask( mainTIMER_TEST_PERIOD );
}
#endif /* ( configSTART_TIMER_TESTS == 1 ) && ( configUSE_PREEMPTION != 0 ) */
#if( configSTART_INTERRUPT_QUEUE_TESTS == 1 )
{
vStartInterruptQueueTasks();
}
#endif /* configSTART_INTERRUPT_QUEUE_TESTS */
#if( configSTART_REGISTER_TESTS == 1 )
{
vStartRegisterTasks( mainREGISTER_TEST_PRIORITY );
}
#endif /* configSTART_REGISTER_TESTS */
#if( configSTART_DELETE_SELF_TESTS == 1 )
{
/* The suicide tasks must be created last as they need to know how many
* tasks were running prior to their creation. This then allows them to
* ascertain whether or not the correct/expected number of tasks are
* running at any given time. */
vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
}
#endif /* configSTART_DELETE_SELF_TESTS */
}
vTaskStartScheduler();
}
/*-----------------------------------------------------------*/
void vFullDemoTickHook( void )
{
/* Called from vApplicationTickHook() when the project is configured to
build the full test/demo applications. */
#if( configSTART_TASK_NOTIFY_TESTS == 1 )
{
xNotifyTaskFromISR();
}
#endif /* configSTART_TASK_NOTIFY_TESTS */
#if( configSTART_TASK_NOTIFY_ARRAY_TESTS == 1 )
{
xNotifyArrayTaskFromISR();
}
#endif /* configSTART_TASK_NOTIFY_ARRAY_TESTS */
#if( configSTART_QUEUE_SET_TESTS == 1 )
{
vQueueSetAccessQueueSetFromISR();
}
#endif /* configSTART_QUEUE_SET_TESTS */
#if( configSTART_QUEUE_OVERWRITE_TESTS == 1 )
{
vQueueOverwritePeriodicISRDemo();
}
#endif /* configSTART_QUEUE_OVERWRITE_TESTS */
#if( configSTART_EVENT_GROUP_TESTS == 1 )
{
vPeriodicEventGroupsProcessing();
}
#endif /* configSTART_EVENT_GROUP_TESTS */
#if( configSTART_INTERRUPT_SEMAPHORE_TESTS == 1 )
{
vInterruptSemaphorePeriodicTest();
}
#endif /* configSTART_INTERRUPT_SEMAPHORE_TESTS */
#if( configSTART_QUEUE_SET_POLLING_TESTS == 1 )
{
vQueueSetPollingInterruptAccess();
}
#endif /* configSTART_QUEUE_SET_POLLING_TESTS */
#if( configSTART_STREAM_BUFFER_TESTS == 1 )
{
vPeriodicStreamBufferProcessing();
}
#endif /* configSTART_STREAM_BUFFER_TESTS */
#if( configSTART_STREAM_BUFFER_INTERRUPT_TESTS == 1 )
{
vBasicStreamBufferSendFromISR();
}
#endif /* configSTART_STREAM_BUFFER_INTERRUPT_TESTS */
#if( ( configSTART_TIMER_TESTS == 1 ) && ( configUSE_PREEMPTION != 0 ) )
{
/* Only created when preemption is used. */
vTimerPeriodicISRTests();
}
#endif /* ( configSTART_TIMER_TESTS == 1 ) && ( configUSE_PREEMPTION != 0 ) */
#if( configSTART_INTERRUPT_QUEUE_TESTS == 1 )
{
portYIELD_FROM_ISR( xFirstTimerHandler() );
}
#endif /* configSTART_INTERRUPT_QUEUE_TESTS */
}
/*-----------------------------------------------------------*/
static void prvCheckTask( void *pvParameters )
{
TickType_t xNextWakeTime;
TickType_t xCycleFrequency = mainNO_ERROR_CHECK_TASK_PERIOD;
char * const pcPassMessage = mainDEMO_SUCCESS_MESSAGE;
char * pcStatusMessage = pcPassMessage;
extern void vToggleLED( void );
/* Silence compiler warnings about unused variables. */
( void ) pvParameters;
/* Demo start marker. */
configPRINT_STRING( "FreeRTOS Demo Start\r\n" );
/* Initialise xNextWakeTime - this only needs to be done once. */
xNextWakeTime = xTaskGetTickCount();
for( ;; )
{
/* Place this task in the blocked state until it is time to run again. */
vTaskDelayUntil( &xNextWakeTime, xCycleFrequency );
#if( configSTART_TASK_NOTIFY_TESTS == 1 )
{
if( xAreTaskNotificationTasksStillRunning() != pdTRUE )
{
pcStatusMessage = "FreeRTOS Demo ERROR: Notification.\r\n";
}
}
#endif /* configSTART_TASK_NOTIFY_TESTS */
#if( configSTART_TASK_NOTIFY_ARRAY_TESTS == 1 )
{
if( xAreTaskNotificationArrayTasksStillRunning() != pdTRUE )
{
pcStatusMessage = "FreeRTOS Demo ERROR: Notification Array.\r\n";
}
}
#endif /* configSTART_TASK_NOTIFY_ARRAY_TESTS */
#if( configSTART_BLOCKING_QUEUE_TESTS == 1 )
{
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
pcStatusMessage = "FreeRTOS Demo ERROR: BlockQueue.\r\n";
}
}
#endif /* configSTART_BLOCKING_QUEUE_TESTS */
#if( configSTART_SEMAPHORE_TESTS == 1 )
{
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
pcStatusMessage = "FreeRTOS Demo ERROR: SemTest.\r\n";
}
}
#endif /* configSTART_SEMAPHORE_TESTS */
#if( configSTART_POLLED_QUEUE_TESTS == 1 )
{
if( xArePollingQueuesStillRunning() != pdTRUE )
{
pcStatusMessage = "FreeRTOS Demo ERROR: PollQueue.\r\n";
}
}
#endif /* configSTART_POLLED_QUEUE_TESTS */
#if( configSTART_INTEGER_MATH_TESTS == 1 )
{
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
{
pcStatusMessage = "FreeRTOS Demo ERROR: IntMath.\r\n";
}
}
#endif /* configSTART_INTEGER_MATH_TESTS */
#if( configSTART_GENERIC_QUEUE_TESTS == 1 )
{
if( xAreGenericQueueTasksStillRunning() != pdTRUE )
{
pcStatusMessage = "FreeRTOS Demo ERROR: GenQueue.\r\n";
}
}
#endif /* configSTART_GENERIC_QUEUE_TESTS */
#if( configSTART_PEEK_QUEUE_TESTS == 1 )
{
if( xAreQueuePeekTasksStillRunning() != pdTRUE )
{
pcStatusMessage = "FreeRTOS Demo ERROR: QueuePeek.\r\n";
}
}
#endif /* configSTART_PEEK_QUEUE_TESTS */
#if( configSTART_MATH_TESTS == 1 )
{
if( xAreMathsTaskStillRunning() != pdPASS )
{
pcStatusMessage = "FreeRTOS Demo ERROR: Flop.\r\n";
}
}
#endif /* configSTART_MATH_TESTS */
#if( configSTART_RECURSIVE_MUTEX_TESTS == 1 )
{
if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
{
pcStatusMessage = "FreeRTOS Demo ERROR: RecMutex.\r\n";
}
}
#endif /* configSTART_RECURSIVE_MUTEX_TESTS */
#if( configSTART_COUNTING_SEMAPHORE_TESTS == 1 )
{
if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )
{
pcStatusMessage = "FreeRTOS Demo ERROR: CountSem.\r\n";
}
}
#endif /* configSTART_COUNTING_SEMAPHORE_TESTS */
#if( configSTART_QUEUE_SET_TESTS == 1 )
{
if( xAreQueueSetTasksStillRunning() != pdPASS )
{
pcStatusMessage = "FreeRTOS Demo ERROR: Queue set.\r\n";
}
}
#endif /* configSTART_QUEUE_SET_TESTS */
#if( configSTART_QUEUE_OVERWRITE_TESTS == 1 )
{
if( xIsQueueOverwriteTaskStillRunning() != pdPASS )
{
pcStatusMessage = "FreeRTOS Demo ERROR: Queue overwrite.\r\n";
}
}
#endif /* configSTART_QUEUE_OVERWRITE_TESTS */
#if( configSTART_EVENT_GROUP_TESTS == 1 )
{
if( xAreEventGroupTasksStillRunning() != pdTRUE )
{
pcStatusMessage = "FreeRTOS Demo ERROR: EventGroup.\r\n";
}
}
#endif /* configSTART_EVENT_GROUP_TESTS */
#if( configSTART_INTERRUPT_SEMAPHORE_TESTS == 1 )
{
if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE )
{
pcStatusMessage = "FreeRTOS Demo ERROR: IntSem.\r\n";
}
}
#endif /* configSTART_INTERRUPT_SEMAPHORE_TESTS */
#if( configSTART_QUEUE_SET_POLLING_TESTS == 1 )
{
if( xAreQueueSetPollTasksStillRunning() != pdPASS )
{
pcStatusMessage = "FreeRTOS Demo ERROR: Queue set polling.\r\n";
}
}
#endif /* configSTART_QUEUE_SET_POLLING_TESTS */
#if( configSTART_BLOCK_TIME_TESTS == 1 )
{
if( xAreBlockTimeTestTasksStillRunning() != pdPASS )
{
pcStatusMessage = "FreeRTOS Demo ERROR: Block time.\r\n";
}
}
#endif /* configSTART_BLOCK_TIME_TESTS */
#if( configSTART_ABORT_DELAY_TESTS == 1 )
{
if( xAreAbortDelayTestTasksStillRunning() != pdPASS )
{
pcStatusMessage = "FreeRTOS Demo ERROR: Abort delay.\r\n";
}
}
#endif /* configSTART_ABORT_DELAY_TESTS */
#if( configSTART_MESSAGE_BUFFER_TESTS == 1 )
{
if( xAreMessageBufferTasksStillRunning() != pdTRUE )
{
pcStatusMessage = "FreeRTOS Demo ERROR: MessageBuffer.\r\n";
}
}
#endif /* configSTART_MESSAGE_BUFFER_TESTS */
#if( configSTART_STREAM_BUFFER_TESTS == 1 )
{
if( xAreStreamBufferTasksStillRunning() != pdTRUE )
{
pcStatusMessage = "FreeRTOS Demo ERROR: StreamBuffer.\r\n";
}
}
#endif /* configSTART_STREAM_BUFFER_TESTS */
#if( configSTART_STREAM_BUFFER_INTERRUPT_TESTS == 1 )
{
if( xIsInterruptStreamBufferDemoStillRunning() != pdPASS )
{
pcStatusMessage = "FreeRTOS Demo ERROR: Stream buffer interrupt.\r\n";
}
}
#endif /* configSTART_STREAM_BUFFER_INTERRUPT_TESTS */
#if( ( configSTART_TIMER_TESTS == 1 ) && ( configUSE_PREEMPTION != 0 ) )
{
if( xAreTimerDemoTasksStillRunning( xCycleFrequency ) != pdTRUE )
{
pcStatusMessage = "FreeRTOS Demo ERROR: TimerDemo.\r\n";
}
}
#endif /* ( configSTART_TIMER_TESTS == 1 ) && ( configUSE_PREEMPTION != 0 ) */
#if( configSTART_INTERRUPT_QUEUE_TESTS == 1 )
{
if( xAreIntQueueTasksStillRunning() != pdTRUE )
{
pcStatusMessage = "FreeRTOS Demo ERROR: IntQueue.\r\n";
}
}
#endif /* configSTART_INTERRUPT_QUEUE_TESTS */
#if( configSTART_REGISTER_TESTS == 1 )
{
if( xAreRegisterTasksStillRunning() != pdTRUE )
{
pcStatusMessage = "FreeRTOS Demo ERROR: RegTests.\r\n";
}
}
#endif /* configSTART_REGISTER_TESTS */
#if( configSTART_DELETE_SELF_TESTS == 1 )
{
if( xIsCreateTaskStillRunning() != pdTRUE )
{
pcStatusMessage = "FreeRTOS Demo ERROR: Death.\r\n";
}
}
#endif /* configSTART_DELETE_SELF_TESTS */
/* Toggle the LED to show the system status if the UART is not
* connected. */
vToggleLED();
/* If an error has been found then increase the LED toggle rate by
* increasing the cycle frequency. */
if( pcStatusMessage != pcPassMessage )
{
xCycleFrequency = mainERROR_CHECK_TASK_PERIOD;
}
configPRINT_STRING( pcStatusMessage );
}
}
/*-----------------------------------------------------------*/

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/*
* FreeRTOS V202107.00
* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
/******************************************************************************
* This project provides two demo applications. A simple blinky style project,
* and a more comprehensive test and demo application. The
* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to
* select between the two. The simply blinky demo is implemented and described
* in main_blinky.c. The more comprehensive test and demo application is
* implemented and described in main_full.c.
*
* This file implements the code that is not demo specific, including the
* hardware setup and standard FreeRTOS hook functions.
*
* When running on the PolarFire SoC hardware:
* When executing correctly the yellow LED will toggle every three seconds. If
* the yellow LED toggles every 500ms then one of the self-monitoring test tasks
* discovered a potential issue. If the red led toggles rapidly then a hardware
* exception occurred.
*
* ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON
* THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO
* APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT!
*
*/
/* FreeRTOS kernel includes. */
#include <FreeRTOS.h>
#include <task.h>
/* PolarFire HAL includes. */
#include "mpfs_hal/mss_hal.h"
#include "drivers/mss/mss_gpio/mss_gpio.h"
#include "drivers/mss/mss_mmuart/mss_uart.h"
/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
or 0 to run the more comprehensive test and demo application. */
#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0
/*-----------------------------------------------------------*/
/*
* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
* main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
*/
#if ( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )
extern void main_blinky( void );
#else
extern void main_full( void );
#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */
/*
* Prototypes for the standard FreeRTOS callback/hook functions implemented
* within this file. See https://www.freertos.org/a00016.html
*/
void vApplicationMallocFailedHook( void );
void vApplicationIdleHook( void );
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );
void vApplicationTickHook( void );
/*
* Setup the hardware to run this demo.
*/
static void prvSetupHardware( void );
/*-----------------------------------------------------------*/
/* Main function for the HART0(E51 processor). Application code running on
* HART0 is placed here. */
void e51( void )
{
prvSetupHardware();
/* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
* of this file. */
#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 )
{
main_blinky();
}
#else
{
main_full();
}
#endif
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* Configure UART0. */
SYSREG->SUBBLK_CLOCK_CR |= SUBBLK_CLOCK_CR_MMUART0_MASK;
SYSREG->SOFT_RESET_CR &= ~SOFT_RESET_CR_MMUART0_MASK;
MSS_UART_init( &( g_mss_uart0_lo ),
MSS_UART_115200_BAUD,
MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT );
/* Configure the LED. */
mss_config_clk_rst( MSS_PERIPH_GPIO2, ( uint8_t )MPFS_HAL_FIRST_HART, PERIPHERAL_ON );
MSS_GPIO_config( GPIO2_LO, MSS_GPIO_16, MSS_GPIO_OUTPUT_MODE ); /* Red Led (LED1). */
MSS_GPIO_config( GPIO2_LO, MSS_GPIO_18, MSS_GPIO_OUTPUT_MODE ); /* Yellow Led (LED3). */
}
/*-----------------------------------------------------------*/
void vApplicationMallocFailedHook( void )
{
/* vApplicationMallocFailedHook() will only be called if
* configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
* function that will get called if a call to pvPortMalloc() fails.
* pvPortMalloc() is called internally by the kernel whenever a task, queue,
* timer or semaphore is created. It is also called by various parts of the
* demo application. If heap_1.c or heap_2.c are used, then the size of the
* heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
* FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
* to query the size of free heap space that remains (although it does not
* provide information on how the remaining heap might be fragmented). */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
* to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
* task. It is essential that code added to this hook function never attempts
* to block in any way (for example, call xQueueReceive() with a block time
* specified, or call vTaskDelay()). If the application makes use of the
* vTaskDelete() API function (as this demo application does) then it is also
* important that vApplicationIdleHook() is permitted to return to its calling
* function, because it is the responsibility of the idle task to clean up
* memory allocated by the kernel to any task that has since been deleted. */
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
{
( void ) pcTaskName;
( void ) pxTask;
/* Run time stack overflow checking is performed if
* configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
* function is called if a stack overflow is detected. */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationTickHook( void )
{
/* The tests in the full demo expect some interaction with interrupts. */
#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY != 1 )
{
extern void vFullDemoTickHook( void );
vFullDemoTickHook();
}
#endif
}
/*-----------------------------------------------------------*/
void vToggleLED( void )
{
static volatile uint8_t value = 0u;
value = ( value == 0u ) ? 1u : 0u;
MSS_GPIO_set_output( GPIO2_LO, MSS_GPIO_18, value );
}
/*-----------------------------------------------------------*/
void vAssertCalled( void )
{
volatile uint32_t ul;
const uint32_t ulNullLoopDelay = 0x1ffffUL;
static volatile uint8_t value = 0u;
taskDISABLE_INTERRUPTS();
/* Flash the red LED to indicate that assert was hit - interrupts are off
* here to prevent any further tick interrupts or context switches, so the
* delay is implemented as a crude loop instead of a peripheral timer. */
for( ;; )
{
for( ul = 0; ul < ulNullLoopDelay; ul++ )
{
__asm volatile( "nop" );
}
value = ( value == 0u ) ? 1u : 0u;
MSS_GPIO_set_output( GPIO2_LO, MSS_GPIO_16, value );
}
}
/*-----------------------------------------------------------*/

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_clk_ddr_pll.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_CLK_DDR_PLL_H_
#define HW_CLK_DDR_PLL_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_DDR_SOFT_RESET)
/*This is a compulsory register for all SCB slaves and must be at the same
offset in all slaves to facilitate global soft reset of all SCB registers with
a single broadcast write from the SCB master. */
#define LIBERO_SETTING_DDR_SOFT_RESET 0x00000000UL
/* NV_MAP [0:1] RST */
/* V_MAP [1:1] RST */
/* PERIPH [8:1] RST */
/* BLOCKID [16:16] ID */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_CTRL)
/*PLL control register */
#define LIBERO_SETTING_DDR_PLL_CTRL 0x0100003FUL
/* REG_POWERDOWN_B [0:1] RW value= 0x1 */
/* REG_RFDIV_EN [1:1] RW value= 0x1 */
/* REG_DIVQ0_EN [2:1] RW value= 0x1 */
/* REG_DIVQ1_EN [3:1] RW value= 0x1 */
/* REG_DIVQ2_EN [4:1] RW value= 0x1 */
/* REG_DIVQ3_EN [5:1] RW value= 0x1 */
/* REG_RFCLK_SEL [6:1] RW value= 0x0 */
/* RESETONLOCK [7:1] RW value= 0x0 */
/* BYPCK_SEL [8:4] RW value= 0x0 */
/* REG_BYPASS_GO_B [12:1] RW value= 0x0 */
/* RESERVE10 [13:3] RSVD */
/* REG_BYPASSPRE [16:4] RW value= 0x0 */
/* REG_BYPASSPOST [20:4] RW value= 0x0 */
/* LP_REQUIRES_LOCK [24:1] RW value= 0x1 */
/* LOCK [25:1] RO */
/* LOCK_INT_EN [26:1] RW value= 0x0 */
/* UNLOCK_INT_EN [27:1] RW value= 0x0 */
/* LOCK_INT [28:1] SW1C */
/* UNLOCK_INT [29:1] SW1C */
/* RESERVE11 [30:1] RSVD */
/* LOCK_B [31:1] RO */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_REF_FB)
/*PLL reference and feedback registers */
#define LIBERO_SETTING_DDR_PLL_REF_FB 0x00000500UL
/* FSE_B [0:1] RW value= 0x0 */
/* FBCK_SEL [1:2] RW value= 0x0 */
/* FOUTFB_SELMUX_EN [3:1] RW value= 0x0 */
/* RESERVE12 [4:4] RSVD */
/* RFDIV [8:6] RW value= 0x5 */
/* RESERVE13 [14:2] RSVD */
/* RESERVE14 [16:12] RSVD */
/* RESERVE15 [28:4] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_FRACN)
/*PLL fractional register */
#define LIBERO_SETTING_DDR_PLL_FRACN 0x00000000UL
/* FRACN_EN [0:1] RW value= 0x0 */
/* FRACN_DAC_EN [1:1] RW value= 0x0 */
/* RESERVE16 [2:6] RSVD */
/* RESERVE17 [8:24] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_DIV_0_1)
/*PLL 0/1 division registers */
#define LIBERO_SETTING_DDR_PLL_DIV_0_1 0x02000100UL
/* VCO0PH_SEL [0:3] RO */
/* DIV0_START [3:3] RW value= 0x0 */
/* RESERVE18 [6:2] RSVD */
/* POST0DIV [8:7] RW value= 0x1 */
/* RESERVE19 [15:1] RSVD */
/* VCO1PH_SEL [16:3] RO */
/* DIV1_START [19:3] RW value= 0x0 */
/* RESERVE20 [22:2] RSVD */
/* POST1DIV [24:7] RW value= 0x2 */
/* RESERVE21 [31:1] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_DIV_2_3)
/*PLL 2/3 division registers */
#define LIBERO_SETTING_DDR_PLL_DIV_2_3 0x01000100UL
/* VCO2PH_SEL [0:3] RO */
/* DIV2_START [3:3] RW value= 0x0 */
/* RESERVE22 [6:2] RSVD */
/* POST2DIV [8:7] RW value= 0x1 */
/* RESERVE23 [15:1] RSVD */
/* VCO3PH_SEL [16:3] RO */
/* DIV3_START [19:3] RW value= 0x0 */
/* RESERVE24 [22:2] RSVD */
/* POST3DIV [24:7] RW value= 0x1 */
/* CKPOST3_SEL [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_CTRL2)
/*PLL control register */
#define LIBERO_SETTING_DDR_PLL_CTRL2 0x00001020UL
/* BWI [0:2] RW value= 0x0 */
/* BWP [2:2] RW value= 0x0 */
/* IREF_EN [4:1] RW value= 0x0 */
/* IREF_TOGGLE [5:1] RW value= 0x1 */
/* RESERVE25 [6:3] RSVD */
/* LOCKCNT [9:4] RW value= 0x8 */
/* RESERVE26 [13:4] RSVD */
/* ATEST_EN [17:1] RW value= 0x0 */
/* ATEST_SEL [18:3] RW value= 0x0 */
/* RESERVE27 [21:11] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_CAL)
/*PLL calibration register */
#define LIBERO_SETTING_DDR_PLL_CAL 0x00000D06UL
/* DSKEWCALCNT [0:3] RW value= 0x6 */
/* DSKEWCAL_EN [3:1] RW value= 0x0 */
/* DSKEWCALBYP [4:1] RW value= 0x0 */
/* RESERVE28 [5:3] RSVD */
/* DSKEWCALIN [8:7] RW value= 0xd */
/* RESERVE29 [15:1] RSVD */
/* DSKEWCALOUT [16:7] RO */
/* RESERVE30 [23:9] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_PLL_PHADJ)
/*PLL phase registers */
#define LIBERO_SETTING_DDR_PLL_PHADJ 0x00005003UL
/* PLL_REG_SYNCREFDIV_EN [0:1] RW value= 0x1 */
/* PLL_REG_ENABLE_SYNCREFDIV [1:1] RW value= 0x1 */
/* REG_OUT0_PHSINIT [2:3] RW value= 0x0 */
/* REG_OUT1_PHSINIT [5:3] RW value= 0x0 */
/* REG_OUT2_PHSINIT [8:3] RW value= 0x0 */
/* REG_OUT3_PHSINIT [11:3] RW value= 0x2 */
/* REG_LOADPHS_B [14:1] RW value= 0x1 */
/* RESERVE31 [15:17] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_SSCG_REG_0)
/*SSCG registers 0 */
#define LIBERO_SETTING_DDR_SSCG_REG_0 0x00000000UL
/* DIVVAL [0:6] RW value= 0x0 */
/* FRACIN [6:24] RW value= 0x0 */
/* RESERVE00 [30:2] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_SSCG_REG_1)
/*SSCG registers 1 */
#define LIBERO_SETTING_DDR_SSCG_REG_1 0x00000000UL
/* DOWNSPREAD [0:1] RW value= 0x0 */
/* SSMD [1:5] RW value= 0x0 */
/* FRACMOD [6:24] RO */
/* RESERVE01 [30:2] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_SSCG_REG_2)
/*SSCG registers 2 */
#define LIBERO_SETTING_DDR_SSCG_REG_2 0x00000080UL
/* INTIN [0:12] RW value= 0x80 */
/* INTMOD [12:12] RO */
/* RESERVE02 [24:8] RSVD */
#endif
#if !defined (LIBERO_SETTING_DDR_SSCG_REG_3)
/*SSCG registers 3 */
#define LIBERO_SETTING_DDR_SSCG_REG_3 0x00000001UL
/* SSE_B [0:1] RW value= 0x1 */
/* SEL_EXTWAVE [1:2] RW value= 0x0 */
/* EXT_MAXADDR [3:8] RW value= 0x0 */
/* TBLADDR [11:8] RO */
/* RANDOM_FILTER [19:1] RW value= 0x0 */
/* RANDOM_SEL [20:2] RW value= 0x0 */
/* RESERVE03 [22:1] RSVD */
/* RESERVE04 [23:9] RSVD */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_CLK_DDR_PLL_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_clk_mss_cfm.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_CLK_MSS_CFM_H_
#define HW_CLK_MSS_CFM_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_MSS_BCLKMUX)
/*Input mux selections */
#define LIBERO_SETTING_MSS_BCLKMUX 0x00000208UL
/* BCLK0_SEL [0:5] RW value= 0x8 */
/* BCLK1_SEL [5:5] RW value= 0x10 */
/* BCLK2_SEL [10:5] RW value= 0x0 */
/* BCLK3_SEL [15:5] RW value= 0x0 */
/* BCLK4_SEL [20:5] RW value= 0x0 */
/* BCLK5_SEL [25:5] RW value= 0x0 */
/* RESERVED [30:2] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_CKMUX)
/*Input mux selections */
#define LIBERO_SETTING_MSS_PLL_CKMUX 0x00000155UL
/* CLK_IN_MAC_TSU_SEL [0:2] RW value= 0x1 */
/* PLL0_RFCLK0_SEL [2:2] RW value= 0x1 */
/* PLL0_RFCLK1_SEL [4:2] RW value= 0x1 */
/* PLL1_RFCLK0_SEL [6:2] RW value= 0x1 */
/* PLL1_RFCLK1_SEL [8:2] RW value= 0x1 */
/* PLL1_FDR_SEL [10:5] RW value= 0x0 */
/* RESERVED [15:17] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSS_MSSCLKMUX)
/*MSS Clock mux selections */
#define LIBERO_SETTING_MSS_MSSCLKMUX 0x00000003UL
/* MSSCLK_MUX_SEL [0:2] RW value= 0x3 */
/* MSSCLK_MUX_MD [2:2] RW value= 0x0 */
/* CLK_STANDBY_SEL [4:1] RW value= 0x0 */
/* RESERVED [5:27] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSS_SPARE0)
/*spare logic */
#define LIBERO_SETTING_MSS_SPARE0 0x00000000UL
/* SPARE0 [0:32] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSS_FMETER_ADDR)
/*Frequency_meter_address_selections */
#define LIBERO_SETTING_MSS_FMETER_ADDR 0x00000000UL
/* ADDR10 [0:2] RSVD */
/* ADDR [2:4] RW value= 0x0 */
/* RESERVE18 [6:26] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_FMETER_DATAW)
/*Frequency_meter_data_write */
#define LIBERO_SETTING_MSS_FMETER_DATAW 0x00000000UL
/* DATA [0:24] RW value= 0x0 */
/* STROBE [24:1] W1P */
/* RESERVE19 [25:7] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_FMETER_DATAR)
/*Frequency_meter_data_read */
#define LIBERO_SETTING_MSS_FMETER_DATAR 0x00000000UL
/* DATA [0:24] RO */
/* RESERVE20 [24:8] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_IMIRROR_TRIM)
/*Imirror TRIM Bits */
#define LIBERO_SETTING_MSS_IMIRROR_TRIM 0x00000000UL
/* BG_CODE [0:3] RW value= 0x0 */
/* CC_CODE [3:8] RW value= 0x0 */
/* RESERVE21 [11:21] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_TEST_CTRL)
/*Test MUX Controls */
#define LIBERO_SETTING_MSS_TEST_CTRL 0x00000000UL
/* OSC_ENABLE [0:4] RW value= 0x0 */
/* ATEST_EN [4:1] RW value= 0x0 */
/* ATEST_SEL [5:5] RW value= 0x0 */
/* DTEST_EN [10:1] RW value= 0x0 */
/* DTEST_SEL [11:5] RW value= 0x0 */
/* RESERVE22 [16:16] RSVD */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_CLK_MSS_CFM_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_clk_mss_pll.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_CLK_MSS_PLL_H_
#define HW_CLK_MSS_PLL_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_CTRL)
/*PLL control register */
#define LIBERO_SETTING_MSS_PLL_CTRL 0x01000037UL
/* REG_POWERDOWN_B [0:1] RW value= 0x1 */
/* REG_RFDIV_EN [1:1] RW value= 0x1 */
/* REG_DIVQ0_EN [2:1] RW value= 0x1 */
/* REG_DIVQ1_EN [3:1] RW value= 0x0 */
/* REG_DIVQ2_EN [4:1] RW value= 0x1 */
/* REG_DIVQ3_EN [5:1] RW value= 0x1 */
/* REG_RFCLK_SEL [6:1] RW value= 0x0 */
/* RESETONLOCK [7:1] RW value= 0x0 */
/* BYPCK_SEL [8:4] RW value= 0x0 */
/* REG_BYPASS_GO_B [12:1] RW value= 0x0 */
/* RESERVE10 [13:3] RSVD */
/* REG_BYPASSPRE [16:4] RW value= 0x0 */
/* REG_BYPASSPOST [20:4] RW value= 0x0 */
/* LP_REQUIRES_LOCK [24:1] RW value= 0x1 */
/* LOCK [25:1] RO */
/* LOCK_INT_EN [26:1] RW value= 0x0 */
/* UNLOCK_INT_EN [27:1] RW value= 0x0 */
/* LOCK_INT [28:1] SW1C */
/* UNLOCK_INT [29:1] SW1C */
/* RESERVE11 [30:1] RSVD */
/* LOCK_B [31:1] RO */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_REF_FB)
/*PLL reference and feedback registers */
#define LIBERO_SETTING_MSS_PLL_REF_FB 0x00000500UL
/* FSE_B [0:1] RW value= 0x0 */
/* FBCK_SEL [1:2] RW value= 0x0 */
/* FOUTFB_SELMUX_EN [3:1] RW value= 0x0 */
/* RESERVE12 [4:4] RSVD */
/* RFDIV [8:6] RW value= 0x5 */
/* RESERVE13 [14:2] RSVD */
/* RESERVE14 [16:12] RSVD */
/* RESERVE15 [28:4] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_FRACN)
/*PLL fractional register */
#define LIBERO_SETTING_MSS_PLL_FRACN 0x00000000UL
/* FRACN_EN [0:1] RW value= 0x0 */
/* FRACN_DAC_EN [1:1] RW value= 0x0 */
/* RESERVE16 [2:6] RSVD */
/* RESERVE17 [8:24] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_DIV_0_1)
/*PLL 0/1 division registers */
#define LIBERO_SETTING_MSS_PLL_DIV_0_1 0x01000200UL
/* VCO0PH_SEL [0:3] RO */
/* DIV0_START [3:3] RW value= 0x0 */
/* RESERVE18 [6:2] RSVD */
/* POST0DIV [8:7] RW value= 0x2 */
/* RESERVE19 [15:1] RSVD */
/* VCO1PH_SEL [16:3] RO */
/* DIV1_START [19:3] RW value= 0x0 */
/* RESERVE20 [22:2] RSVD */
/* POST1DIV [24:7] RW value= 0x1 */
/* RESERVE21 [31:1] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_DIV_2_3)
/*PLL 2/3 division registers */
#define LIBERO_SETTING_MSS_PLL_DIV_2_3 0x0F000600UL
/* VCO2PH_SEL [0:3] RO */
/* DIV2_START [3:3] RW value= 0x0 */
/* RESERVE22 [6:2] RSVD */
/* POST2DIV [8:7] RW value= 0x6 */
/* RESERVE23 [15:1] RSVD */
/* VCO3PH_SEL [16:3] RO */
/* DIV3_START [19:3] RW value= 0x0 */
/* RESERVE24 [22:2] RSVD */
/* POST3DIV [24:7] RW value= 0xF */
/* CKPOST3_SEL [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_CTRL2)
/*PLL control register */
#define LIBERO_SETTING_MSS_PLL_CTRL2 0x00001020UL
/* BWI [0:2] RW value= 0x0 */
/* BWP [2:2] RW value= 0x0 */
/* IREF_EN [4:1] RW value= 0x0 */
/* IREF_TOGGLE [5:1] RW value= 0x1 */
/* RESERVE25 [6:3] RSVD */
/* LOCKCNT [9:4] RW value= 0x8 */
/* RESERVE26 [13:4] RSVD */
/* ATEST_EN [17:1] RW value= 0x0 */
/* ATEST_SEL [18:3] RW value= 0x0 */
/* RESERVE27 [21:11] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_CAL)
/*PLL calibration register */
#define LIBERO_SETTING_MSS_PLL_CAL 0x00000D06UL
/* DSKEWCALCNT [0:3] RW value= 0x6 */
/* DSKEWCAL_EN [3:1] RW value= 0x0 */
/* DSKEWCALBYP [4:1] RW value= 0x0 */
/* RESERVE28 [5:3] RSVD */
/* DSKEWCALIN [8:7] RW value= 0xd */
/* RESERVE29 [15:1] RSVD */
/* DSKEWCALOUT [16:7] RO */
/* RESERVE30 [23:9] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_PLL_PHADJ)
/*PLL phase registers */
#define LIBERO_SETTING_MSS_PLL_PHADJ 0x00004003UL
/* PLL_REG_SYNCREFDIV_EN [0:1] RW value= 0x1 */
/* PLL_REG_ENABLE_SYNCREFDIV [1:1] RW value= 0x1 */
/* REG_OUT0_PHSINIT [2:3] RW value= 0x0 */
/* REG_OUT1_PHSINIT [5:3] RW value= 0x0 */
/* REG_OUT2_PHSINIT [8:3] RW value= 0x0 */
/* REG_OUT3_PHSINIT [11:3] RW value= 0x8 */
/* REG_LOADPHS_B [14:1] RW value= 0x0 */
/* RESERVE31 [15:17] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_SSCG_REG_0)
/*SSCG registers 0 */
#define LIBERO_SETTING_MSS_SSCG_REG_0 0x00000000UL
/* DIVVAL [0:6] RW value= 0x0 */
/* FRACIN [6:24] RW value= 0x0 */
/* RESERVE00 [30:2] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_SSCG_REG_1)
/*SSCG registers 1 */
#define LIBERO_SETTING_MSS_SSCG_REG_1 0x00000000UL
/* DOWNSPREAD [0:1] RW value= 0x0 */
/* SSMD [1:5] RW value= 0x0 */
/* FRACMOD [6:24] RO */
/* RESERVE01 [30:2] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_SSCG_REG_2)
/*SSCG registers 2 */
#define LIBERO_SETTING_MSS_SSCG_REG_2 0x000000C0UL
/* INTIN [0:12] RW value= 0xC0 */
/* INTMOD [12:12] RO */
/* RESERVE02 [24:8] RSVD */
#endif
#if !defined (LIBERO_SETTING_MSS_SSCG_REG_3)
/*SSCG registers 3 */
#define LIBERO_SETTING_MSS_SSCG_REG_3 0x00000001UL
/* SSE_B [0:1] RW value= 0x1 */
/* SEL_EXTWAVE [1:2] RW value= 0x0 */
/* EXT_MAXADDR [3:8] RW value= 0x0 */
/* TBLADDR [11:8] RO */
/* RANDOM_FILTER [19:1] RW value= 0x0 */
/* RANDOM_SEL [20:2] RW value= 0x0 */
/* RESERVE03 [22:1] RSVD */
/* RESERVE04 [23:9] RSVD */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_CLK_MSS_PLL_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_clk_sgmii_cfm.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_CLK_SGMII_CFM_H_
#define HW_CLK_SGMII_CFM_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_SGMII_REFCLKMUX)
/*Input mux selections */
#define LIBERO_SETTING_SGMII_REFCLKMUX 0x00000005UL
/* PLL0_RFCLK0_SEL [0:2] RW value= 0x1 */
/* PLL0_RFCLK1_SEL [2:2] RW value= 0x1 */
/* RESERVED [4:28] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SGMII_SGMII_CLKMUX)
/*sgmii clk mux */
#define LIBERO_SETTING_SGMII_SGMII_CLKMUX 0x00000005UL
/* SGMII_CLKMUX [0:32] RW value= 0x5 */
#endif
#if !defined (LIBERO_SETTING_SGMII_SPARE0)
/*spare logic */
#define LIBERO_SETTING_SGMII_SPARE0 0x00000000UL
/* RESERVED [0:32] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SGMII_CLK_XCVR)
/*Clock_Receiver */
#define LIBERO_SETTING_SGMII_CLK_XCVR 0x00002C30UL
/* EN_UDRIVE_P [0:1] RW value= 0x0 */
/* EN_INS_HYST_P [1:1] RW value= 0x0 */
/* EN_TERM_P [2:2] RW value= 0x0 */
/* EN_RXMODE_P [4:2] RW value= 0x3 */
/* EN_UDRIVE_N [6:1] RW value= 0x0 */
/* EN_INS_HYST_N [7:1] RW value= 0x0 */
/* EN_TERM_N [8:2] RW value= 0x0 */
/* EN_RXMODE_N [10:2] RW value= 0x3 */
/* CLKBUF_EN_PULLUP [12:1] RW value= 0x0 */
/* EN_RDIFF [13:1] RW value= 0x1 */
/* RESERVED [14:18] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SGMII_TEST_CTRL)
/*Test MUX Controls */
#define LIBERO_SETTING_SGMII_TEST_CTRL 0x00000000UL
/* OSC_ENABLE [0:4] RW value= 0x0 */
/* ATEST_EN [4:1] RW value= 0x0 */
/* ATEST_SEL [5:5] RW value= 0x0 */
/* DTEST_EN [10:1] RW value= 0x0 */
/* DTEST_SEL [11:5] RW value= 0x0 */
/* RESERVE22 [16:16] RSVD */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_CLK_SGMII_CFM_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_clk_sgmii_pll.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_CLK_SGMII_PLL_H_
#define HW_CLK_SGMII_PLL_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_SGMII_SOFT_RESET)
/*This is a compulsory register for all SCB slaves and must be at the same
offset in all slaves to facilitate global soft reset of all SCB registers with
a single broadcast write from the SCB master. */
#define LIBERO_SETTING_SGMII_SOFT_RESET 0x00000000UL
/* NV_MAP [0:1] RST */
/* V_MAP [1:1] RST */
/* PERIPH [8:1] RST */
/* BLOCKID [16:16] ID */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_CTRL)
/*PLL control register */
#define LIBERO_SETTING_SGMII_PLL_CTRL 0x0100003FUL
/* REG_POWERDOWN_B [0:1] RW value= 0x1 */
/* REG_RFDIV_EN [1:1] RW value= 0x1 */
/* REG_DIVQ0_EN [2:1] RW value= 0x1 */
/* REG_DIVQ1_EN [3:1] RW value= 0x1 */
/* REG_DIVQ2_EN [4:1] RW value= 0x1 */
/* REG_DIVQ3_EN [5:1] RW value= 0x1 */
/* REG_RFCLK_SEL [6:1] RW value= 0x0 */
/* RESETONLOCK [7:1] RW value= 0x0 */
/* BYPCK_SEL [8:4] RW value= 0x0 */
/* REG_BYPASS_GO_B [12:1] RW value= 0x0 */
/* RESERVE10 [13:3] RSVD */
/* REG_BYPASSPRE [16:4] RW value= 0x0 */
/* REG_BYPASSPOST [20:4] RW value= 0x0 */
/* LP_REQUIRES_LOCK [24:1] RW value= 0x1 */
/* LOCK [25:1] RO */
/* LOCK_INT_EN [26:1] RW value= 0x0 */
/* UNLOCK_INT_EN [27:1] RW value= 0x0 */
/* LOCK_INT [28:1] SW1C */
/* UNLOCK_INT [29:1] SW1C */
/* RESERVE11 [30:1] RSVD */
/* LOCK_B [31:1] RO */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_REF_FB)
/*PLL reference and feedback registers */
#define LIBERO_SETTING_SGMII_PLL_REF_FB 0x00000100UL
/* FSE_B [0:1] RW value= 0x0 */
/* FBCK_SEL [1:2] RW value= 0x0 */
/* FOUTFB_SELMUX_EN [3:1] RW value= 0x0 */
/* RESERVE12 [4:4] RSVD */
/* RFDIV [8:6] RW value= 0x1 */
/* RESERVE13 [14:2] RSVD */
/* RESERVE14 [16:12] RSVD */
/* RESERVE15 [28:4] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_FRACN)
/*PLL fractional register */
#define LIBERO_SETTING_SGMII_PLL_FRACN 0x00000000UL
/* FRACN_EN [0:1] RW value= 0x0 */
/* FRACN_DAC_EN [1:1] RW value= 0x0 */
/* RESERVE16 [2:6] RSVD */
/* RESERVE17 [8:24] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_DIV_0_1)
/*PLL 0/1 division registers */
#define LIBERO_SETTING_SGMII_PLL_DIV_0_1 0x01000100UL
/* VCO0PH_SEL [0:3] RO */
/* DIV0_START [3:3] RW value= 0x0 */
/* RESERVE18 [6:2] RSVD */
/* POST0DIV [8:7] RW value= 0x1 */
/* RESERVE19 [15:1] RSVD */
/* VCO1PH_SEL [16:3] RO */
/* DIV1_START [19:3] RW value= 0x0 */
/* RESERVE20 [22:2] RSVD */
/* POST1DIV [24:7] RW value= 0x1 */
/* RESERVE21 [31:1] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_DIV_2_3)
/*PLL 2/3 division registers */
#define LIBERO_SETTING_SGMII_PLL_DIV_2_3 0x01000100UL
/* VCO2PH_SEL [0:3] RO */
/* DIV2_START [3:3] RW value= 0x0 */
/* RESERVE22 [6:2] RSVD */
/* POST2DIV [8:7] RW value= 0x1 */
/* RESERVE23 [15:1] RSVD */
/* VCO3PH_SEL [16:3] RO */
/* DIV3_START [19:3] RW value= 0x0 */
/* RESERVE24 [22:2] RSVD */
/* POST3DIV [24:7] RW value= 0x1 */
/* CKPOST3_SEL [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_CTRL2)
/*PLL control register */
#define LIBERO_SETTING_SGMII_PLL_CTRL2 0x00001020UL
/* BWI [0:2] RW value= 0x0 */
/* BWP [2:2] RW value= 0x0 */
/* IREF_EN [4:1] RW value= 0x0 */
/* IREF_TOGGLE [5:1] RW value= 0x1 */
/* RESERVE25 [6:3] RSVD */
/* LOCKCNT [9:4] RW value= 0x8 */
/* RESERVE26 [13:4] RSVD */
/* ATEST_EN [17:1] RW value= 0x0 */
/* ATEST_SEL [18:3] RW value= 0x0 */
/* RESERVE27 [21:11] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_CAL)
/*PLL calibration register */
#define LIBERO_SETTING_SGMII_PLL_CAL 0x00000D06UL
/* DSKEWCALCNT [0:3] RW value= 0x6 */
/* DSKEWCAL_EN [3:1] RW value= 0x0 */
/* DSKEWCALBYP [4:1] RW value= 0x0 */
/* RESERVE28 [5:3] RSVD */
/* DSKEWCALIN [8:7] RW value= 0xd */
/* RESERVE29 [15:1] RSVD */
/* DSKEWCALOUT [16:7] RO */
/* RESERVE30 [23:9] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_PLL_PHADJ)
/*PLL phase registers */
#define LIBERO_SETTING_SGMII_PLL_PHADJ 0x00007443UL
/* PLL_REG_SYNCREFDIV_EN [0:1] RW value= 0x1 */
/* PLL_REG_ENABLE_SYNCREFDIV [1:1] RW value= 0x1 */
/* REG_OUT0_PHSINIT [2:3] RW value= 0x0 */
/* REG_OUT1_PHSINIT [5:3] RW value= 0x2 */
/* REG_OUT2_PHSINIT [8:3] RW value= 0x4 */
/* REG_OUT3_PHSINIT [11:3] RW value= 0x6 */
/* REG_LOADPHS_B [14:1] RW value= 0x1 */
/* RESERVE31 [15:17] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_SSCG_REG_0)
/*SSCG registers 0 */
#define LIBERO_SETTING_SGMII_SSCG_REG_0 0x00000000UL
/* DIVVAL [0:6] RW value= 0x0 */
/* FRACIN [6:24] RW value= 0x0 */
/* RESERVE00 [30:2] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_SSCG_REG_1)
/*SSCG registers 1 */
#define LIBERO_SETTING_SGMII_SSCG_REG_1 0x00000000UL
/* DOWNSPREAD [0:1] RW value= 0x0 */
/* SSMD [1:5] RW value= 0x0 */
/* FRACMOD [6:24] RO */
/* RESERVE01 [30:2] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_SSCG_REG_2)
/*SSCG registers 2 */
#define LIBERO_SETTING_SGMII_SSCG_REG_2 0x00000014UL
/* INTIN [0:12] RW value= 0x14 */
/* INTMOD [12:12] RO */
/* RESERVE02 [24:8] RSVD */
#endif
#if !defined (LIBERO_SETTING_SGMII_SSCG_REG_3)
/*SSCG registers 3 */
#define LIBERO_SETTING_SGMII_SSCG_REG_3 0x00000001UL
/* SSE_B [0:1] RW value= 0x1 */
/* SEL_EXTWAVE [1:2] RW value= 0x0 */
/* EXT_MAXADDR [3:8] RW value= 0x0 */
/* TBLADDR [11:8] RO */
/* RANDOM_FILTER [19:1] RW value= 0x0 */
/* RANDOM_SEL [20:2] RW value= 0x0 */
/* RESERVE03 [22:1] RSVD */
/* RESERVE04 [23:9] RSVD */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_CLK_SGMII_PLL_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_clk_sysreg.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_CLK_SYSREG_H_
#define HW_CLK_SYSREG_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_MSS_CLOCK_CONFIG_CR)
/*Master clock config (00=/1 01=/2 10=/4 11=/8 ) */
#define LIBERO_SETTING_MSS_CLOCK_CONFIG_CR 0x00000024UL
/* DIVIDER_CPU [0:2] RW value= 0x0 */
/* DIVIDER_AXI [2:2] RW value= 0x1 */
/* DIVIDER_APB_AHB [4:2] RW value= 0x2 */
#endif
#if !defined (LIBERO_SETTING_MSS_RTC_CLOCK_CR)
/*RTC clock divider */
#define LIBERO_SETTING_MSS_RTC_CLOCK_CR 0x0000007DUL
/* PERIOD [0:12] RW value= 0x7D */
#endif
#if !defined (LIBERO_SETTING_MSS_ENVM_CR)
/*ENVM AHB Controller setup - - Clock period = (Value+1) * (1000/AHBFREQMHZ)
e.g. 7 will generate a 40ns period 25MHz clock if the AHB clock is 200MHz */
#define LIBERO_SETTING_MSS_ENVM_CR 0x40050006UL
/* CLOCK_PERIOD [0:6] RW value= 0x6 */
/* CLOCK_CONTINUOUS [8:1] RW value= 0x0 */
/* CLOCK_SUPPRESS [9:1] RW value= 0x0 */
/* READAHEAD [16:1] RW value= 0x1 */
/* SLOWREAD [17:1] RW value= 0x0 */
/* INTERRUPT_ENABLE [18:1] RW value= 0x1 */
/* TIMER [24:8] RW value= 0x40 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_CLK_SYSREG_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mss_clks.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MSS_CLKS_H_
#define HW_MSS_CLKS_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_MSS_EXT_SGMII_REF_CLK)
/*Ref Clock rate in MHz */
#define LIBERO_SETTING_MSS_EXT_SGMII_REF_CLK 125000000
/* MSS_EXT_SGMII_REF_CLK [0:32] RW value= 125000000 */
#endif
#if !defined (LIBERO_SETTING_MSS_COREPLEX_CPU_CLK)
/*CPU Clock rate in MHz */
#define LIBERO_SETTING_MSS_COREPLEX_CPU_CLK 600000000
/* MSS_COREPLEX_CPU_CLK [0:32] RW value= 600000000 */
#endif
#if !defined (LIBERO_SETTING_MSS_SYSTEM_CLK)
/*System Clock rate in MHz static power. */
#define LIBERO_SETTING_MSS_SYSTEM_CLK 600000000
/* MSS_SYSTEM_CLK [0:32] RW value= 600000000 */
#endif
#if !defined (LIBERO_SETTING_MSS_RTC_TOGGLE_CLK)
/*RTC toggle Clock rate in MHz static power. */
#define LIBERO_SETTING_MSS_RTC_TOGGLE_CLK 1000000
/* MSS_RTC_TOGGLE_CLK [0:32] RW value= 1000000 */
#endif
#if !defined (LIBERO_SETTING_MSS_AXI_CLK)
/*AXI Clock rate in MHz static power. */
#define LIBERO_SETTING_MSS_AXI_CLK 300000000
/* MSS_AXI_CLK [0:32] RW value= 300000000 */
#endif
#if !defined (LIBERO_SETTING_MSS_APB_AHB_CLK)
/*AXI Clock rate in MHz static power. */
#define LIBERO_SETTING_MSS_APB_AHB_CLK 150000000
/* MSS_APB_AHB_CLK [0:32] RW value= 150000000 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MSS_CLKS_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_ddr_io_bank.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_DDR_IO_BANK_H_
#define HW_DDR_IO_BANK_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_DPC_BITS)
/*DPC Bits Register */
#define LIBERO_SETTING_DPC_BITS 0x0004C422UL
/* DPC_VS [0:4] RW value= 0x2 */
/* DPC_VRGEN_H [4:6] RW value= 0x2 */
/* DPC_VRGEN_EN_H [10:1] RW value= 0x1 */
/* DPC_MOVE_EN_H [11:1] RW value= 0x0 */
/* DPC_VRGEN_V [12:6] RW value= 0xC */
/* DPC_VRGEN_EN_V [18:1] RW value= 0x1 */
/* DPC_MOVE_EN_V [19:1] RW value= 0x0 */
/* RESERVE01 [20:12] RSVD */
#endif
#if !defined (LIBERO_SETTING_RPC_ODT_DQ)
/*Need to be set by software in all modes but OFF mode. Decoding options should
follow ODT_STR table, depends on drive STR setting */
#define LIBERO_SETTING_RPC_ODT_DQ 0x00000006UL
/* RPC_ODT_DQ [0:32] RW value= 0x6 */
#endif
#if !defined (LIBERO_SETTING_RPC_ODT_DQS)
/*Need to be set by software in all modes but OFF mode. Decoding options should
follow ODT_STR table, depends on drive STR setting */
#define LIBERO_SETTING_RPC_ODT_DQS 0x00000006UL
/* RPC_ODT_DQS [0:32] RW value= 0x6 */
#endif
#if !defined (LIBERO_SETTING_RPC_ODT_ADDCMD)
/*Need to be set by software in all modes but OFF mode. Decoding options should
follow ODT_STR table, depends on drive STR setting */
#define LIBERO_SETTING_RPC_ODT_ADDCMD 0x00000002UL
/* RPC_ODT_ADDCMD [0:32] RW value= 0x2 */
#endif
#if !defined (LIBERO_SETTING_RPC_ODT_CLK)
/*Need to be set by software in all modes but OFF mode. Decoding options should
follow ODT_STR table, depends on drive STR setting */
#define LIBERO_SETTING_RPC_ODT_CLK 0x00000002UL
/* RPC_ODT_CLK [0:32] RW value= 0x2 */
#endif
#if !defined (LIBERO_SETTING_RPC_ODT_STATIC_DQ)
/*0x2000 73A8 (rpc10_ODT) */
#define LIBERO_SETTING_RPC_ODT_STATIC_DQ 0x00000005UL
/* RPC_ODT_STATIC_DQ [0:32] RW value= 0x5 */
#endif
#if !defined (LIBERO_SETTING_RPC_ODT_STATIC_DQS)
/*0x2000 73AC (rpc11_ODT) */
#define LIBERO_SETTING_RPC_ODT_STATIC_DQS 0x00000005UL
/* RPC_ODT_STATIC_DQS [0:32] RW value= 0x5 */
#endif
#if !defined (LIBERO_SETTING_RPC_ODT_STATIC_ADDCMD)
/*0x2000 739C (rpc7_ODT) */
#define LIBERO_SETTING_RPC_ODT_STATIC_ADDCMD 0x00000007UL
/* RPC_ODT_STATIC_ADDCMD [0:32] RW value= 0x7 */
#endif
#if !defined (LIBERO_SETTING_RPC_ODT_STATIC_CLKP)
/*0x2000 73A4 (rpc9_ODT) */
#define LIBERO_SETTING_RPC_ODT_STATIC_CLKP 0x00000007UL
/* RPC_ODT_STATIC_CLKP [0:32] RW value= 0x7 */
#endif
#if !defined (LIBERO_SETTING_RPC_ODT_STATIC_CLKN)
/*0x2000 73A0 (rpc8_ODT) */
#define LIBERO_SETTING_RPC_ODT_STATIC_CLKN 0x00000007UL
/* RPC_ODT_STATIC_CLKN [0:32] RW value= 0x7 */
#endif
#if !defined (LIBERO_SETTING_RPC_IBUFMD_ADDCMD)
/*0x2000 757C (rpc95) */
#define LIBERO_SETTING_RPC_IBUFMD_ADDCMD 0x00000003UL
/* RPC_IBUFMD_ADDCMD [0:32] RW value= 0x3 */
#endif
#if !defined (LIBERO_SETTING_RPC_IBUFMD_CLK)
/*0x2000 7580 (rpc96) */
#define LIBERO_SETTING_RPC_IBUFMD_CLK 0x00000004UL
/* RPC_IBUFMD_CLK [0:32] RW value= 0x4 */
#endif
#if !defined (LIBERO_SETTING_RPC_IBUFMD_DQ)
/*0x2000 7584 (rpc97) */
#define LIBERO_SETTING_RPC_IBUFMD_DQ 0x00000003UL
/* RPC_IBUFMD_DQ [0:32] RW value= 0x3 */
#endif
#if !defined (LIBERO_SETTING_RPC_IBUFMD_DQS)
/*0x2000 7588 (rpc98) */
#define LIBERO_SETTING_RPC_IBUFMD_DQS 0x00000004UL
/* RPC_IBUFMD_DQS [0:32] RW value= 0x4 */
#endif
#if !defined (LIBERO_SETTING_RPC_SPARE0_DQ)
/*bits 15:14 connect to pc_ibufmx DQ/DQS/DM bits 13:12 connect to pc_ibufmx
CA/CK Check at ioa pc bit */
#define LIBERO_SETTING_RPC_SPARE0_DQ 0x00008000UL
/* RPC_SPARE0_DQ [0:32] RW value= 0x8000 */
#endif
#if !defined (LIBERO_SETTING_RPC_EN_ADDCMD0_OVRT9)
/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding
to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC_EN_ADDCMD0_OVRT9 0x00000F00UL
/* MSS_DDR_CK0 [0:1] RW value= 0x0 */
/* MSS_DDR_CK_N0 [1:1] RW value= 0x0 */
/* MSS_DDR_A0 [2:1] RW value= 0x0 */
/* MSS_DDR_A1 [3:1] RW value= 0x0 */
/* MSS_DDR_A2 [4:1] RW value= 0x0 */
/* MSS_DDR_A3 [5:1] RW value= 0x0 */
/* MSS_DDR_A4 [6:1] RW value= 0x0 */
/* MSS_DDR_A5 [7:1] RW value= 0x0 */
/* MSS_DDR_A6 [8:1] RW value= 0x1 */
/* MSS_DDR_A7 [9:1] RW value= 0x1 */
/* MSS_DDR_A8 [10:1] RW value= 0x1 */
/* MSS_DDR_A9 [11:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10)
/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding
to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10 0x00000FFFUL
/* MSS_DDR_CK1 [0:1] RW value= 0x1 */
/* MSS_DDR_CK_N1 [1:1] RW value= 0x1 */
/* MSS_DDR_A10 [2:1] RW value= 0x1 */
/* MSS_DDR_A11 [3:1] RW value= 0x1 */
/* MSS_DDR_A12 [4:1] RW value= 0x1 */
/* MSS_DDR_A13 [5:1] RW value= 0x1 */
/* MSS_DDR_A14 [6:1] RW value= 0x1 */
/* MSS_DDR_A15 [7:1] RW value= 0x1 */
/* MSS_DDR_A16 [8:1] RW value= 0x1 */
/* MSS_DDR3_WE_N [9:1] RW value= 0x1 */
/* MSS_DDR_BA0 [10:1] RW value= 0x1 */
/* MSS_DDR_BA1 [11:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11)
/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding
to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11 0x00000FE6UL
/* MSS_DDR_RAM_RST_N [0:1] RW value= 0x0 */
/* MSS_DDR_BG0 [1:1] RW value= 0x1 */
/* MSS_DDR_BG1 [2:1] RW value= 0x1 */
/* MSS_DDR_CS0 [3:1] RW value= 0x0 */
/* MSS_DDR_CKE0 [4:1] RW value= 0x0 */
/* MSS_DDR_ODT0 [5:1] RW value= 0x1 */
/* MSS_DDR_CS1 [6:1] RW value= 0x1 */
/* MSS_DDR_CKE1 [7:1] RW value= 0x1 */
/* MSS_DDR_ODT1 [8:1] RW value= 0x1 */
/* MSS_DDR_ACT_N [9:1] RW value= 0x1 */
/* MSS_DDR_PARITY [10:1] RW value= 0x1 */
/* MSS_DDR_ALERT_N [11:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC_EN_DATA0_OVRT12)
/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding
to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC_EN_DATA0_OVRT12 0x00000000UL
/* MSS_DDR_DQ0 [0:1] RW value= 0x0 */
/* MSS_DDR_DQ1 [1:1] RW value= 0x0 */
/* MSS_DDR_DQ2 [2:1] RW value= 0x0 */
/* MSS_DDR_DQ3 [3:1] RW value= 0x0 */
/* MSS_DDR_DQS_P0 [4:1] RW value= 0x0 */
/* MSS_DDR_DQS_N0 [5:1] RW value= 0x0 */
/* MSS_DDR_DQ4 [6:1] RW value= 0x0 */
/* MSS_DDR_DQ5 [7:1] RW value= 0x0 */
/* MSS_DDR_DQ6 [8:1] RW value= 0x0 */
/* MSS_DDR_DQ7 [9:1] RW value= 0x0 */
/* MSS_DDR_DM0 [10:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC_EN_DATA1_OVRT13)
/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding
to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC_EN_DATA1_OVRT13 0x00000000UL
/* MSS_DDR_DQ8 [0:1] RW value= 0x0 */
/* MSS_DDR_DQ9 [1:1] RW value= 0x0 */
/* MSS_DDR_DQ10 [2:1] RW value= 0x0 */
/* MSS_DDR_DQ11 [3:1] RW value= 0x0 */
/* MSS_DDR_DQS_P1 [4:1] RW value= 0x0 */
/* MSS_DDR_DQS_N1 [5:1] RW value= 0x0 */
/* MSS_DDR_DQ12 [6:1] RW value= 0x0 */
/* MSS_DDR_DQ13 [7:1] RW value= 0x0 */
/* MSS_DDR_DQ14 [8:1] RW value= 0x0 */
/* MSS_DDR_DQ15 [9:1] RW value= 0x0 */
/* MSS_DDR_DM1 [10:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC_EN_DATA2_OVRT14)
/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding
to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC_EN_DATA2_OVRT14 0x00000000UL
/* MSS_DDR_DQ16 [0:1] RW value= 0x0 */
/* MSS_DDR_DQ17 [1:1] RW value= 0x0 */
/* MSS_DDR_DQ18 [2:1] RW value= 0x0 */
/* MSS_DDR_DQ19 [3:1] RW value= 0x0 */
/* MSS_DDR_DQS_P2 [4:1] RW value= 0x0 */
/* MSS_DDR_DQS_N2 [5:1] RW value= 0x0 */
/* MSS_DDR_DQ20 [6:1] RW value= 0x0 */
/* MSS_DDR_DQ21 [7:1] RW value= 0x0 */
/* MSS_DDR_DQ22 [8:1] RW value= 0x0 */
/* MSS_DDR_DQ23 [9:1] RW value= 0x0 */
/* MSS_DDR_DM2 [10:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC_EN_DATA3_OVRT15)
/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding
to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC_EN_DATA3_OVRT15 0x00000000UL
/* MSS_DDR_DQ24 [0:1] RW value= 0x0 */
/* MSS_DDR_DQ25 [1:1] RW value= 0x0 */
/* MSS_DDR_DQ26 [2:1] RW value= 0x0 */
/* MSS_DDR_DQ27 [3:1] RW value= 0x0 */
/* MSS_DDR_DQS_P3 [4:1] RW value= 0x0 */
/* MSS_DDR_DQS_N3 [5:1] RW value= 0x0 */
/* MSS_DDR_DQ28 [6:1] RW value= 0x0 */
/* MSS_DDR_DQ29 [7:1] RW value= 0x0 */
/* MSS_DDR_DQ30 [8:1] RW value= 0x0 */
/* MSS_DDR_DQ31 [9:1] RW value= 0x0 */
/* MSS_DDR_DM3 [10:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC_EN_ECC_OVRT16)
/*Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding
to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC_EN_ECC_OVRT16 0x0000007FUL
/* MSS_DDR_DQ32 [0:1] RW value= 0x1 */
/* MSS_DDR_DQ33 [1:1] RW value= 0x1 */
/* MSS_DDR_DQ34 [2:1] RW value= 0x1 */
/* MSS_DDR_DQ35 [3:1] RW value= 0x1 */
/* MSS_DDR_DQS_P4 [4:1] RW value= 0x1 */
/* MSS_DDR_DQS_N4 [5:1] RW value= 0x1 */
/* MSS_DDR_DM4 [6:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC235_WPD_ADD_CMD0)
/*Sets pull-downs when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC235_WPD_ADD_CMD0 0x00000000UL
/* MSS_DDR_CK0 [0:1] RW value= 0x0 */
/* MSS_DDR_CK_N0 [1:1] RW value= 0x0 */
/* MSS_DDR_A0 [2:1] RW value= 0x0 */
/* MSS_DDR_A1 [3:1] RW value= 0x0 */
/* MSS_DDR_A2 [4:1] RW value= 0x0 */
/* MSS_DDR_A3 [5:1] RW value= 0x0 */
/* MSS_DDR_A4 [6:1] RW value= 0x0 */
/* MSS_DDR_A5 [7:1] RW value= 0x0 */
/* MSS_DDR_A6 [8:1] RW value= 0x0 */
/* MSS_DDR_A7 [9:1] RW value= 0x0 */
/* MSS_DDR_A8 [10:1] RW value= 0x0 */
/* MSS_DDR_A9 [11:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC236_WPD_ADD_CMD1)
/*Sets pull-downs when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC236_WPD_ADD_CMD1 0x00000000UL
/* MSS_DDR_CK1 [0:1] RW value= 0x0 */
/* MSS_DDR_CK_N1 [1:1] RW value= 0x0 */
/* MSS_DDR_A10 [2:1] RW value= 0x0 */
/* MSS_DDR_A11 [3:1] RW value= 0x0 */
/* MSS_DDR_A12 [4:1] RW value= 0x0 */
/* MSS_DDR_A13 [5:1] RW value= 0x0 */
/* MSS_DDR_A14 [6:1] RW value= 0x0 */
/* MSS_DDR_A15 [7:1] RW value= 0x0 */
/* MSS_DDR_A16 [8:1] RW value= 0x0 */
/* MSS_DDR3_WE_N [9:1] RW value= 0x0 */
/* MSS_DDR_BA0 [10:1] RW value= 0x0 */
/* MSS_DDR_BA1 [11:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC237_WPD_ADD_CMD2)
/*Sets pull-downs when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. Note: For LPDDR4 need
to over-ride MSS_DDR_ODT0 and MSS_DDR_ODT1 and eanble PU i.e. (set OVR_EN ==1 ,
wpu == 0 , wpd == 1 ) */
#define LIBERO_SETTING_RPC237_WPD_ADD_CMD2 0x00000120UL
/* MSS_DDR_RAM_RST_N [0:1] RW value= 0x0 */
/* MSS_DDR_BG0 [1:1] RW value= 0x0 */
/* MSS_DDR_BG1 [2:1] RW value= 0x0 */
/* MSS_DDR_CS0 [3:1] RW value= 0x0 */
/* MSS_DDR_CKE0 [4:1] RW value= 0x0 */
/* MSS_DDR_ODT0 [5:1] RW value= 0x1 */
/* MSS_DDR_CS1 [6:1] RW value= 0x0 */
/* MSS_DDR_CKE1 [7:1] RW value= 0x0 */
/* MSS_DDR_ODT1 [8:1] RW value= 0x1 */
/* MSS_DDR_ACT_N [9:1] RW value= 0x0 */
/* MSS_DDR_PARITY [10:1] RW value= 0x0 */
/* MSS_DDR_ALERT_N [11:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC238_WPD_DATA0)
/*Sets pull-downs when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC238_WPD_DATA0 0x00000000UL
/* MSS_DDR_DQ0 [0:1] RW value= 0x0 */
/* MSS_DDR_DQ1 [1:1] RW value= 0x0 */
/* MSS_DDR_DQ2 [2:1] RW value= 0x0 */
/* MSS_DDR_DQ3 [3:1] RW value= 0x0 */
/* MSS_DDR_DQS_P0 [4:1] RW value= 0x0 */
/* MSS_DDR_DQS_N0 [5:1] RW value= 0x0 */
/* MSS_DDR_DQ4 [6:1] RW value= 0x0 */
/* MSS_DDR_DQ5 [7:1] RW value= 0x0 */
/* MSS_DDR_DQ6 [8:1] RW value= 0x0 */
/* MSS_DDR_DQ7 [9:1] RW value= 0x0 */
/* MSS_DDR_DM0 [10:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC239_WPD_DATA1)
/*Sets pull-downs when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC239_WPD_DATA1 0x00000000UL
/* MSS_DDR_DQ8 [0:1] RW value= 0x0 */
/* MSS_DDR_DQ9 [1:1] RW value= 0x0 */
/* MSS_DDR_DQ10 [2:1] RW value= 0x0 */
/* MSS_DDR_DQ11 [3:1] RW value= 0x0 */
/* MSS_DDR_DQS_P1 [4:1] RW value= 0x0 */
/* MSS_DDR_DQS_N1 [5:1] RW value= 0x0 */
/* MSS_DDR_DQ12 [6:1] RW value= 0x0 */
/* MSS_DDR_DQ13 [7:1] RW value= 0x0 */
/* MSS_DDR_DQ14 [8:1] RW value= 0x0 */
/* MSS_DDR_DQ15 [9:1] RW value= 0x0 */
/* MSS_DDR_DM1 [10:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC240_WPD_DATA2)
/*Sets pull-downs when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC240_WPD_DATA2 0x00000000UL
/* MSS_DDR_DQ16 [0:1] RW value= 0x0 */
/* MSS_DDR_DQ17 [1:1] RW value= 0x0 */
/* MSS_DDR_DQ18 [2:1] RW value= 0x0 */
/* MSS_DDR_DQ19 [3:1] RW value= 0x0 */
/* MSS_DDR_DQS_P2 [4:1] RW value= 0x0 */
/* MSS_DDR_DQS_N2 [5:1] RW value= 0x0 */
/* MSS_DDR_DQ20 [6:1] RW value= 0x0 */
/* MSS_DDR_DQ21 [7:1] RW value= 0x0 */
/* MSS_DDR_DQ22 [8:1] RW value= 0x0 */
/* MSS_DDR_DQ23 [9:1] RW value= 0x0 */
/* MSS_DDR_DM2 [10:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC241_WPD_DATA3)
/*Sets pull-downs when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC241_WPD_DATA3 0x00000000UL
/* MSS_DDR_DQ24 [0:1] RW value= 0x0 */
/* MSS_DDR_DQ25 [1:1] RW value= 0x0 */
/* MSS_DDR_DQ26 [2:1] RW value= 0x0 */
/* MSS_DDR_DQ27 [3:1] RW value= 0x0 */
/* MSS_DDR_DQS_P3 [4:1] RW value= 0x0 */
/* MSS_DDR_DQS_N3 [5:1] RW value= 0x0 */
/* MSS_DDR_DQ28 [6:1] RW value= 0x0 */
/* MSS_DDR_DQ29 [7:1] RW value= 0x0 */
/* MSS_DDR_DQ30 [8:1] RW value= 0x0 */
/* MSS_DDR_DQ31 [9:1] RW value= 0x0 */
/* MSS_DDR_DM3 [10:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC242_WPD_ECC)
/*Sets pull-downs when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC242_WPD_ECC 0x00000000UL
/* MSS_DDR_DQ32 [0:1] RW value= 0x0 */
/* MSS_DDR_DQ33 [1:1] RW value= 0x0 */
/* MSS_DDR_DQ34 [2:1] RW value= 0x0 */
/* MSS_DDR_DQ35 [3:1] RW value= 0x0 */
/* MSS_DDR_DQS_P4 [4:1] RW value= 0x0 */
/* MSS_DDR_DQS_N4 [5:1] RW value= 0x0 */
/* MSS_DDR_DM4 [6:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RPC243_WPU_ADD_CMD0)
/*Sets pull-ups when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC243_WPU_ADD_CMD0 0x00000FFFUL
/* MSS_DDR_CK0 [0:1] RW value= 0x1 */
/* MSS_DDR_CK_N0 [1:1] RW value= 0x1 */
/* MSS_DDR_A0 [2:1] RW value= 0x1 */
/* MSS_DDR_A1 [3:1] RW value= 0x1 */
/* MSS_DDR_A2 [4:1] RW value= 0x1 */
/* MSS_DDR_A3 [5:1] RW value= 0x1 */
/* MSS_DDR_A4 [6:1] RW value= 0x1 */
/* MSS_DDR_A5 [7:1] RW value= 0x1 */
/* MSS_DDR_A6 [8:1] RW value= 0x1 */
/* MSS_DDR_A7 [9:1] RW value= 0x1 */
/* MSS_DDR_A8 [10:1] RW value= 0x1 */
/* MSS_DDR_A9 [11:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC244_WPU_ADD_CMD1)
/*Sets pull-ups when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC244_WPU_ADD_CMD1 0x00000FFFUL
/* MSS_DDR_CK1 [0:1] RW value= 0x1 */
/* MSS_DDR_CK_N1 [1:1] RW value= 0x1 */
/* MSS_DDR_A10 [2:1] RW value= 0x1 */
/* MSS_DDR_A11 [3:1] RW value= 0x1 */
/* MSS_DDR_A12 [4:1] RW value= 0x1 */
/* MSS_DDR_A13 [5:1] RW value= 0x1 */
/* MSS_DDR_A14 [6:1] RW value= 0x1 */
/* MSS_DDR_A15 [7:1] RW value= 0x1 */
/* MSS_DDR_A16 [8:1] RW value= 0x1 */
/* MSS_DDR3_WE_N [9:1] RW value= 0x1 */
/* MSS_DDR_BA0 [10:1] RW value= 0x1 */
/* MSS_DDR_BA1 [11:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC245_WPU_ADD_CMD2)
/*Sets pull-ups when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC245_WPU_ADD_CMD2 0x00000EDFUL
/* MSS_DDR_RAM_RST_N [0:1] RW value= 0x1 */
/* MSS_DDR_BG0 [1:1] RW value= 0x1 */
/* MSS_DDR_BG1 [2:1] RW value= 0x1 */
/* MSS_DDR_CS0 [3:1] RW value= 0x1 */
/* MSS_DDR_CKE0 [4:1] RW value= 0x1 */
/* MSS_DDR_ODT0 [5:1] RW value= 0x0 */
/* MSS_DDR_CS1 [6:1] RW value= 0x1 */
/* MSS_DDR_CKE1 [7:1] RW value= 0x1 */
/* MSS_DDR_ODT1 [8:1] RW value= 0x0 */
/* MSS_DDR_ACT_N [9:1] RW value= 0x1 */
/* MSS_DDR_PARITY [10:1] RW value= 0x1 */
/* MSS_DDR_ALERT_N [11:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC246_WPU_DATA0)
/*Sets pull-ups when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC246_WPU_DATA0 0x000007FFUL
/* MSS_DDR_DQ0 [0:1] RW value= 0x1 */
/* MSS_DDR_DQ1 [1:1] RW value= 0x1 */
/* MSS_DDR_DQ2 [2:1] RW value= 0x1 */
/* MSS_DDR_DQ3 [3:1] RW value= 0x1 */
/* MSS_DDR_DQS_P0 [4:1] RW value= 0x1 */
/* MSS_DDR_DQS_N0 [5:1] RW value= 0x1 */
/* MSS_DDR_DQ4 [6:1] RW value= 0x1 */
/* MSS_DDR_DQ5 [7:1] RW value= 0x1 */
/* MSS_DDR_DQ6 [8:1] RW value= 0x1 */
/* MSS_DDR_DQ7 [9:1] RW value= 0x1 */
/* MSS_DDR_DM0 [10:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC247_WPU_DATA1)
/*Sets pull-ups when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC247_WPU_DATA1 0x000007FFUL
/* MSS_DDR_DQ8 [0:1] RW value= 0x1 */
/* MSS_DDR_DQ9 [1:1] RW value= 0x1 */
/* MSS_DDR_DQ10 [2:1] RW value= 0x1 */
/* MSS_DDR_DQ11 [3:1] RW value= 0x1 */
/* MSS_DDR_DQS_P1 [4:1] RW value= 0x1 */
/* MSS_DDR_DQS_N1 [5:1] RW value= 0x1 */
/* MSS_DDR_DQ12 [6:1] RW value= 0x1 */
/* MSS_DDR_DQ13 [7:1] RW value= 0x1 */
/* MSS_DDR_DQ14 [8:1] RW value= 0x1 */
/* MSS_DDR_DQ15 [9:1] RW value= 0x1 */
/* MSS_DDR_DM1 [10:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC248_WPU_DATA2)
/*Sets pull-ups when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC248_WPU_DATA2 0x000007FFUL
/* MSS_DDR_DQ16 [0:1] RW value= 0x1 */
/* MSS_DDR_DQ17 [1:1] RW value= 0x1 */
/* MSS_DDR_DQ18 [2:1] RW value= 0x1 */
/* MSS_DDR_DQ19 [3:1] RW value= 0x1 */
/* MSS_DDR_DQS_P2 [4:1] RW value= 0x1 */
/* MSS_DDR_DQS_N2 [5:1] RW value= 0x1 */
/* MSS_DDR_DQ20 [6:1] RW value= 0x1 */
/* MSS_DDR_DQ21 [7:1] RW value= 0x1 */
/* MSS_DDR_DQ22 [8:1] RW value= 0x1 */
/* MSS_DDR_DQ23 [9:1] RW value= 0x1 */
/* MSS_DDR_DM2 [10:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC249_WPU_DATA3)
/*Sets pull-ups when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC249_WPU_DATA3 0x000007FFUL
/* MSS_DDR_DQ24 [0:1] RW value= 0x1 */
/* MSS_DDR_DQ25 [1:1] RW value= 0x1 */
/* MSS_DDR_DQ26 [2:1] RW value= 0x1 */
/* MSS_DDR_DQ27 [3:1] RW value= 0x1 */
/* MSS_DDR_DQS_P3 [4:1] RW value= 0x1 */
/* MSS_DDR_DQS_N3 [5:1] RW value= 0x1 */
/* MSS_DDR_DQ28 [6:1] RW value= 0x1 */
/* MSS_DDR_DQ29 [7:1] RW value= 0x1 */
/* MSS_DDR_DQ30 [8:1] RW value= 0x1 */
/* MSS_DDR_DQ31 [9:1] RW value= 0x1 */
/* MSS_DDR_DM3 [10:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_RPC250_WPU_ECC)
/*Sets pull-ups when override enabled. Each bit corresponding to an IO in
corresponding IOG lane, starting from p_pair0 to n_pair5. */
#define LIBERO_SETTING_RPC250_WPU_ECC 0x0000007FUL
/* MSS_DDR_DQ32 [0:1] RW value= 0x1 */
/* MSS_DDR_DQ33 [1:1] RW value= 0x1 */
/* MSS_DDR_DQ34 [2:1] RW value= 0x1 */
/* MSS_DDR_DQ35 [3:1] RW value= 0x1 */
/* MSS_DDR_DQS_P4 [4:1] RW value= 0x1 */
/* MSS_DDR_DQS_N4 [5:1] RW value= 0x1 */
/* MSS_DDR_DM4 [6:1] RW value= 0x1 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_DDR_IO_BANK_H_ */

69
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@ -0,0 +1,69 @@
/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_ddr_mode.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_DDR_MODE_H_
#define HW_DDR_MODE_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_DDRPHY_MODE)
/*DDRPHY MODE (binary)- 000 ddr3, 001 ddr33L, 010 ddr4, 011 LPDDR3, 100 LPDDR4,
111 OFF_MODE */
#define LIBERO_SETTING_DDRPHY_MODE 0x00014B24UL
/* DDRMODE [0:3] RW value= 0x4 */
/* ECC [3:1] RW value= 0x0 */
/* CRC [4:1] RW value= 0x0 */
/* BUS_WIDTH [5:3] RW value= 0x1 */
/* DMI_DBI [8:1] RW value= 0x1 */
/* DQ_DRIVE [9:2] RW value= 0x1 */
/* DQS_DRIVE [11:2] RW value= 0x1 */
/* ADD_CMD_DRIVE [13:2] RW value= 0x2 */
/* CLOCK_OUT_DRIVE [15:2] RW value= 0x2 */
/* DQ_TERMINATION [17:2] RW value= 0x0 */
/* DQS_TERMINATION [19:2] RW value= 0x0 */
/* ADD_CMD_INPUT_PIN_TERMINATION [21:2] RW value= 0x0 */
/* PRESET_ODT_CLK [23:2] RW value= 0x0 */
/* POWER_DOWN [25:1] RW value= 0x0 */
/* RANK [26:1] RW value= 0x0 */
/* RESERVED [27:5] RSVD */
#endif
#if !defined (LIBERO_SETTING_DATA_LANES_USED)
/*number of lanes used for data- does not include ECC, infer from mode register
*/
#define LIBERO_SETTING_DATA_LANES_USED 0x00000004UL
/* DATA_LANES [0:3] RW value= 0x4 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_DDR_MODE_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_ddr_off_mode.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_DDR_OFF_MODE_H_
#define HW_DDR_OFF_MODE_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_DDRPHY_MODE_OFF)
/*DDRPHY MODE Register, ddr off */
#define LIBERO_SETTING_DDRPHY_MODE_OFF 0x00000000UL
/* DDRMODE [0:3] RW value= 0x0 */
/* ECC [3:1] RW value= 0x0 */
/* CRC [4:1] RW value= 0x0 */
/* BUS_WIDTH [5:3] RW value= 0x0 */
/* DMI_DBI [8:1] RW value= 0x0 */
/* DQ_DRIVE [9:2] RW value= 0x0 */
/* DQS_DRIVE [11:2] RW value= 0x0 */
/* ADD_CMD_DRIVE [13:2] RW value= 0x0 */
/* CLOCK_OUT_DRIVE [15:2] RW value= 0x0 */
/* DQ_TERMINATION [17:2] RW value= 0x0 */
/* DQS_TERMINATION [19:2] RW value= 0x0 */
/* ADD_CMD_INPUT_PIN_TERMINATION [21:2] RW value= 0x0 */
/* PRESET_ODT_CLK [23:2] RW value= 0x0 */
/* POWER_DOWN [25:1] RW value= 0x0 */
/* RANK [26:1] RW value= 0x0 */
/* RESERVED [27:5] RSVD */
#endif
#if !defined (LIBERO_SETTING_DPC_BITS_OFF_MODE)
/*DPC Bits Register off mode */
#define LIBERO_SETTING_DPC_BITS_OFF_MODE 0x00000000UL
/* DPC_VS [0:4] RW value= 0x0 */
/* DPC_VRGEN_H [4:6] RW value= 0x0 */
/* DPC_VRGEN_EN_H [10:1] RW value= 0x0 */
/* DPC_MOVE_EN_H [11:1] RW value= 0x0 */
/* DPC_VRGEN_V [12:6] RW value= 0x0 */
/* DPC_VRGEN_EN_V [18:1] RW value= 0x0 */
/* DPC_MOVE_EN_V [19:1] RW value= 0x0 */
/* RESERVE01 [20:12] RSVD */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_DDR_OFF_MODE_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_ddr_options.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_DDR_OPTIONS_H_
#define HW_DDR_OPTIONS_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_CA_BUS_RX_OFF_POST_TRAINING)
/*Tip config: Referenced receivers in the CA bus are turned on for CA training.
These burn static power.(0x01 => turn off ; 0x00 => no action ) */
#define LIBERO_SETTING_CA_BUS_RX_OFF_POST_TRAINING 0x00000001UL
/* CA_BUS_RX_OFF_POST_TRAINING [0:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_USER_INPUT_PHY_RANKS_TO_TRAIN)
/*Tip config: 1 => 1 rank, 3 => 2 ranks */
#define LIBERO_SETTING_USER_INPUT_PHY_RANKS_TO_TRAIN 0x00000001UL
/* USER_INPUT_PHY_RANKS_TO_TRAIN [0:2] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_TRAINING_SKIP_SETTING)
/*Tip config: Pick what trainings we want performed by the TIP, default is 0x1F
*/
#define LIBERO_SETTING_TRAINING_SKIP_SETTING 0x00000002UL
/* SKIP_BCLKSCLK_TIP_TRAINING [0:1] RW value= 0x0 */
/* SKIP_ADDCMD_TIP_TRAINING [1:1] RW value= 0x1 */
/* SKIP_WRLVL_TIP_TRAINING [2:1] RW value= 0x0 */
/* SKIP_RDGATE_TIP_TRAINING [3:1] RW value= 0x0 */
/* SKIP_DQ_DQS_OPT_TIP_TRAINING [4:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_TIP_CFG_PARAMS)
/*Tip config: default: 0x2,0x4,0x0,0x1F,0x1F */
#define LIBERO_SETTING_TIP_CFG_PARAMS 0x07CFE02AUL
/* ADDCMD_OFFSET [0:3] RW value= 0x2 */
/* BCKLSCLK_OFFSET [3:3] RW value= 0x5 */
/* WRCALIB_WRITE_COUNT [6:7] RW value= 0x0 */
/* READ_GATE_MIN_READS [13:8] RW value= 0x7F */
/* ADDRCMD_WAIT_COUNT [22:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_TIP_CONFIG_PARAMS_BCLK_VCOPHS_OFFSET)
/*in simulation we need to set this to 2, for hardware it will be dependent on
the trace lengths */
#define LIBERO_SETTING_TIP_CONFIG_PARAMS_BCLK_VCOPHS_OFFSET 0x00000002UL
/* TIP_CONFIG_PARAMS_BCLK_VCOPHS [0:32] RW value= 0x02 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_DDR_OPTIONS_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_ddr_segs.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_DDR_SEGS_H_
#define HW_DDR_SEGS_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_SEG0_0)
/*Cached access at 0x00_8000_0000 (-0x80+0x00) */
#define LIBERO_SETTING_SEG0_0 0x80007F80UL
/* ADDRESS_OFFSET [0:15] RW value= 0x7F80 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_SEG0_1)
/*Cached access at 0x10_0000_000 */
#define LIBERO_SETTING_SEG0_1 0x80007030UL
/* ADDRESS_OFFSET [0:15] RW value= 0x7030 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_SEG0_2)
/*not used */
#define LIBERO_SETTING_SEG0_2 0x00000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SEG0_3)
/*not used */
#define LIBERO_SETTING_SEG0_3 0x00000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SEG0_4)
/*not used */
#define LIBERO_SETTING_SEG0_4 0x00000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SEG0_5)
/*not used */
#define LIBERO_SETTING_SEG0_5 0x00000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:6] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SEG0_6)
/*not used */
#define LIBERO_SETTING_SEG0_6 0x00000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SEG0_7)
/*not used */
#define LIBERO_SETTING_SEG0_7 0x00000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SEG1_0)
/*not used */
#define LIBERO_SETTING_SEG1_0 0x00000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SEG1_1)
/*not used */
#define LIBERO_SETTING_SEG1_1 0x00000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SEG1_2)
/*Non-Cached access at 0x00_c000_0000 */
#define LIBERO_SETTING_SEG1_2 0x80007FB0UL
/* ADDRESS_OFFSET [0:15] RW value= 0x7FB0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_SEG1_3)
/*Non-Cached access at 0x14_0000_0000 */
#define LIBERO_SETTING_SEG1_3 0x80000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_SEG1_4)
/*Non-Cached WCB access at 0x00_d000_0000 */
#define LIBERO_SETTING_SEG1_4 0x80007FA0UL
/* ADDRESS_OFFSET [0:15] RW value= 0x7FA0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_SEG1_5)
/*Non-Cached WCB 0x18_0000_0000 */
#define LIBERO_SETTING_SEG1_5 0x80000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:6] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_SEG1_6)
/*Trace - Trace not in use here so can be left as 0 */
#define LIBERO_SETTING_SEG1_6 0x00000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SEG1_7)
/*not used */
#define LIBERO_SETTING_SEG1_7 0x00000000UL
/* ADDRESS_OFFSET [0:15] RW value= 0x0 */
/* RESERVED [15:16] RW value= 0x0 */
/* LOCKED [31:1] RW value= 0x0 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_DDR_SEGS_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file fpga_design_config.h
* @author Embedded Software
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef FPGA_DESIGN_CONFIG_H_
#define FPGA_DESIGN_CONFIG_H_
#define LIBERO_SETTING_MSS_CONFIGURATOR_VERSION "2021.1"
#define LIBERO_SETTING_DESIGN_NAME "ICICLE_MSS"
#define LIBERO_SETTING_MPFS_PART "MPFS250T_ES"
#define LIBERO_SETTING_GENERATION_DATE "04-11-2021_22:30:25"
#define LIBERO_SETTING_XML_VERSION "0.5.3"
#define LIBERO_SETTING_XML_VERSION_MAJOR 0
#define LIBERO_SETTING_XML_VERSION_MINOR 5
#define LIBERO_SETTING_XML_VERSION_PATCH 3
#define LIBERO_SETTING_HEADER_GENERATOR_VERSION "0.6.3"
#define LIBERO_SETTING_HEADER_GENERATOR_VERSION_MAJOR 0
#define LIBERO_SETTING_HEADER_GENERATOR_VERSION_MINOR 6
#define LIBERO_SETTING_HEADER_GENERATOR_VERSION_PATCH 3
#include "memory_map/hw_memory.h"
#include "memory_map/hw_apb_split.h"
#include "memory_map/hw_cache.h"
#include "memory_map/hw_pmp_hart0.h"
#include "memory_map/hw_pmp_hart1.h"
#include "memory_map/hw_pmp_hart2.h"
#include "memory_map/hw_pmp_hart3.h"
#include "memory_map/hw_pmp_hart4.h"
#include "memory_map/hw_mpu_fic0.h"
#include "memory_map/hw_mpu_fic1.h"
#include "memory_map/hw_mpu_fic2.h"
#include "memory_map/hw_mpu_crypto.h"
#include "memory_map/hw_mpu_gem0.h"
#include "memory_map/hw_mpu_gem1.h"
#include "memory_map/hw_mpu_usb.h"
#include "memory_map/hw_mpu_mmc.h"
#include "memory_map/hw_mpu_scb.h"
#include "memory_map/hw_mpu_trace.h"
#include "io/hw_mssio_mux.h"
#include "io/hw_hsio_mux.h"
#include "sgmii/hw_sgmii_tip.h"
#include "ddr/hw_ddr_options.h"
#include "ddr/hw_ddr_io_bank.h"
#include "ddr/hw_ddr_mode.h"
#include "ddr/hw_ddr_off_mode.h"
#include "ddr/hw_ddr_segs.h"
#include "ddr/hw_ddrc.h"
#include "clocks/hw_mss_clks.h"
#include "clocks/hw_clk_sysreg.h"
#include "clocks/hw_clk_mss_pll.h"
#include "clocks/hw_clk_sgmii_pll.h"
#include "clocks/hw_clk_ddr_pll.h"
#include "clocks/hw_clk_mss_cfm.h"
#include "clocks/hw_clk_sgmii_cfm.h"
#include "general/hw_gen_peripherals.h"
#ifdef __cplusplus
extern "C" {
#endif
/* No content in this file, used for referencing header */
#ifdef __cplusplus
}
#endif
#endif /* #ifdef FPGA_DESIGN_CONFIG_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_gen_peripherals.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_GEN_PERIPHERALS_H_
#define HW_GEN_PERIPHERALS_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_GPIO_CR)
/*GPIO Blocks reset control- (soft_reset options chossen in Libero confgurator)
*/
#define LIBERO_SETTING_GPIO_CR 0x000F0703UL
/* GPIO0_SOFT_RESET_SELECT [0:2] RW value= 0x3 */
/* GPIO0_DEFAULT [4:2] RW value= 0x0 */
/* GPIO1_SOFT_RESET_SELECT [8:3] RW value= 0x7 */
/* GPIO1_DEFAULT [12:3] RW value= 0x0 */
/* GPIO2_SOFT_RESET_SELECT [16:4] RW value= 0xF */
/* GPIO2_DEFAULT [20:4] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_CRYPTO_CR_INFO)
/*Information on how Crypto setup on this MPFS */
#define LIBERO_SETTING_CRYPTO_CR_INFO 0x00000000UL
/* MSS_MODE [0:2] RO */
/* RESERVED [2:1] RO */
/* STREAM_ENABLE [3:1] RO */
/* RESERVED1 [4:28] RO */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_GEN_PERIPHERALS_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_hsio_mux.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_HSIO_MUX_H_
#define HW_HSIO_MUX_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_TRIM_OPTIONS)
/*User trim options- set option to 1 to use */
#define LIBERO_SETTING_TRIM_OPTIONS 0x00000000UL
/* TRIM_DDR_OPTION [0:1] */
/* TRIM_SGMII_OPTION [1:1] */
#endif
#if !defined (LIBERO_SETTING_DDR_IOC_REG0)
/*Manual trim values */
#define LIBERO_SETTING_DDR_IOC_REG0 0x00000000UL
/* BANK_PCODE [0:6] RW value= 0x0 */
/* BANK_NCODE [6:6] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SGMII_IOC_REG0)
/*Manual trim values */
#define LIBERO_SETTING_SGMII_IOC_REG0 0x00000000UL
/* BANK_PCODE [0:6] RW value= 0x0 */
/* BANK_NCODE [6:6] RW value= 0x0 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_HSIO_MUX_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mssio_mux.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MSSIO_MUX_H_
#define HW_MSSIO_MUX_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_IOMUX0_CR)
/*Selects whether the peripheral is connected to the Fabric or IOMUX structure.
*/
#define LIBERO_SETTING_IOMUX0_CR 0x00000F9DUL
/* SPI0_FABRIC [0:1] RW value= 0x1 */
/* SPI1_FABRIC [1:1] RW value= 0x0 */
/* I2C0_FABRIC [2:1] RW value= 0x1 */
/* I2C1_FABRIC [3:1] RW value= 0x1 */
/* CAN0_FABRIC [4:1] RW value= 0x1 */
/* CAN1_FABRIC [5:1] RW value= 0x0 */
/* QSPI_FABRIC [6:1] RW value= 0x0 */
/* MMUART0_FABRIC [7:1] RW value= 0x1 */
/* MMUART1_FABRIC [8:1] RW value= 0x1 */
/* MMUART2_FABRIC [9:1] RW value= 0x1 */
/* MMUART3_FABRIC [10:1] RW value= 0x1 */
/* MMUART4_FABRIC [11:1] RW value= 0x1 */
/* MDIO0_FABRIC [12:1] RW value= 0x0 */
/* MDIO1_FABRIC [13:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_IOMUX1_CR)
/*Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies
EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies
I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved
(Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies
Logic 0,0xE implies Logic 1, 0xF implies Tristate */
#define LIBERO_SETTING_IOMUX1_CR 0x11111111UL
/* PAD0 [0:4] RW value= 0x1 */
/* PAD1 [4:4] RW value= 0x1 */
/* PAD2 [8:4] RW value= 0x1 */
/* PAD3 [12:4] RW value= 0x1 */
/* PAD4 [16:4] RW value= 0x1 */
/* PAD5 [20:4] RW value= 0x1 */
/* PAD6 [24:4] RW value= 0x1 */
/* PAD7 [28:4] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_IOMUX2_CR)
/*Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies
EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies
I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved
(Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies
Logic 0,0xE implies Logic 1, 0xF implies Tristate */
#define LIBERO_SETTING_IOMUX2_CR 0x00FF1111UL
/* PAD8 [0:4] RW value= 0x1 */
/* PAD9 [4:4] RW value= 0x1 */
/* PAD10 [8:4] RW value= 0x1 */
/* PAD11 [12:4] RW value= 0x1 */
/* PAD12 [16:4] RW value= 0xF */
/* PAD13 [20:4] RW value= 0xF */
#endif
#if !defined (LIBERO_SETTING_IOMUX3_CR)
/*Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies
EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies
I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved
(Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies
Logic 0,0xE implies Logic 1, 0xF implies Tristate */
#define LIBERO_SETTING_IOMUX3_CR 0x44444444UL
/* PAD14 [0:4] RW value= 0x4 */
/* PAD15 [4:4] RW value= 0x4 */
/* PAD16 [8:4] RW value= 0x4 */
/* PAD17 [12:4] RW value= 0x4 */
/* PAD18 [16:4] RW value= 0x4 */
/* PAD19 [20:4] RW value= 0x4 */
/* PAD20 [24:4] RW value= 0x4 */
/* PAD21 [28:4] RW value= 0x4 */
#endif
#if !defined (LIBERO_SETTING_IOMUX4_CR)
/*Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies
EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies
I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved
(Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies
Logic 0,0xE implies Logic 1, 0xF implies Tristate */
#define LIBERO_SETTING_IOMUX4_CR 0x88CC4444UL
/* PAD22 [0:4] RW value= 0x4 */
/* PAD23 [4:4] RW value= 0x4 */
/* PAD24 [8:4] RW value= 0x4 */
/* PAD25 [12:4] RW value= 0x4 */
/* PAD26 [16:4] RW value= 0xC */
/* PAD27 [20:4] RW value= 0xC */
/* PAD28 [24:4] RW value= 0x8 */
/* PAD29 [28:4] RW value= 0x8 */
#endif
#if !defined (LIBERO_SETTING_IOMUX5_CR)
/*Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies
EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies
I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved
(Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies
Logic 0,0xE implies Logic 1, 0xF implies Tristate */
#define LIBERO_SETTING_IOMUX5_CR 0xF7772222UL
/* PAD30 [0:4] RW value= 0x2 */
/* PAD31 [4:4] RW value= 0x2 */
/* PAD32 [8:4] RW value= 0x2 */
/* PAD33 [12:4] RW value= 0x2 */
/* PAD34 [16:4] RW value= 0x7 */
/* PAD35 [20:4] RW value= 0x7 */
/* PAD36 [24:4] RW value= 0x7 */
/* PAD37 [28:4] RW value= 0xF */
#endif
#if !defined (LIBERO_SETTING_IOMUX6_CR)
/*Sets whether the MMC/SD Voltage select lines are inverted on entry to the
IOMUX structure */
#define LIBERO_SETTING_IOMUX6_CR 0x00000000UL
/* VLT_SEL [0:1] RW value= 0x0 */
/* VLT_EN [1:1] RW value= 0x0 */
/* VLT_CMD_DIR [2:1] RW value= 0x0 */
/* VLT_DIR_0 [3:1] RW value= 0x0 */
/* VLT_DIR_1_3 [4:1] RW value= 0x0 */
/* SD_LED [5:1] RW value= 0x0 */
/* SD_VOLT_0 [6:1] RW value= 0x0 */
/* SD_VOLT_1 [7:1] RW value= 0x0 */
/* SD_VOLT_2 [8:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK4_CFG_CR)
/*Configures the MSSIO block using SCB write */
#define LIBERO_SETTING_MSSIO_BANK4_CFG_CR 0x00040A0DUL
/* BANK_PCODE [0:6] RW value= 0xD */
/* RESERVED0 [6:2] RW value= 0x00 */
/* BANK_NCODE [8:6] RW value= 0xA */
/* RESERVED1 [14:2] RW value= 0x0 */
/* VS [16:4] RW value= 0x4 */
/* RESERVED2 [20:12] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_0_1_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_0_1_CR 0x09280928UL
/* IO_CFG_0 [0:16] RW value= 0x0928 */
/* IO_CFG_1 [16:16] RW value= 0x0928 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_2_3_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_2_3_CR 0x09280928UL
/* IO_CFG_2 [0:16] RW value= 0x0928 */
/* IO_CFG_3 [16:16] RW value= 0x0928 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_4_5_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_4_5_CR 0x09280928UL
/* IO_CFG_4 [0:16] RW value= 0x0928 */
/* IO_CFG_5 [16:16] RW value= 0x0928 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_6_7_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_6_7_CR 0x09280928UL
/* IO_CFG_6 [0:16] RW value= 0x0928 */
/* IO_CFG_7 [16:16] RW value= 0x0928 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_8_9_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_8_9_CR 0x09280928UL
/* IO_CFG_8 [0:16] RW value= 0x0928 */
/* IO_CFG_9 [16:16] RW value= 0x0928 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_10_11_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_10_11_CR 0x09280928UL
/* IO_CFG_10 [0:16] RW value= 0x0928 */
/* IO_CFG_11 [16:16] RW value= 0x0928 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK4_IO_CFG_12_13_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK4_IO_CFG_12_13_CR 0x09280928UL
/* IO_CFG_12 [0:16] RW value= 0x0928 */
/* IO_CFG_13 [16:16] RW value= 0x0928 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_CFG_CR)
/*Configures the MSSIO block using SCB write */
#define LIBERO_SETTING_MSSIO_BANK2_CFG_CR 0x00080907UL
/* BANK_PCODE [0:6] RW value= 0x7 */
/* RESERVED0 [6:2] RW value= 0x00 */
/* BANK_NCODE [8:6] RW value= 0x9 */
/* RESERVED1 [14:2] RW value= 0x0 */
/* VS [16:4] RW value= 0x8 */
/* RESERVED2 [20:12] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_0_1_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_0_1_CR 0x08290829UL
/* IO_CFG_0 [0:16] RW value= 0x0829 */
/* IO_CFG_1 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_2_3_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_2_3_CR 0x08290829UL
/* IO_CFG_2 [0:16] RW value= 0x0829 */
/* IO_CFG_3 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_4_5_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_4_5_CR 0x08290829UL
/* IO_CFG_4 [0:16] RW value= 0x0829 */
/* IO_CFG_5 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_6_7_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_6_7_CR 0x08290829UL
/* IO_CFG_6 [0:16] RW value= 0x0829 */
/* IO_CFG_7 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_8_9_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_8_9_CR 0x08290829UL
/* IO_CFG_8 [0:16] RW value= 0x0829 */
/* IO_CFG_9 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_10_11_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_10_11_CR 0x08290829UL
/* IO_CFG_10 [0:16] RW value= 0x0829 */
/* IO_CFG_11 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_12_13_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_12_13_CR 0x08290829UL
/* IO_CFG_12 [0:16] RW value= 0x0829 */
/* IO_CFG_13 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_14_15_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_14_15_CR 0x08290829UL
/* IO_CFG_14 [0:16] RW value= 0x0829 */
/* IO_CFG_15 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_16_17_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_16_17_CR 0x08290829UL
/* IO_CFG_16 [0:16] RW value= 0x0829 */
/* IO_CFG_17 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_18_19_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_18_19_CR 0x08290829UL
/* IO_CFG_18 [0:16] RW value= 0x0829 */
/* IO_CFG_19 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_20_21_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_20_21_CR 0x08290829UL
/* IO_CFG_20 [0:16] RW value= 0x0829 */
/* IO_CFG_21 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_BANK2_IO_CFG_22_23_CR)
/*IO electrical configuration for MSSIO pad */
#define LIBERO_SETTING_MSSIO_BANK2_IO_CFG_22_23_CR 0x08290829UL
/* IO_CFG_22 [0:16] RW value= 0x0829 */
/* IO_CFG_23 [16:16] RW value= 0x0829 */
#endif
#if !defined (LIBERO_SETTING_MSSIO_VB2_CFG)
/*default dpc values for MSSIO bank 2 */
#define LIBERO_SETTING_MSSIO_VB2_CFG 0x00000828UL
/* DPC_IO_CFG_IBUFMD_0 [0:1] RW value= 0x0 */
/* DPC_IO_CFG_IBUFMD_1 [1:1] RW value= 0x0 */
/* DPC_IO_CFG_IBUFMD_2 [2:1] RW value= 0x0 */
/* DPC_IO_CFG_DRV_0 [3:1] RW value= 0x1 */
/* DPC_IO_CFG_DRV_1 [4:1] RW value= 0x0 */
/* DPC_IO_CFG_DRV_2 [5:1] RW value= 0x1 */
/* DPC_IO_CFG_DRV_3 [6:1] RW value= 0x0 */
/* DPC_IO_CFG_CLAMP [7:1] RW value= 0x0 */
/* DPC_IO_CFG_ENHYST [8:1] RW value= 0x0 */
/* DPC_IO_CFG_LOCKDN_EN [9:1] RW value= 0x0 */
/* DPC_IO_CFG_WPD [10:1] RW value= 0x0 */
/* DPC_IO_CFG_WPU [11:1] RW value= 0x1 */
/* DPC_IO_CFG_ATP_EN [12:1] RW value= 0x0 */
/* DPC_IO_CFG_LP_PERSIST_EN [13:1] RW value= 0x0 */
/* DPC_IO_CFG_LP_BYPASS_EN [14:1] RW value= 0x0 */
/* RESERVED [15:17] R */
#endif
#if !defined (LIBERO_SETTING_MSSIO_VB4_CFG)
/*default dpc values for MSSIO bank 4 */
#define LIBERO_SETTING_MSSIO_VB4_CFG 0x00000828UL
/* DPC_IO_CFG_IBUFMD_0 [0:1] RW value= 0x0 */
/* DPC_IO_CFG_IBUFMD_1 [1:1] RW value= 0x0 */
/* DPC_IO_CFG_IBUFMD_2 [2:1] RW value= 0x0 */
/* DPC_IO_CFG_DRV_0 [3:1] RW value= 0x1 */
/* DPC_IO_CFG_DRV_1 [4:1] RW value= 0x0 */
/* DPC_IO_CFG_DRV_2 [5:1] RW value= 0x1 */
/* DPC_IO_CFG_DRV_3 [6:1] RW value= 0x0 */
/* DPC_IO_CFG_CLAMP [7:1] RW value= 0x0 */
/* DPC_IO_CFG_ENHYST [8:1] RW value= 0x0 */
/* DPC_IO_CFG_LOCKDN_EN [9:1] RW value= 0x0 */
/* DPC_IO_CFG_WPD [10:1] RW value= 0x0 */
/* DPC_IO_CFG_WPU [11:1] RW value= 0x1 */
/* DPC_IO_CFG_ATP_EN [12:1] RW value= 0x0 */
/* DPC_IO_CFG_LP_PERSIST_EN [13:1] RW value= 0x0 */
/* DPC_IO_CFG_LP_BYPASS_EN [14:1] RW value= 0x0 */
/* RESERVED [15:17] R */
#endif
#if !defined (LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS)
/*Indicates if eMMC is configured for use (bit 0 == 1), If SD is configued for
use (bit 1 == 1). Bit 2 indicates which one should be used by default on MSS
embedded software startup ( bit2 == 0, implies default is eMMC, bit2 == 1,
implies default is SD). The eMMC configuration is always defined in xml tag
(io_mux, the SD configuration is always defined in xml tag (io_mux_alt). All
other elements in the (o_mux) and (io_mux_alt) not releating to eMMC/SD
differences should be the same values. */
#define LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS 0x00000000UL
/* EMMC_CONFIGURED [0:1] RW value= 0x0 */
/* SD_CONFIGURED [1:1] RW value= 0x0 */
/* DEFAULT_ON_START [2:1] RW value= 0x0 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MSSIO_MUX_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_apb_split.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_APB_SPLIT_H_
#define HW_APB_SPLIT_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_APB_SPLIT_VERSION)
/*This version incrments when change to format of this file */
#define LIBERO_SETTING_APB_SPLIT_VERSION 0x00000001UL
/* VERSION [0:32] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_MEM_CONFIGS_ENABLED)
/*Enabled in configurator when bit set to 1 */
#define LIBERO_SETTING_MEM_CONFIGS_ENABLED 0x00000000UL
/* PMP [0:0] RW value= 0x0 */
/* MPU [1:0] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_APBBUS_CR)
/*AMP Mode peripheral mapping register. When the register bit is '0' the
peripheral is mapped into the 0x2000000 address range using AXI bus 5 from the
Coreplex. When the register bit is '1' the peripheral is mapped into the
0x28000000 address range using AXI bus 6 from the Coreplex. */
#define LIBERO_SETTING_APBBUS_CR 0x00000000UL
/* MMUART0 [0:1] RW value= 0x0 */
/* MMUART1 [1:1] RW value= 0x0 */
/* MMUART2 [2:1] RW value= 0x0 */
/* MMUART3 [3:1] RW value= 0x0 */
/* MMUART4 [4:1] RW value= 0x0 */
/* WDOG0 [5:1] RW value= 0x0 */
/* WDOG1 [6:1] RW value= 0x0 */
/* WDOG2 [7:1] RW value= 0x0 */
/* WDOG3 [8:1] RW value= 0x0 */
/* WDOG4 [9:1] RW value= 0x0 */
/* SPI0 [10:1] RW value= 0x0 */
/* SPI1 [11:1] RW value= 0x0 */
/* I2C0 [12:1] RW value= 0x0 */
/* I2C1 [13:1] RW value= 0x0 */
/* CAN0 [14:1] RW value= 0x0 */
/* CAN1 [15:1] RW value= 0x0 */
/* GEM0 [16:1] RW value= 0x0 */
/* GEM1 [17:1] RW value= 0x0 */
/* TIMER [18:1] RW value= 0x0 */
/* GPIO0 [19:1] RW value= 0x0 */
/* GPIO1 [20:1] RW value= 0x0 */
/* GPIO2 [21:1] RW value= 0x0 */
/* RTC [22:1] RW value= 0x0 */
/* H2FINT [23:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_CONTEXT_A_EN)
/*AMP context A. When the register bit is '0' the peripheral is not allowed
access from context A. */
#define LIBERO_SETTING_CONTEXT_A_EN 0x00000000UL
/* MMUART0 [0:1] RW value= 0x0 */
/* MMUART1 [1:1] RW value= 0x0 */
/* MMUART2 [2:1] RW value= 0x0 */
/* MMUART3 [3:1] RW value= 0x0 */
/* MMUART4 [4:1] RW value= 0x0 */
/* WDOG0 [5:1] RW value= 0x0 */
/* WDOG1 [6:1] RW value= 0x0 */
/* WDOG2 [7:1] RW value= 0x0 */
/* WDOG3 [8:1] RW value= 0x0 */
/* WDOG4 [9:1] RW value= 0x0 */
/* SPI0 [10:1] RW value= 0x0 */
/* SPI1 [11:1] RW value= 0x0 */
/* I2C0 [12:1] RW value= 0x0 */
/* I2C1 [13:1] RW value= 0x0 */
/* CAN0 [14:1] RW value= 0x0 */
/* CAN1 [15:1] RW value= 0x0 */
/* GEM0 [16:1] RW value= 0x0 */
/* GEM1 [17:1] RW value= 0x0 */
/* TIMER [18:1] RW value= 0x0 */
/* GPIO0 [19:1] RW value= 0x0 */
/* GPIO1 [20:1] RW value= 0x0 */
/* GPIO2 [21:1] RW value= 0x0 */
/* RTC [22:1] RW value= 0x0 */
/* H2FINT [23:1] RW value= 0x0 */
/* CRYPTO [24:1] RW value= 0x0 */
/* USB [25:1] RW value= 0x0 */
/* QSPIXIP [26:1] RW value= 0x0 */
/* ATHENA [27:1] RW value= 0x0 */
/* TRACE [28:1] RW value= 0x0 */
/* MAILBOX_SC [29:1] RW value= 0x0 */
/* EMMC [30:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_CONTEXT_B_EN)
/*AMP context B. When the register bit is '0' the peripheral is not allowed
access from context B. */
#define LIBERO_SETTING_CONTEXT_B_EN 0x00000000UL
/* MMUART0 [0:1] RW value= 0x0 */
/* MMUART1 [1:1] RW value= 0x0 */
/* MMUART2 [2:1] RW value= 0x0 */
/* MMUART3 [3:1] RW value= 0x0 */
/* MMUART4 [4:1] RW value= 0x0 */
/* WDOG0 [5:1] RW value= 0x0 */
/* WDOG1 [6:1] RW value= 0x0 */
/* WDOG2 [7:1] RW value= 0x0 */
/* WDOG3 [8:1] RW value= 0x0 */
/* WDOG4 [9:1] RW value= 0x0 */
/* SPI0 [10:1] RW value= 0x0 */
/* SPI1 [11:1] RW value= 0x0 */
/* I2C0 [12:1] RW value= 0x0 */
/* I2C1 [13:1] RW value= 0x0 */
/* CAN0 [14:1] RW value= 0x0 */
/* CAN1 [15:1] RW value= 0x0 */
/* GEM0 [16:1] RW value= 0x0 */
/* GEM1 [17:1] RW value= 0x0 */
/* TIMER [18:1] RW value= 0x0 */
/* GPIO0 [19:1] RW value= 0x0 */
/* GPIO1 [20:1] RW value= 0x0 */
/* GPIO2 [21:1] RW value= 0x0 */
/* RTC [22:1] RW value= 0x0 */
/* H2FINT [23:1] RW value= 0x0 */
/* CRYPTO [24:1] RW value= 0x0 */
/* USB [25:1] RW value= 0x0 */
/* QSPIXIP [26:1] RW value= 0x0 */
/* ATHENA [27:1] RW value= 0x0 */
/* TRACE [28:1] RW value= 0x0 */
/* MAILBOX_SC [29:1] RW value= 0x0 */
/* EMMC [30:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_CONTEXT_A_HART_EN)
/*When the register bit is '0' hart is not associated with context A. */
#define LIBERO_SETTING_CONTEXT_A_HART_EN 0x00000000UL
/* HART0 [0:1] RW value= 0x0 */
/* HART1 [1:1] RW value= 0x0 */
/* HART2 [2:1] RW value= 0x0 */
/* HART3 [3:1] RW value= 0x0 */
/* HART4 [4:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_CONTEXT_B_HART_EN)
/*When the register bit is '0' hart is not associated with context B. */
#define LIBERO_SETTING_CONTEXT_B_HART_EN 0x00000000UL
/* HART0 [0:1] RW value= 0x0 */
/* HART1 [1:1] RW value= 0x0 */
/* HART2 [2:1] RW value= 0x0 */
/* HART3 [3:1] RW value= 0x0 */
/* HART4 [4:1] RW value= 0x0 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_APB_SPLIT_H_ */

436
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design_config/memory_map/hw_cache.h Normal file
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@ -0,0 +1,436 @@
/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_cache.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_CACHE_H_
#define HW_CACHE_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_WAY_ENABLE)
/*Way indexes less than or equal to this register value may be used by the
cache. E.g. set to 0x7, will allocate 8 cache ways, 0-7 to cache, and leave
8-15 as LIM. Note 1: Way 0 is always allocated as cache. Note 2: each way is
128KB. */
#define LIBERO_SETTING_WAY_ENABLE 0x0000000BUL
/* WAY_ENABLE [0:8] RW value= 0xB */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_DMA)
/*Way mask register master DMA. Set field to zero to disable way from this
master. The available cache ways are 0 to number set in WAY_ENABLE register. If
using scratch pad memory, the ways you want reserved for scrathpad are not
available for selection, you must set to 0. e.g. If three ways reserved for
scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all
masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_DMA 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_0)
/*Way mask register master DMA. Set field to zero to disable way from this
master. The available cache ways are 0 to number set in WAY_ENABLE register. If
using scratch pad memory, the ways you want reserved for scrathpad are not
available for selection, you must set to 0. e.g. If three ways reserved for
scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all
masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_0 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_1)
/*Way mask register master DMA. Set field to zero to disable way from this
master. The available cache ways are 0 to number set in WAY_ENABLE register. If
using scratch pad memory, the ways you want reserved for scrathpad are not
available for selection, you must set to 0. e.g. If three ways reserved for
scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all
masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_1 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_2)
/*Way mask registerAXI slave port 2. Set field to zero to disable way from this
master. The available cache ways are 0 to number set in WAY_ENABLE register. If
using scratch pad memory, the ways you want reserved for scrathpad are not
available for selection, you must set to 0. e.g. If three ways reserved for
scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all
masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_2 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_3)
/*Way mask register AXI slave port 3. Set field to 1 to disable way from this
master. Set field to zero to disable way from this master. The available cache
ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory,
the ways you want reserved for scrathpad are not available for selection, you
must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0,
WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not
evict the way. */
#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_3 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_E51_DCACHE)
/*Way mask register E51 data cache (hart0). Set field to zero to disable way
from this master. The available cache ways are 0 to number set in WAY_ENABLE
register. If using scratch pad memory, the ways you want reserved for scrathpad
are not available for selection, you must set to 0. e.g. If three ways reserved
for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for
all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_E51_DCACHE 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_E51_ICACHE)
/*Way mask registerE52 instruction cache (hart0). Set field to zero to disable
way from this master. The available cache ways are 0 to number set in
WAY_ENABLE register. If using scratch pad memory, the ways you want reserved
for scrathpad are not available for selection, you must set to 0. e.g. If three
ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set
to zero for all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_E51_ICACHE 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_1_DCACHE)
/*Way mask register data cache (hart1). Set field to zero to disable way from
this master. The available cache ways are 0 to number set in WAY_ENABLE
register. If using scratch pad memory, the ways you want reserved for scrathpad
are not available for selection, you must set to 0. e.g. If three ways reserved
for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for
all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_1_DCACHE 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_1_ICACHE)
/*Way mask register instruction cache (hart1). Set field to zero to disable way
from this master. The available cache ways are 0 to number set in WAY_ENABLE
register. If using scratch pad memory, the ways you want reserved for scrathpad
are not available for selection, you must set to 0. e.g. If three ways reserved
for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for
all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_1_ICACHE 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_2_DCACHE)
/*Way mask register data cache (hart2). Set field to 1 to disable way from this
master. Set field to zero to disable way from this master. The available cache
ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory,
the ways you want reserved for scrathpad are not available for selection, you
must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0,
WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not
evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_2_DCACHE 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_2_ICACHE)
/*Way mask register instruction cache (hart2). Set field to zero to disable way
from this master. The available cache ways are 0 to number set in WAY_ENABLE
register. If using scratch pad memory, the ways you want reserved for scrathpad
are not available for selection, you must set to 0. e.g. If three ways reserved
for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for
all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_2_ICACHE 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_3_DCACHE)
/*Way mask register data cache (hart3). Set field to 1 to disable way from this
master.Set field to zero to disable way from this master. The available cache
ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory,
the ways you want reserved for scrathpad are not available for selection, you
must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0,
WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not
evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_3_DCACHE 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_3_ICACHE)
/*Way mask register instruction cache(hart3). Set field to zero to disable way
from this master. The available cache ways are 0 to number set in WAY_ENABLE
register. If using scratch pad memory, the ways you want reserved for scrathpad
are not available for selection, you must set to 0. e.g. If three ways reserved
for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for
all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_3_ICACHE 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_4_DCACHE)
/*Way mask register data cache (hart4). Set field to 1 to disable way from this
master. Set field to zero to disable way from this master. The available cache
ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory,
the ways you want reserved for scrathpad are not available for selection, you
must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0,
WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not
evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_4_DCACHE 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_4_ICACHE)
/*Way mask register instruction cache (hart4). Set field to zero to disable way
from this master. The available cache ways are 0 to number set in WAY_ENABLE
register. If using scratch pad memory, the ways you want reserved for scrathpad
are not available for selection, you must set to 0. e.g. If three ways reserved
for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for
all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_4_ICACHE 0x0000F0FFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x0 */
/* WAY_MASK_9 [9:1] RW value= 0x0 */
/* WAY_MASK_10 [10:1] RW value= 0x0 */
/* WAY_MASK_11 [11:1] RW value= 0x0 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS)
/*Number of ways reserved for scratchpad. Note 1: This is not a register Note
2: each way is 128KB. Note 3: Embedded software expects cache ways allocated
for scratchpad start at way 0, and work up. */
#define LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS 0x00000004UL
/* NUM_OF_WAYS [0:8] RW value= 0x4 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_CACHE_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_memory.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MEMORY_H_
#define HW_MEMORY_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_RESET_VECTOR_HART0)
/*Reset vector hart0 */
#define LIBERO_SETTING_RESET_VECTOR_HART0 0x20220000
#define LIBERO_SETTING_RESET_VECTOR_HART0_SIZE 0x4 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_RESET_VECTOR_HART1)
/*Reset vector hart1 */
#define LIBERO_SETTING_RESET_VECTOR_HART1 0x20220000
#define LIBERO_SETTING_RESET_VECTOR_HART1_SIZE 0x4 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_RESET_VECTOR_HART2)
/*Reset vector hart2 */
#define LIBERO_SETTING_RESET_VECTOR_HART2 0x20220000
#define LIBERO_SETTING_RESET_VECTOR_HART2_SIZE 0x4 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_RESET_VECTOR_HART3)
/*Reset vector hart3 */
#define LIBERO_SETTING_RESET_VECTOR_HART3 0x20220000
#define LIBERO_SETTING_RESET_VECTOR_HART3_SIZE 0x4 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_RESET_VECTOR_HART4)
/*Reset vector hart4 */
#define LIBERO_SETTING_RESET_VECTOR_HART4 0x20220000
#define LIBERO_SETTING_RESET_VECTOR_HART4_SIZE 0x4 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_DDR_32_CACHE)
/*example instance of memory */
#define LIBERO_SETTING_DDR_32_CACHE 0x80000000
#define LIBERO_SETTING_DDR_32_CACHE_SIZE 0x100000 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_DDR_32_NON_CACHE)
/*example instance */
#define LIBERO_SETTING_DDR_32_NON_CACHE 0xC0000000
#define LIBERO_SETTING_DDR_32_NON_CACHE_SIZE 0x100000 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_DDR_64_CACHE)
/*64 bit address */
#define LIBERO_SETTING_DDR_64_CACHE 0x1000000000
#define LIBERO_SETTING_DDR_64_CACHE_SIZE 0x100000 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_DDR_64_NON_CACHE)
/*64 bit address */
#define LIBERO_SETTING_DDR_64_NON_CACHE 0x1400000000
#define LIBERO_SETTING_DDR_64_NON_CACHE_SIZE 0x100000 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_DDR_32_WCB)
/*example instance */
#define LIBERO_SETTING_DDR_32_WCB 0xD0000000
#define LIBERO_SETTING_DDR_32_WCB_SIZE 0x100000 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_DDR_64_WCB)
/*64 bit address */
#define LIBERO_SETTING_DDR_64_WCB 0x1800000000
#define LIBERO_SETTING_DDR_64_WCB_SIZE 0x100000 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_RESERVED_SNVM)
/*Offset and size of reserved sNVM. (Not available to MSS) */
#define LIBERO_SETTING_RESERVED_SNVM 0x00000000
#define LIBERO_SETTING_RESERVED_SNVM_SIZE 0x00000000 /* Length of memory block*/
#endif
#if !defined (LIBERO_SETTING_RESERVED_ENVM)
/*Offset and size of reserved eNVM (Not available to MSS) */
#define LIBERO_SETTING_RESERVED_ENVM 0x00000000
#define LIBERO_SETTING_RESERVED_ENVM_SIZE 0x00000000 /* Length of memory block*/
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MEMORY_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mpu_crypto.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MPU_CRYPTO_H_
#define HW_MPU_CRYPTO_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_CRYPTO_MPU_CFG_PMP0)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_CRYPTO_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_CRYPTO_MPU_CFG_PMP1)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_CRYPTO_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_CRYPTO_MPU_CFG_PMP2)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_CRYPTO_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_CRYPTO_MPU_CFG_PMP3)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_CRYPTO_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MPU_CRYPTO_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mpu_fic0.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MPU_FIC0_H_
#define HW_MPU_FIC0_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP0)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP1)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP2)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP3)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP4)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP5)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP6)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP7)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP8)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP8 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP9)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP9 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP10)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP10 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP11)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP11 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP12)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP12 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP13)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP13 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP14)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP14 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC0_MPU_CFG_PMP15)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC0_MPU_CFG_PMP15 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MPU_FIC0_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mpu_fic1.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MPU_FIC1_H_
#define HW_MPU_FIC1_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP0)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP1)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP2)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP3)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP4)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP5)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP6)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP7)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP8)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP8 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP9)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP9 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP10)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP10 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP11)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP11 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP12)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP12 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP13)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP13 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP14)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP14 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC1_MPU_CFG_PMP15)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC1_MPU_CFG_PMP15 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MPU_FIC1_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mpu_fic2.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MPU_FIC2_H_
#define HW_MPU_FIC2_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP0)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_FIC2_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP1)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_FIC2_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP2)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC2_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP3)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC2_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP4)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC2_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP5)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC2_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP6)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC2_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_FIC2_MPU_CFG_PMP7)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_FIC2_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MPU_FIC2_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mpu_gem0.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MPU_GEM0_H_
#define HW_MPU_GEM0_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP0)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_GEM0_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP1)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_GEM0_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP2)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM0_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP3)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM0_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP4)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM0_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP5)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM0_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP6)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM0_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM0_MPU_CFG_PMP7)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM0_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MPU_GEM0_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mpu_gem1.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MPU_GEM1_H_
#define HW_MPU_GEM1_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP0)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_GEM1_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP1)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_GEM1_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP2)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM1_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP3)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM1_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP4)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM1_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP5)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM1_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP6)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM1_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_GEM1_MPU_CFG_PMP7)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_GEM1_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MPU_GEM1_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mpu_mmc.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MPU_MMC_H_
#define HW_MPU_MMC_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_MMC_MPU_CFG_PMP0)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_MMC_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_MMC_MPU_CFG_PMP1)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_MMC_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_MMC_MPU_CFG_PMP2)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_MMC_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_MMC_MPU_CFG_PMP3)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_MMC_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MPU_MMC_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mpu_scb.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MPU_SCB_H_
#define HW_MPU_SCB_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP0)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_SCB_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP1)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_SCB_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP2)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_SCB_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP3)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_SCB_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP4)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_SCB_MPU_CFG_PMP4 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP5)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_SCB_MPU_CFG_PMP5 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP6)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_SCB_MPU_CFG_PMP6 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_SCB_MPU_CFG_PMP7)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_SCB_MPU_CFG_PMP7 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MPU_SCB_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mpu_trace.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MPU_TRACE_H_
#define HW_MPU_TRACE_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_TRACE_MPU_CFG_PMP0)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_TRACE_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_TRACE_MPU_CFG_PMP1)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_TRACE_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MPU_TRACE_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_mpu_usb.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_MPU_USB_H_
#define HW_MPU_USB_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_USB_MPU_CFG_PMP0)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_USB_MPU_CFG_PMP0 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_USB_MPU_CFG_PMP1)
/*mpu setup register, 64 bits */
#define LIBERO_SETTING_USB_MPU_CFG_PMP1 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_USB_MPU_CFG_PMP2)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_USB_MPU_CFG_PMP2 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#if !defined (LIBERO_SETTING_USB_MPU_CFG_PMP3)
/*pmp setup register, 64 bits */
#define LIBERO_SETTING_USB_MPU_CFG_PMP3 0x1F00000FFFFFFFFFULL
/* PMP [0:38] RW value= 0xFFFFFFFFF */
/* RESERVED [38:18] RW value= 0x0 */
/* MODE [56:8] RW value= 0x1F */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_MPU_USB_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_pmp_hart0.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_PMP_HART0_H_
#define HW_PMP_HART0_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPCFG0)
/*PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2
execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */
#define LIBERO_SETTING_HART0_CSR_PMPCFG0 0x0000000000000000ULL
/* PMP0CFG [0:8] RW value= 0x00 */
/* PMP1CFG [8:8] RW value= 0x0 */
/* PMP2CFG [16:8] RW value= 0x00 */
/* PMP3CFG [24:8] RW value= 0x00 */
/* PMP4CFG [32:8] RW value= 0x00 */
/* PMP5CFG [40:8] RW value= 0x00 */
/* PMP6CFG [48:8] RW value= 0x00 */
/* PMP7CFG [56:8] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPCFG2)
/*PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2
execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */
#define LIBERO_SETTING_HART0_CSR_PMPCFG2 0x0000000000000000ULL
/* PMP8CFG [0:8] RW value= 0x00 */
/* PMP9CFG [8:8] RW value= 0x00 */
/* PMP10CFG [16:8] RW value= 0x00 */
/* PMP11CFG [24:8] RW value= 0x00 */
/* PMP12CFG [32:8] RW value= 0x00 */
/* PMP13CFG [40:8] RW value= 0x00 */
/* PMP14CFG [48:8] RW value= 0x00 */
/* PMP15CFG [56:8] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR0)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR0 0x0000000000000000ULL
/* CSR_PMPADDR0 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR1)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR1 0x0000000000000000ULL
/* CSR_PMPADDR1 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR2)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR2 0x0000000000000000ULL
/* CSR_PMPADDR2 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR3)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR3 0x0000000000000000ULL
/* CSR_PMPADDR3 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR4)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR4 0x0000000000000000ULL
/* CSR_PMPADDR4 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR5)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR5 0x0000000000000000ULL
/* CSR_PMPADDR5 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR6)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR6 0x0000000000000000ULL
/* CSR_PMPADDR6 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR7)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR7 0x0000000000000000ULL
/* CSR_PMPADDR7 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR8)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR8 0x0000000000000000ULL
/* CSR_PMPADDR8 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR9)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR9 0x0000000000000000ULL
/* CSR_PMPADDR9 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR10)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR10 0x0000000000000000ULL
/* CSR_PMPADDR10 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR11)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR11 0x0000000000000000ULL
/* CSR_PMPADDR11 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR12)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR12 0x0000000000000000ULL
/* CSR_PMPADDR12 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR13)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR13 0x0000000000000000ULL
/* CSR_PMPADDR13 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR14)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR14 0x0000000000000000ULL
/* CSR_PMPADDR14 [0:64] RW value= 0x00 */
#endif
#if !defined (LIBERO_SETTING_HART0_CSR_PMPADDR15)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART0_CSR_PMPADDR15 0x0000000000000000ULL
/* CSR_PMPADDR15 [0:64] RW value= 0x00 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_PMP_HART0_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_pmp_hart1.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_PMP_HART1_H_
#define HW_PMP_HART1_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPCFG0)
/*PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2
execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */
#define LIBERO_SETTING_HART1_CSR_PMPCFG0 0x000000000000009FULL
/* PMP0CFG [0:8] RW value= 0x9F */
/* PMP1CFG [8:8] RW value= 0x0 */
/* PMP2CFG [16:8] RW value= 0x0 */
/* PMP3CFG [24:8] RW value= 0x0 */
/* PMP4CFG [32:8] RW value= 0x0 */
/* PMP5CFG [40:8] RW value= 0x0 */
/* PMP6CFG [48:8] RW value= 0x0 */
/* PMP7CFG [56:8] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPCFG2)
/*PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2
execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */
#define LIBERO_SETTING_HART1_CSR_PMPCFG2 0x0000000000000000ULL
/* PMP8CFG [0:8] RW value= 0x0 */
/* PMP9CFG [8:8] RW value= 0x0 */
/* PMP10CFG [16:8] RW value= 0x0 */
/* PMP11CFG [24:8] RW value= 0x0 */
/* PMP12CFG [32:8] RW value= 0x0 */
/* PMP13CFG [40:8] RW value= 0x0 */
/* PMP14CFG [48:8] RW value= 0x0 */
/* PMP15CFG [56:8] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR0)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR0 0xFFFFFFFFFFFFFFFFULL
/* CSR_PMPADDR0 [0:64] RW value= 0xFFFFFFFFFFFFFFFF */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR1)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR1 0x0000000000000000ULL
/* CSR_PMPADDR1 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR2)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR2 0x0000000000000000ULL
/* CSR_PMPADDR2 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR3)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR3 0x0000000000000000ULL
/* CSR_PMPADDR3 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR4)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR4 0x0000000000000000ULL
/* CSR_PMPADDR4 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR5)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR5 0x0000000000000000ULL
/* CSR_PMPADDR5 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR6)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR6 0x0000000000000000ULL
/* CSR_PMPADDR6 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR7)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR7 0x0000000000000000ULL
/* CSR_PMPADDR7 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR8)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR8 0x0000000000000000ULL
/* CSR_PMPADDR8 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR9)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR9 0x0000000000000000ULL
/* CSR_PMPADDR9 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR10)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR10 0x0000000000000000ULL
/* CSR_PMPADDR10 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR11)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR11 0x0000000000000000ULL
/* CSR_PMPADDR11 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR12)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR12 0x0000000000000000ULL
/* CSR_PMPADDR12 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR13)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR13 0x0000000000000000ULL
/* CSR_PMPADDR13 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR14)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR14 0x0000000000000000ULL
/* CSR_PMPADDR14 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART1_CSR_PMPADDR15)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART1_CSR_PMPADDR15 0x0000000000000000ULL
/* CSR_PMPADDR15 [0:64] RW value= 0x0 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_PMP_HART1_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_pmp_hart2.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_PMP_HART2_H_
#define HW_PMP_HART2_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPCFG0)
/*PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2
execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */
#define LIBERO_SETTING_HART2_CSR_PMPCFG0 0x000000000000009FULL
/* PMP0CFG [0:8] RW value= 0x9F */
/* PMP1CFG [8:8] RW value= 0x0 */
/* PMP2CFG [16:8] RW value= 0x0 */
/* PMP3CFG [24:8] RW value= 0x0 */
/* PMP4CFG [32:8] RW value= 0x0 */
/* PMP5CFG [40:8] RW value= 0x0 */
/* PMP6CFG [48:8] RW value= 0x0 */
/* PMP7CFG [56:8] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPCFG2)
/*PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2
execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */
#define LIBERO_SETTING_HART2_CSR_PMPCFG2 0x0000000000000000ULL
/* PMP8CFG [0:8] RW value= 0x0 */
/* PMP9CFG [8:8] RW value= 0x0 */
/* PMP10CFG [16:8] RW value= 0x0 */
/* PMP11CFG [24:8] RW value= 0x0 */
/* PMP12CFG [32:8] RW value= 0x0 */
/* PMP13CFG [40:8] RW value= 0x0 */
/* PMP14CFG [48:8] RW value= 0x0 */
/* PMP15CFG [56:8] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR0)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR0 0xFFFFFFFFFFFFFFFFULL
/* CSR_PMPADDR0 [0:64] RW value= 0xFFFFFFFFFFFFFFFF */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR1)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR1 0x0000000000000000ULL
/* CSR_PMPADDR1 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR2)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR2 0x0000000000000000ULL
/* CSR_PMPADDR2 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR3)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR3 0x0000000000000000ULL
/* CSR_PMPADDR3 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR4)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR4 0x0000000000000000ULL
/* CSR_PMPADDR4 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR5)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR5 0x0000000000000000ULL
/* CSR_PMPADDR5 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR6)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR6 0x0000000000000000ULL
/* CSR_PMPADDR6 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR7)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR7 0x0000000000000000ULL
/* CSR_PMPADDR7 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR8)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR8 0x0000000000000000ULL
/* CSR_PMPADDR8 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR9)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR9 0x0000000000000000ULL
/* CSR_PMPADDR9 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR10)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR10 0x0000000000000000ULL
/* CSR_PMPADDR10 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR11)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR11 0x0000000000000000ULL
/* CSR_PMPADDR11 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR12)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR12 0x0000000000000000ULL
/* CSR_PMPADDR12 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR13)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR13 0x0000000000000000ULL
/* CSR_PMPADDR13 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR14)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR14 0x0000000000000000ULL
/* CSR_PMPADDR14 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART2_CSR_PMPADDR15)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART2_CSR_PMPADDR15 0x0000000000000000ULL
/* CSR_PMPADDR15 [0:64] RW value= 0x0 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_PMP_HART2_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_pmp_hart3.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_PMP_HART3_H_
#define HW_PMP_HART3_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPCFG0)
/*PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2
execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */
#define LIBERO_SETTING_HART3_CSR_PMPCFG0 0x000000000000009FULL
/* PMP0CFG [0:8] RW value= 0x9F */
/* PMP1CFG [8:8] RW value= 0x0 */
/* PMP2CFG [16:8] RW value= 0x0 */
/* PMP3CFG [24:8] RW value= 0x0 */
/* PMP4CFG [32:8] RW value= 0x0 */
/* PMP5CFG [40:8] RW value= 0x0 */
/* PMP6CFG [48:8] RW value= 0x0 */
/* PMP7CFG [56:8] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPCFG2)
/*PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2
execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */
#define LIBERO_SETTING_HART3_CSR_PMPCFG2 0x0000000000000000ULL
/* PMP8CFG [0:8] RW value= 0x0 */
/* PMP9CFG [8:8] RW value= 0x0 */
/* PMP10CFG [16:8] RW value= 0x0 */
/* PMP11CFG [24:8] RW value= 0x0 */
/* PMP12CFG [32:8] RW value= 0x0 */
/* PMP13CFG [40:8] RW value= 0x0 */
/* PMP14CFG [48:8] RW value= 0x0 */
/* PMP15CFG [56:8] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR0)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR0 0xFFFFFFFFFFFFFFFFULL
/* CSR_PMPADDR0 [0:64] RW value= 0xFFFFFFFFFFFFFFFF */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR1)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR1 0x0000000000000000ULL
/* CSR_PMPADDR1 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR2)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR2 0x0000000000000000ULL
/* CSR_PMPADDR2 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR3)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR3 0x0000000000000000ULL
/* CSR_PMPADDR3 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR4)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR4 0x0000000000000000ULL
/* CSR_PMPADDR4 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR5)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR5 0x0000000000000000ULL
/* CSR_PMPADDR5 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR6)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR6 0x0000000000000000ULL
/* CSR_PMPADDR6 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR7)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR7 0x0000000000000000ULL
/* CSR_PMPADDR7 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR8)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR8 0x0000000000000000ULL
/* CSR_PMPADDR8 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR9)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR9 0x0000000000000000ULL
/* CSR_PMPADDR9 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR10)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR10 0x0000000000000000ULL
/* CSR_PMPADDR10 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR11)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR11 0x0000000000000000ULL
/* CSR_PMPADDR11 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR12)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR12 0x0000000000000000ULL
/* CSR_PMPADDR12 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR13)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR13 0x0000000000000000ULL
/* CSR_PMPADDR13 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR14)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR14 0x0000000000000000ULL
/* CSR_PMPADDR14 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART3_CSR_PMPADDR15)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART3_CSR_PMPADDR15 0x0000000000000000ULL
/* CSR_PMPADDR15 [0:64] RW value= 0x0 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_PMP_HART3_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_pmp_hart4.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_PMP_HART4_H_
#define HW_PMP_HART4_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPCFG0)
/*PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2
execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */
#define LIBERO_SETTING_HART4_CSR_PMPCFG0 0x000000000000009FULL
/* PMP0CFG [0:8] RW value= 0x9F */
/* PMP1CFG [8:8] RW value= 0x0 */
/* PMP2CFG [16:8] RW value= 0x0 */
/* PMP3CFG [24:8] RW value= 0x0 */
/* PMP4CFG [32:8] RW value= 0x0 */
/* PMP5CFG [40:8] RW value= 0x0 */
/* PMP6CFG [48:8] RW value= 0x0 */
/* PMP7CFG [56:8] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPCFG2)
/*PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2
execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) */
#define LIBERO_SETTING_HART4_CSR_PMPCFG2 0x0000000000000000ULL
/* PMP8CFG [0:8] RW value= 0x0 */
/* PMP9CFG [8:8] RW value= 0x0 */
/* PMP10CFG [16:8] RW value= 0x0 */
/* PMP11CFG [24:8] RW value= 0x0 */
/* PMP12CFG [32:8] RW value= 0x0 */
/* PMP13CFG [40:8] RW value= 0x0 */
/* PMP14CFG [48:8] RW value= 0x0 */
/* PMP15CFG [56:8] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR0)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR0 0xFFFFFFFFFFFFFFFFULL
/* CSR_PMPADDR0 [0:64] RW value= 0xFFFFFFFFFFFFFFFF */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR1)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR1 0x0000000000000000ULL
/* CSR_PMPADDR1 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR2)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR2 0x0000000000000000ULL
/* CSR_PMPADDR2 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR3)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR3 0x0000000000000000ULL
/* CSR_PMPADDR3 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR4)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR4 0x0000000000000000ULL
/* CSR_PMPADDR4 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR5)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR5 0x0000000000000000ULL
/* CSR_PMPADDR5 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR6)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR6 0x0000000000000000ULL
/* CSR_PMPADDR6 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR7)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR7 0x0000000000000000ULL
/* CSR_PMPADDR7 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR8)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR8 0x0000000000000000ULL
/* CSR_PMPADDR8 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR9)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR9 0x0000000000000000ULL
/* CSR_PMPADDR9 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR10)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR10 0x0000000000000000ULL
/* CSR_PMPADDR10 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR11)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR11 0x0000000000000000ULL
/* CSR_PMPADDR11 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR12)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR12 0x0000000000000000ULL
/* CSR_PMPADDR12 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR13)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR13 0x0000000000000000ULL
/* CSR_PMPADDR13 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR14)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR14 0x0000000000000000ULL
/* CSR_PMPADDR14 [0:64] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_HART4_CSR_PMPADDR15)
/*PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte
in CSR_PMPCFGx */
#define LIBERO_SETTING_HART4_CSR_PMPADDR15 0x0000000000000000ULL
/* CSR_PMPADDR15 [0:64] RW value= 0x0 */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_PMP_HART4_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* @file hw_sgmii_tip.h
* @author Microchip-FPGA Embedded Systems Solutions
*
*
* Note 1: This file should not be edited. If you need to modify a parameter
* without going through regenerating using the MSS Configurator Libero flow
* or editing the associated xml file
* the following method is recommended:
* 1. edit the following file
* boards/your_board/platform_config/mpfs_hal_config/mss_sw_config.h
* 2. define the value you want to override there.
* (Note: There is a commented example in the platform directory)
* Note 2: The definition in mss_sw_config.h takes precedence, as
* mss_sw_config.h is included prior to the generated header files located in
* boards/your_board/fpga_design_config
*
*/
#ifndef HW_SGMII_TIP_H_
#define HW_SGMII_TIP_H_
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_SGMII_MODE)
/*SGMII mode control (SEU) */
#define LIBERO_SETTING_SGMII_MODE 0x08C0E6FFUL
/* REG_PLL_EN [0:1] RW value= 0x1 */
/* REG_DLL_EN [1:1] RW value= 0x1 */
/* REG_PVT_EN [2:1] RW value= 0x1 */
/* REG_BC_VRGEN_EN [3:1] RW value= 0x1 */
/* REG_TX0_EN [4:1] RW value= 0x1 */
/* REG_RX0_EN [5:1] RW value= 0x1 */
/* REG_TX1_EN [6:1] RW value= 0x1 */
/* REG_RX1_EN [7:1] RW value= 0x1 */
/* REG_DLL_LOCK_FLT [8:2] RW value= 0x2 */
/* REG_DLL_ADJ_CODE [10:4] RW value= 0x9 */
/* REG_CH0_CDR_RESET_B [14:1] RW value= 0x1 */
/* REG_CH1_CDR_RESET_B [15:1] RW value= 0x1 */
/* REG_BC_VRGEN [16:6] RW value= 0x00 */
/* REG_CDR_MOVE_STEP [22:1] RW value= 0x1 */
/* REG_REFCLK_EN_RDIFF [23:1] RW value= 0x1 */
/* REG_BC_VS [24:4] RW value= 0x8 */
/* REG_REFCLK_EN_UDRIVE_P [28:1] RW value= 0x0 */
/* REG_REFCLK_EN_INS_HYST_P [29:1] RW value= 0x0 */
/* REG_REFCLK_EN_UDRIVE_N [30:1] RW value= 0x0 */
/* REG_REFCLK_EN_INS_HYST_N [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_PLL_CNTL)
/*PLL control register (SEU) */
#define LIBERO_SETTING_PLL_CNTL 0x80140101UL
/* REG_PLL_POSTDIV [0:7] RW value= 0x1 */
/* ARO_PLL0_LOCK [7:1] RO */
/* REG_PLL_RFDIV [8:6] RW value= 0x1 */
/* REG_PLL_REG_RFCLK_SEL [14:1] RW value= 0x0 */
/* REG_PLL_LP_REQUIRES_LOCK [15:1] RW value= 0x0 */
/* REG_PLL_INTIN [16:12] RW value= 0x14 */
/* REG_PLL_BWI [28:2] RW value= 0x0 */
/* REG_PLL_BWP [30:2] RW value= 0x2 */
#endif
#if !defined (LIBERO_SETTING_CH0_CNTL)
/*Channel0 control register */
#define LIBERO_SETTING_CH0_CNTL 0x37F07770UL
/* REG_TX0_WPU_P [0:1] RW value= 0x0 */
/* REG_TX0_WPD_P [1:1] RW value= 0x0 */
/* REG_TX0_SLEW_P [2:2] RW value= 0x0 */
/* REG_TX0_DRV_P [4:4] RW value= 0x7 */
/* REG_TX0_ODT_P [8:4] RW value= 0x7 */
/* REG_TX0_ODT_STATIC_P [12:3] RW value= 0x7 */
/* REG_RX0_TIM_LONG [15:1] RW value= 0x0 */
/* REG_RX0_WPU_P [16:1] RW value= 0x0 */
/* REG_RX0_WPD_P [17:1] RW value= 0x0 */
/* REG_RX0_IBUFMD_P [18:3] RW value= 0x4 */
/* REG_RX0_EYEWIDTH_P [21:3] RW value= 0x7 */
/* REG_RX0_ODT_P [24:4] RW value= 0x7 */
/* REG_RX0_ODT_STATIC_P [28:3] RW value= 0x3 */
/* REG_RX0_EN_FLAG_N [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_CH1_CNTL)
/*Channel1 control register */
#define LIBERO_SETTING_CH1_CNTL 0x37F07770UL
/* REG_TX1_WPU_P [0:1] RW value= 0x0 */
/* REG_TX1_WPD_P [1:1] RW value= 0x0 */
/* REG_TX1_SLEW_P [2:2] RW value= 0x0 */
/* REG_TX1_DRV_P [4:4] RW value= 0x7 */
/* REG_TX1_ODT_P [8:4] RW value= 0x7 */
/* REG_TX1_ODT_STATIC_P [12:3] RW value= 0x7 */
/* REG_RX1_TIM_LONG [15:1] RW value= 0x0 */
/* REG_RX1_WPU_P [16:1] RW value= 0x0 */
/* REG_RX1_WPD_P [17:1] RW value= 0x0 */
/* REG_RX1_IBUFMD_P [18:3] RW value= 0x4 */
/* REG_RX1_EYEWIDTH_P [21:3] RW value= 0x7 */
/* REG_RX1_ODT_P [24:4] RW value= 0x7 */
/* REG_RX1_ODT_STATIC_P [28:3] RW value= 0x3 */
/* REG_RX1_EN_FLAG_N [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_RECAL_CNTL)
/*Recalibration control register */
#define LIBERO_SETTING_RECAL_CNTL 0x000020C8UL
/* REG_RECAL_DIFF_RANGE [0:5] RW value= 0x8 */
/* REG_RECAL_START_EN [5:1] RW value= 0x0 */
/* REG_PVT_CALIB_START [6:1] RW value= 0x1 */
/* REG_PVT_CALIB_LOCK [7:1] RW value= 0x1 */
/* REG_RECAL_UPD [8:1] RW value= 0x0 */
/* BC_VRGEN_DIRECTION [9:1] RW value= 0x0 */
/* BC_VRGEN_LOAD [10:1] RW value= 0x0 */
/* BC_VRGEN_MOVE [11:1] RW value= 0x0 */
/* REG_PVT_REG_CALIB_CLKDIV [12:2] RW value= 0x2 */
/* REG_PVT_REG_CALIB_DIFFR_VSEL [14:2] RW value= 0x0 */
/* SRO_DLL_90_CODE [16:7] RO */
/* SRO_DLL_LOCK [23:1] RO */
/* SRO_DLL_ST_CODE [24:7] RO */
/* SRO_RECAL_START [31:1] RO */
#endif
#if !defined (LIBERO_SETTING_CLK_CNTL)
/*Clock input and routing control registers */
#define LIBERO_SETTING_CLK_CNTL 0xF00050CCUL
/* REG_REFCLK_EN_TERM_P [0:2] RW value= 0x0 */
/* REG_REFCLK_EN_RXMODE_P [2:2] RW value= 0x3 */
/* REG_REFCLK_EN_TERM_N [4:2] RW value= 0x0 */
/* REG_REFCLK_EN_RXMODE_N [6:2] RW value= 0x3 */
/* REG_REFCLK_CLKBUF_EN_PULLUP [8:1] RW value= 0x0 */
/* REG_CLKMUX_FCLK_SEL [9:3] RW value= 0x0 */
/* REG_CLKMUX_PLL0_RFCLK0_SEL [12:2] RW value= 0x1 */
/* REG_CLKMUX_PLL0_RFCLK1_SEL [14:2] RW value= 0x1 */
/* REG_CLKMUX_SPARE0 [16:16] RW value= 0xf000 */
#endif
#if !defined (LIBERO_SETTING_DYN_CNTL)
/*Dynamic control registers */
#define LIBERO_SETTING_DYN_CNTL 0x00000000UL
/* REG_PLL_DYNEN [0:1] RW value= 0x0 */
/* REG_DLL_DYNEN [1:1] RW value= 0x0 */
/* REG_PVT_DYNEN [2:1] RW value= 0x0 */
/* REG_BC_DYNEN [3:1] RW value= 0x0 */
/* REG_CLKMUX_DYNEN [4:1] RW value= 0x0 */
/* REG_LANE0_DYNEN [5:1] RW value= 0x0 */
/* REG_LANE1_DYNEN [6:1] RW value= 0x0 */
/* BC_VRGEN_OOR [7:1] RO */
/* REG_PLL_SOFT_RESET_PERIPH [8:1] RW value= 0x0 */
/* REG_DLL_SOFT_RESET_PERIPH [9:1] RW value= 0x0 */
/* REG_PVT_SOFT_RESET_PERIPH [10:1] RW value= 0x0 */
/* REG_BC_SOFT_RESET_PERIPH [11:1] RW value= 0x0 */
/* REG_CLKMUX_SOFT_RESET_PERIPH [12:1] RW value= 0x0 */
/* REG_LANE0_SOFT_RESET_PERIPH [13:1] RW value= 0x0 */
/* REG_LANE1_SOFT_RESET_PERIPH [14:1] RW value= 0x0 */
/* PVT_CALIB_STATUS [15:1] RO */
/* ARO_PLL0_VCO0PH_SEL [16:3] RO */
/* ARO_PLL0_VCO1PH_SEL [19:3] RO */
/* ARO_PLL0_VCO2PH_SEL [22:3] RO */
/* ARO_PLL0_VCO3PH_SEL [25:3] RO */
/* ARO_REF_DIFFR [28:4] RO */
#endif
#if !defined (LIBERO_SETTING_PVT_STAT)
/*PVT calibrator status registers */
#define LIBERO_SETTING_PVT_STAT 0x00000000UL
/* ARO_REF_PCODE [0:6] RO */
/* ARO_IOEN_BNK [6:1] RO */
/* ARO_IOEN_BNK_B [7:1] RO */
/* ARO_REF_NCODE [8:6] RO */
/* ARO_CALIB_STATUS [14:1] RO */
/* ARO_CALIB_STATUS_B [15:1] RO */
/* ARO_PCODE [16:6] RO */
/* ARO_CALIB_INTRPT [22:1] RO */
/* PVT_CALIB_INTRPT [23:1] RO */
/* ARO_NCODE [24:6] RO */
/* PVT_CALIB_LOCK [30:1] RW value= 0x0 */
/* PVT_CALIB_START [31:1] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_SPARE_CNTL)
/*Spare control register */
#define LIBERO_SETTING_SPARE_CNTL 0xFF000000UL
/* REG_SPARE [0:32] RW value= 0xFF000000 */
#endif
#if !defined (LIBERO_SETTING_SPARE_STAT)
/*Spare status register */
#define LIBERO_SETTING_SPARE_STAT 0x00000000UL
/* SRO_SPARE [0:32] RO */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifdef HW_SGMII_TIP_H_ */

5
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/platform_config/drivers_config/readme.txt Normal file
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contains user configuration of the drivers.
drivers config should follow the following format:
platform/config/drivers/<same folder name as driver folder>/<driver name>_sw_cfg.h
e.g
platform/config/drivers/ddr/ddr_sw_cfg.h

325
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/platform_config/linker/mpfs-envm.ld Normal file
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/*******************************************************************************
*
* file name : mpfs_envm.ld
* Use with Bare metal startup code.
* Startup code runs from envm on MSS reset
*
* You can find details on the PolarFireSoC Memory map in the mpfs-memory-hierarchy.md
* which can be found under the link below:
* https://github.com/polarfire-soc/polarfire-soc-documentation
*
*/
OUTPUT_ARCH( "riscv" )
ENTRY(_start)
/*-----------------------------------------------------------------------------
-- MSS hart Reset vector
The MSS reset vector for each hart is stored securely in the MPFS.
The most common usage will be where the reset vector for each hart will be set
to the start of the envm at address 0x2022_0100, giving 128K-256B of contiguous
non-volatile storage. Normally this is where the initial boot-loader will
reside. (Note: The first 256B page of envm is used for metadata associated with
secure boot. When not using secure boot (mode 0,1), this area is still reserved
by convention. It allows easier transition from non-secure to secure boot flow
during the development process.
When debugging a bare metal program that is run out of reset from envm, a linker
script will be used whereby the program will run from LIM instead of envm.
In this case, the reset vector in the linker script is normally set to the
start of LIM, 0x0800_0000.
This means you are not continually programming the envm each time you load a
program and there is no limitation with break points when debugging.
See the mpfs-lim.ld example linker script when runing from LIM.
------------------------------------------------------------------------------*/
MEMORY
{
/* In this example, our reset vector is set to point to the */
/* start at page 1 of the envm */
envm (rx) : ORIGIN = 0x20220100, LENGTH = 128k - 0x100
dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k
e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k
u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k
u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k
u54_3_itim (rwx) : ORIGIN = 0x01818000, LENGTH = 28k
u54_4_itim (rwx) : ORIGIN = 0x01820000, LENGTH = 28k
l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 256k
scratchpad(rwx) : ORIGIN = 0x0A000000, LENGTH = 256k
/* This 1K of DTIM is used to run code when switching the envm clock */
switch_code_dtim (rx) : ORIGIN = 0x01001c00, LENGTH = 1k
/* DDR sections example */
ddr_cached_32bit (rwx) : ORIGIN = 0x80000000, LENGTH = 768M
ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 256M
ddr_wcb_32bit (rwx) : ORIGIN = 0xD0000000, LENGTH = 256M
ddr_cached_38bit (rwx) : ORIGIN = 0x1000000000, LENGTH = 1024M
ddr_non_cached_38bit (rwx) : ORIGIN = 0x1400000000, LENGTH = 0k
ddr_wcb_38bit (rwx) : ORIGIN = 0x1800000000, LENGTH = 0k
}
HEAP_SIZE = 8k; /* needs to be calculated for your application */
/* STACK_SIZE_PER_HART needs to be calculated for your */
/* application. Must be aligned */
/* Also Thread local storage (AKA hart local storage) allocated for each hart */
/* as part of the stack
/* So memory map will look like once apportion in startup code: */
/* */
/* stack hart0 Actual Stack size = (STACK_SIZE_PER_HART - HLS_DEBUG_AREA_SIZE) */
/* TLS hart 0 */
/* stack hart1 */
/* TLS hart 1 */
/* etc */
/* note: HLS_DEBUG_AREA_SIZE is defined in mss_sw_config.h */
STACK_SIZE_PER_HART = 8k;
/*
* Stack size for each hart's application.
* These are the stack sizes that will be allocated to each hart before starting
* each hart's application function, e51(), u54_1(), u54_2(), u54_3(), u54_4().
*/
STACK_SIZE_E51_APPLICATION = 8k;
STACK_SIZE_U54_1_APPLICATION = 8k;
STACK_SIZE_U54_2_APPLICATION = 8k;
STACK_SIZE_U54_3_APPLICATION = 8k;
STACK_SIZE_U54_4_APPLICATION = 8k;
SECTIONS
{
PROVIDE(__envm_start = ORIGIN(envm));
PROVIDE(__envm_end = ORIGIN(envm) + LENGTH(envm));
PROVIDE(__l2lim_start = ORIGIN(l2lim));
PROVIDE(__l2lim_end = ORIGIN(l2lim) + LENGTH(l2lim));
PROVIDE(__ddr_cached_32bit_start = ORIGIN(ddr_cached_32bit));
PROVIDE(__ddr_cached_32bit_end = ORIGIN(ddr_cached_32bit) + LENGTH(ddr_cached_32bit));
PROVIDE(__ddr_non_cached_32bit_start = ORIGIN(ddr_non_cached_32bit));
PROVIDE(__ddr_non_cached_32bit_end = ORIGIN(ddr_non_cached_32bit) + LENGTH(ddr_non_cached_32bit));
PROVIDE(__ddr_wcb_32bit_start = ORIGIN(ddr_wcb_32bit));
PROVIDE(__ddr_wcb_32bit_end = ORIGIN(ddr_wcb_32bit) + LENGTH(ddr_wcb_32bit));
PROVIDE(__ddr_cached_38bit_start = ORIGIN(ddr_cached_38bit));
PROVIDE(__ddr_cached_38bit_end = ORIGIN(ddr_cached_38bit) + LENGTH(ddr_cached_38bit));
PROVIDE(__ddr_non_cached_38bit_start = ORIGIN(ddr_non_cached_38bit));
PROVIDE(__ddr_non_cached_38bit_end = ORIGIN(ddr_non_cached_38bit) + LENGTH(ddr_non_cached_38bit));
PROVIDE(__ddr_wcb_38bit_start = ORIGIN(ddr_wcb_38bit));
PROVIDE(__ddr_wcb_38bit_end = ORIGIN(ddr_wcb_38bit) + LENGTH(ddr_wcb_38bit));
PROVIDE(__dtim_start = ORIGIN(dtim));
PROVIDE(__dtim_end = ORIGIN(dtim) + LENGTH(dtim));
PROVIDE(__e51itim_start = ORIGIN(e51_itim));
PROVIDE(__e51itim_end = ORIGIN(e51_itim) + LENGTH(e51_itim));
PROVIDE(__u54_1_itim_start = ORIGIN(u54_1_itim));
PROVIDE(__u54_1_itim_end = ORIGIN(u54_1_itim) + LENGTH(u54_1_itim));
PROVIDE(__u54_2_itim_start = ORIGIN(u54_2_itim));
PROVIDE(__u54_2_itim_end = ORIGIN(u54_2_itim) + LENGTH(u54_2_itim));
PROVIDE(__u54_3_itim_start = ORIGIN(u54_3_itim));
PROVIDE(__u54_3_itim_end = ORIGIN(u54_3_itim) + LENGTH(u54_3_itim));
PROVIDE(__u54_4_itim_start = ORIGIN(u54_4_itim));
PROVIDE(__u54_4_itim_end = ORIGIN(u54_4_itim) + LENGTH(u54_4_itim));
. = __envm_start;
.text : ALIGN(0x10)
{
__text_load = LOADADDR(.text);
__text_start = .;
*(.text.init)
/* *entry.o(.text); */
. = ALIGN(0x10);
*(.text .text.* .gnu.linkonce.t.*)
*(.plt)
. = ALIGN(0x10);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
*(.gcc_except_table)
*(.eh_frame_hdr)
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (__fini_array_end = .);
*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
*(.srodata*)
. = ALIGN(0x10);
__text_end = .;
} > envm
.l2_scratchpad : ALIGN(0x10)
{
__l2_scratchpad_load = LOADADDR(.l2_scratchpad);
__l2_scratchpad_start = .;
__l2_scratchpad_vma_start = .;
*(.l2_scratchpad)
. = ALIGN(0x10);
__l2_scratchpad_end = .;
__l2_scratchpad_vma_end = .;
} >scratchpad AT> envm
/*
* The .ram_code section will contain the code that is run from RAM.
* We are using this code to switch the clocks including envm clock.
* This can not be done when running from envm
* This will need to be copied to ram, before any of this code is run.
*/
.ram_code :
{
. = ALIGN (4);
__sc_load = LOADADDR (.ram_code);
__sc_start = .;
*(.ram_codetext) /* .ram_codetext sections (code) */
*(.ram_codetext*) /* .ram_codetext* sections (code) */
*(.ram_coderodata) /* read-only data (constants) */
*(.ram_coderodata*)
. = ALIGN (4);
__sc_end = .;
} >switch_code_dtim AT>envm
/*
* The .ddr_code section will contain the code that is run from DDR.
* This is to verify DDR working as expeted
*/
.ddr_code :
{
. = ALIGN (4);
__ddr_load = LOADADDR (.ram_code);
__ddr_start = .;
*(.ddr_codetext) /* .ram_codetext sections (code) */
*(.ddr_codetext*) /* .ram_codetext* sections (code) */
*(.ddr_coderodata) /* read-only data (constants) */
*(.ddr_coderodata*)
. = ALIGN (4);
__ddr_end = .;
} >ddr_cached_32bit AT>envm
/* short/global data section */
.sdata : ALIGN(0x10)
{
__sdata_load = LOADADDR(.sdata);
__sdata_start = .;
/* offset used with gp(gloabl pointer) are +/- 12 bits, so set
point to middle of expected sdata range */
/* If sdata more than 4K, linker used direct addressing.
Perhaps we should add check/warning to linker script if sdata is > 4k */
__global_pointer$ = . + 0x800;
*(.sdata .sdata.* .gnu.linkonce.s.*)
. = ALIGN(0x10);
__sdata_end = .;
} > l2lim AT > envm
/* data section */
.data : ALIGN(0x10)
{
__data_load = LOADADDR(.data);
__data_start = .;
*(.got.plt) *(.got)
*(.shdata)
*(.data .data.* .gnu.linkonce.d.*)
. = ALIGN(0x10);
__data_end = .;
} > l2lim AT > envm
/* sbss section */
.sbss : ALIGN(0x10)
{
__sbss_start = .;
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
. = ALIGN(0x10);
__sbss_end = .;
} > l2lim
/* sbss section */
.bss : ALIGN(0x10)
{
__bss_start = .;
*(.shbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(0x10);
__bss_end = .;
} > l2lim
/* End of uninitialized data segment */
_end = .;
.heap : ALIGN(0x10)
{
__heap_start = .;
. += HEAP_SIZE;
__heap_end = .;
. = ALIGN(0x10);
_heap_end = __heap_end;
} > l2lim
/* must be on 4k boundary (0x1000) - corresponds to page size, when using
memory mem */
/* protection */
/* .stack : ALIGN(0x1000) */
.stack : ALIGN(0x10)
{
PROVIDE(__stack_bottom_h0$ = .);
PROVIDE(__app_stack_bottom_h0 = .);
. += STACK_SIZE_E51_APPLICATION;
PROVIDE(__app_stack_top_h0 = .);
PROVIDE(__stack_top_h0$ = .);
PROVIDE(__stack_bottom_h1$ = .);
PROVIDE(__app_stack_bottom_h1$ = .);
. += STACK_SIZE_U54_1_APPLICATION;
PROVIDE(__app_stack_top_h1 = .);
PROVIDE(__stack_top_h1$ = .);
PROVIDE(__stack_bottom_h2$ = .);
PROVIDE(__app_stack_bottom_h2 = .);
. += STACK_SIZE_U54_2_APPLICATION;
PROVIDE(__app_stack_top_h2 = .);
PROVIDE(__stack_top_h2$ = .);
PROVIDE(__stack_bottom_h3$ = .);
PROVIDE(__app_stack_bottom_h3 = .);
. += STACK_SIZE_U54_3_APPLICATION;
PROVIDE(__app_stack_top_h3 = .);
PROVIDE(__stack_top_h3$ = .);
PROVIDE(__stack_bottom_h4$ = .);
PROVIDE(__app_stack_bottom_h4 = .);
. += STACK_SIZE_U54_4_APPLICATION;
PROVIDE(__app_stack_top_h4 = .);
PROVIDE(__stack_top_h4$ = .);
/* place __start_of_free_lim$ after last allocation of l2_lim */
. = ALIGN(0x10);
PROVIDE(__start_of_free_lim$ = .);
} > l2lim
}

298
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/platform_config/linker/mpfs-lim.ld Normal file
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@ -0,0 +1,298 @@
/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/*******************************************************************************
*
* file name : mpfs_lim.ld
* Used when debugging code. The debugger loads the code to LIM.
*
* You can find details on the PolarFireSoC Memory map in the mpfs-memory-hierarchy.md
* which can be found under the link below:
* https://github.com/polarfire-soc/polarfire-soc-documentation
*
*/
OUTPUT_ARCH( "riscv" )
ENTRY(_start)
/*-----------------------------------------------------------------------------
-- MSS hart Reset vector
The MSS reset vector for each hart is stored securely in the MPFS.
The most common usage will be where the reset vector for each hart will be set
to the start of the envm at address 0x2022_0100, giving 128K-256B of contiguous
non-volatile storage. Normally this is where the initial boot-loader will
reside. (Note: The first 256B page of envm is used for metadata associated with
secure boot. When not using secure boot (mode 0,1), this area is still reserved
by convention. It allows easier transition from non-secure to secure boot flow
during the development process.
When debugging a bare metal program that is run out of reset from envm, a linker
script will be used whereby the program will run from LIM instead of envm.
In this case, the reset vector in the linker script is normally set to the
start of LIM, 0x0800_0000.
This means you are not continually programming the envm each time you load a
program and there is no limitation with break points when debugging.
See the mpfs-lim.ld example linker script when runing from LIM.
------------------------------------------------------------------------------*/
MEMORY
{
envm (rx) : ORIGIN = 0x20220100, LENGTH = 128k - 0x100
dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k
switch_code (rx) : ORIGIN = 0x01001c00, LENGTH = 1k
e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k
u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k
u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k
u54_3_itim (rwx) : ORIGIN = 0x01818000, LENGTH = 28k
u54_4_itim (rwx) : ORIGIN = 0x01820000, LENGTH = 28k
l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 256k
scratchpad(rwx) : ORIGIN = 0x0A000000, LENGTH = 256k
/* DDR sections example */
ddr_cached_32bit (rwx) : ORIGIN = 0x80000000, LENGTH = 768M
ddr_non_cached_32bit (rwx) : ORIGIN = 0xC0000000, LENGTH = 256M
ddr_wcb_32bit (rwx) : ORIGIN = 0xD0000000, LENGTH = 256M
ddr_cached_38bit (rwx) : ORIGIN = 0x1000000000, LENGTH = 1024M
ddr_non_cached_38bit (rwx) : ORIGIN = 0x1400000000, LENGTH = 0k
ddr_wcb_38bit (rwx) : ORIGIN = 0x1800000000, LENGTH = 0k
}
HEAP_SIZE = 8k; /* needs to be calculated for your application if using */
/* STACK_SIZE_PER_HART needs to be calculated for your */
/* application. Must be aligned */
/* Also Thread local storage (AKA hart local storage) allocated for each hart */
/* as part of the stack
/* So memory map will look like once apportion in startup code: */
/* */
/* stack hart0 Actual Stack size = (STACK_SIZE_PER_HART - HLS_DEBUG_AREA_SIZE) */
/* TLS hart 0 */
/* stack hart1 */
/* TLS hart 1 */
/* etc */
/* note: HLS_DEBUG_AREA_SIZE is defined in mss_sw_config.h */
/* STACK_SIZE_PER_HART = 8k; */
/*
* Stack size for each hart's application.
* These are the stack sizes that will be allocated to each hart before starting
* each hart's application function, e51(), u54_1(), u54_2(), u54_3(), u54_4().
*/
STACK_SIZE_E51_APPLICATION = 8k;
STACK_SIZE_U54_1_APPLICATION = 8k;
STACK_SIZE_U54_2_APPLICATION = 8k;
STACK_SIZE_U54_3_APPLICATION = 8k;
STACK_SIZE_U54_4_APPLICATION = 8k;
SECTIONS
{
PROVIDE(__envm_start = ORIGIN(envm));
PROVIDE(__envm_end = ORIGIN(envm) + LENGTH(envm));
PROVIDE(__l2lim_start = ORIGIN(l2lim));
PROVIDE(__l2lim_end = ORIGIN(l2lim) + LENGTH(l2lim));
PROVIDE(__ddr_cached_32bit_start = ORIGIN(ddr_cached_32bit));
PROVIDE(__ddr_cached_32bit_end = ORIGIN(ddr_cached_32bit) + LENGTH(ddr_cached_32bit));
PROVIDE(__ddr_non_cached_32bit_start = ORIGIN(ddr_non_cached_32bit));
PROVIDE(__ddr_non_cached_32bit_end = ORIGIN(ddr_non_cached_32bit) + LENGTH(ddr_non_cached_32bit));
PROVIDE(__ddr_wcb_32bit_start = ORIGIN(ddr_wcb_32bit));
PROVIDE(__ddr_wcb_32bit_end = ORIGIN(ddr_wcb_32bit) + LENGTH(ddr_wcb_32bit));
PROVIDE(__ddr_cached_38bit_start = ORIGIN(ddr_cached_38bit));
PROVIDE(__ddr_cached_38bit_end = ORIGIN(ddr_cached_38bit) + LENGTH(ddr_cached_38bit));
PROVIDE(__ddr_non_cached_38bit_start = ORIGIN(ddr_non_cached_38bit));
PROVIDE(__ddr_non_cached_38bit_end = ORIGIN(ddr_non_cached_38bit) + LENGTH(ddr_non_cached_38bit));
PROVIDE(__ddr_wcb_38bit_start = ORIGIN(ddr_wcb_38bit));
PROVIDE(__ddr_wcb_38bit_end = ORIGIN(ddr_wcb_38bit) + LENGTH(ddr_wcb_38bit));
PROVIDE(__dtim_start = ORIGIN(dtim));
PROVIDE(__dtim_end = ORIGIN(dtim) + LENGTH(dtim));
PROVIDE(__e51itim_start = ORIGIN(e51_itim));
PROVIDE(__e51itim_end = ORIGIN(e51_itim) + LENGTH(e51_itim));
PROVIDE(__u54_1_itim_start = ORIGIN(u54_1_itim));
PROVIDE(__u54_1_itim_end = ORIGIN(u54_1_itim) + LENGTH(u54_1_itim));
PROVIDE(__u54_2_itim_start = ORIGIN(u54_2_itim));
PROVIDE(__u54_2_itim_end = ORIGIN(u54_2_itim) + LENGTH(u54_2_itim));
PROVIDE(__u54_3_itim_start = ORIGIN(u54_3_itim));
PROVIDE(__u54_3_itim_end = ORIGIN(u54_3_itim) + LENGTH(u54_3_itim));
PROVIDE(__u54_4_itim_start = ORIGIN(u54_4_itim));
PROVIDE(__u54_4_itim_end = ORIGIN(u54_4_itim) + LENGTH(u54_4_itim));
/* text: text code section */
. = __l2lim_start;
.text : ALIGN(0x10)
{
__text_load = LOADADDR(.text);
__text_start = .;
*(.text.init)
. = ALIGN(0x10);
*(.text .text.* .gnu.linkonce.t.*)
*(.plt)
. = ALIGN(0x10);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
*(.gcc_except_table)
*(.eh_frame_hdr)
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (__fini_array_end = .);
*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
*(.srodata*)
. = ALIGN(0x10);
__text_end = .;
. = ALIGN(0x10);
} > l2lim
.l2_scratchpad : ALIGN(0x10)
{
. = ALIGN (0x10);
__l2_scratchpad_load = LOADADDR(.l2_scratchpad);
__l2_scratchpad_start = .;
__l2_scratchpad_vma_start = .;
*(.l2_scratchpad)
. = ALIGN(0x10);
__l2_scratchpad_end = .;
__l2_scratchpad_vma_end = .;
} >scratchpad AT> l2lim
/*
* The .ram_code section will contain the code That is run from RAM.
* We are using this code to switch the clocks including eNVM clock.
* This can not be done when running from eNVM
* This will need to be copied to ram, before any of this code is run.
*/
.ram_code :
{
. = ALIGN (4);
__sc_load = LOADADDR (.ram_code);
__sc_start = .;
*(.ram_codetext) /* .ram_codetext sections (code) */
*(.ram_codetext*) /* .ram_codetext* sections (code) */
*(.ram_coderodata) /* read-only data (constants) */
*(.ram_coderodata*)
. = ALIGN (4);
__sc_end = .;
} >switch_code AT> l2lim /* On the MPFS for startup code use, >switch_code AT>eNVM */
/* short/global data section */
.sdata : ALIGN(0x10)
{
__sdata_load = LOADADDR(.sdata);
__sdata_start = .;
/* offset used with gp(gloabl pointer) are +/- 12 bits, so set point to middle of expected sdata range */
/* If sdata more than 4K, linker used direct addressing. Perhaps we should add check/warning to linker script if sdata is > 4k */
__global_pointer$ = . + 0x800;
*(.sdata .sdata.* .gnu.linkonce.s.*)
. = ALIGN(0x10);
__sdata_end = .;
} > l2lim
/* data section */
.data : ALIGN(0x10)
{
__data_load = LOADADDR(.data);
__data_start = .;
*(.got.plt) *(.got)
*(.shdata)
*(.data .data.* .gnu.linkonce.d.*)
. = ALIGN(0x10);
__data_end = .;
} > l2lim
/* sbss section */
.sbss : ALIGN(0x10)
{
__sbss_start = .;
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
. = ALIGN(0x10);
__sbss_end = .;
} > l2lim
/* sbss section */
.bss : ALIGN(0x10)
{
__bss_start = .;
*(.shbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(0x10);
__bss_end = .;
} > l2lim
/* End of uninitialized data segment */
_end = .;
.heap : ALIGN(0x10)
{
__heap_start = .;
. += HEAP_SIZE;
__heap_end = .;
. = ALIGN(0x10);
_heap_end = __heap_end;
} > l2lim
/* must be on 4k boundary- corresponds to page size */
.stack : ALIGN(0x1000)
{
PROVIDE(__stack_bottom_h0$ = .);
PROVIDE(__app_stack_bottom_h0 = .);
. += STACK_SIZE_E51_APPLICATION;
PROVIDE(__app_stack_top_h0 = .);
PROVIDE(__stack_top_h0$ = .);
PROVIDE(__stack_bottom_h1$ = .);
PROVIDE(__app_stack_bottom_h1$ = .);
. += STACK_SIZE_U54_1_APPLICATION;
PROVIDE(__app_stack_top_h1 = .);
PROVIDE(__stack_top_h1$ = .);
PROVIDE(__stack_bottom_h2$ = .);
PROVIDE(__app_stack_bottom_h2 = .);
. += STACK_SIZE_U54_2_APPLICATION;
PROVIDE(__app_stack_top_h2 = .);
PROVIDE(__stack_top_h2$ = .);
PROVIDE(__stack_bottom_h3$ = .);
PROVIDE(__app_stack_bottom_h3 = .);
. += STACK_SIZE_U54_3_APPLICATION;
PROVIDE(__app_stack_top_h3 = .);
PROVIDE(__stack_top_h3$ = .);
PROVIDE(__stack_bottom_h4$ = .);
PROVIDE(__app_stack_bottom_h4 = .);
. += STACK_SIZE_U54_4_APPLICATION;
PROVIDE(__app_stack_top_h4 = .);
PROVIDE(__stack_top_h4$ = .);
} > l2lim
}

197
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/platform_config/mpfs_hal_config/mss_sw_config.h Normal file
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/*******************************************************************************
*
* Platform definitions
* Version based on requirements of MPFS MSS
*
*/
/*========================================================================*//**
@mainpage Sample file detailing how mss_sw_config.h should be constructed for
the MPFS MSS
@section intro_sec Introduction
The mss_sw_config.h has the default software configuration settings for the
MPFS HAL and will be located at
<Project-Name>/src/platform/platform_config_reference folder of the bare
metal SoftConsole project. The platform_config_reference is provided as a
default reference configuration.
When you want to configure the MPFS HAL with required configuration for
your project, the mss_sw_config.h must be edited and be placed in the
following project directory:
<Project-Name>/src/boards/<your-board>/platform_config/mpfs_hal_config/
@section
*//*==========================================================================*/
#ifndef MSS_SW_CONFIG_H_
#define MSS_SW_CONFIG_H_
/*
* MPFS_HAL_FIRST_HART and MPFS_HAL_LAST_HART defines are used to specify which
* harts to actually start. The value and the actual hart it represents are
* listed below:
* value hart
* 0 E51
* 1 U54_1
* 2 U54_2
* 3 U54_3
* 4 U54_4
* Set MPFS_HAL_FIRST_HART to a value greater than 0 if you do not want your
* application to start and execute code on the harts represented by smaller
* value numbers.
* Set MPFS_HAL_LAST_HART to a value smaller than 4 if you do not wish to use
* all U54_x harts.
* Harts that are not started will remain in an infinite WFI loop unless used
* through some other method.
* The value of MPFS_HAL_FIRST_HART must always be less than MPFS_HAL_LAST_HART.
* The value of MPFS_HAL_LAST_HART must never be greater than 4.
* A typical use-case where you set MPFS_HAL_FIRST_HART = 1 and
* MPFS_HAL_LAST_HART = 1 is when
* your application is running on U54_1 and a bootloader running on E51 loads
* your application to the target memory and kicks-off U54_1 to run it.
*/
#ifndef MPFS_HAL_FIRST_HART
#define MPFS_HAL_FIRST_HART 0
#endif
#ifndef MPFS_HAL_LAST_HART
#define MPFS_HAL_LAST_HART 4
#endif
/*
* IMAGE_LOADED_BY_BOOTLOADER
* We set IMAGE_LOADED_BY_BOOTLOADER = 0 if the application image runs from
* non-volatile memory after reset. (No previous stage bootloader is used.)
* Set IMAGE_LOADED_BY_BOOTLOADER = 1 if the application image is loaded by a
* previous stage bootloader.
*
* MPFS_HAL_HW_CONFIG is defined if we are a boot-loader. This is a
* conditional compile switch is used to determine if MPFS HAL will perform the
* hardware configurations or not.
* Defined => This program acts as a First stage bootloader and performs
* hardware configurations.
* Not defined => This program assumes that the hardware configurations are
* already performed (Typically by a previous boot stage)
*
* List of items initialised when MPFS_HAL_HW_CONFIG is enabled
* - load virtual rom (see load_virtual_rom(void) in system_startup.c)
* - l2 cache config
* - Bus error unit config
* - MPU config
* - pmp config
* - I/O, clock and clock mux's, DDR and SGMII
* - will start other harts, see text describing MPFS_HAL_FIRST_HART,
* MPFS_HAL_LAST_HART above
*
*/
#define IMAGE_LOADED_BY_BOOTLOADER 0
#if (IMAGE_LOADED_BY_BOOTLOADER == 0)
#define MPFS_HAL_HW_CONFIG
#endif
/*
* If you are using common memory for sharing across harts,
* uncomment #define MPFS_HAL_SHARED_MEM_ENABLED
* make sure common memory is allocated in the linker script
* See app_hart_common mem section in the example platform
* linker scripts.
*/
#define MPFS_HAL_SHARED_MEM_ENABLED
/* define the required tick rate in Milliseconds */
/* if this program is running on one hart only, only that particular hart value
* will be used */
#define HART0_TICK_RATE_MS 5UL
#define HART1_TICK_RATE_MS 5UL
#define HART2_TICK_RATE_MS 5UL
#define HART3_TICK_RATE_MS 5UL
#define HART4_TICK_RATE_MS 5UL
/*
* Define the size of the Hart Local Storage (HLS).
* In the MPFS HAL, we are using HLS for debug data storage during the initial
* boot phase.
* This includes the flags which indicate the hart state regarding boot state.
* The HLS will take memory from top of each stack allocated at boot time.
*
*/
#define HLS_DEBUG_AREA_SIZE 64
/*
* Bus Error Unit (BEU) configurations
* BEU_ENABLE => Configures the events that the BEU can report. bit value
* 1= enabled, 0 = disabled.
* BEU_PLIC_INT => Configures which accrued events should generate an
* interrupt to the PLIC.
* BEU_LOCAL_INT => Configures which accrued events should generate a
* local interrupt to the hart on which the event accrued.
*/
#define BEU_ENABLE 0x0ULL
#define BEU_PLIC_INT 0x0ULL
#define BEU_LOCAL_INT 0x0ULL
/*
* Clear memory on startup
* 0 => do not clear DTIM and L2
* 1 => Clears memory
* Note: If you are the zero stage bootloader, set this to one.
*/
#ifndef MPFS_HAL_CLEAR_MEMORY
#define MPFS_HAL_CLEAR_MEMORY 1
#endif
/*
* Comment out the lines to disable the corresponding hardware support not required
* in your application.
* This is not necessary from an operational point of view as operation dictated
* by MSS configurator settings, and items are enabled/disabled by this method.
* The reason you may want to use below is to save code space.
*/
//#define SGMII_SUPPORT
//#define DDR_SUPPORT
#define MSSIO_SUPPORT
/*
* DDR software options
*/
/*
* Debug DDR startup through a UART
* Comment out in normal operation. May be useful for debug purposes in bring-up
* of a new board design.
* See the weakly linked function setup_ddr_debug_port(mss_uart_instance_t * uart)
* If you need to edit this function, make another copy of the function in your
* application without the weak linking attribute. This copy will then get linked.
* */
//#define DEBUG_DDR_INIT
//#define DEBUG_DDR_RD_RW_FAIL
//#define DEBUG_DDR_RD_RW_PASS
//#define DEBUG_DDR_CFG_DDR_SGMII_PHY
//#define DEBUG_DDR_DDRCFG
/*
* The hardware configuration settings imported from Libero project get generated
* into <project_name>/src/boards/<your-board>/<fpga-design-config> folder.
* If you need to overwrite them for testing purposes, you can do so here.
* e.g. If you want change the default SEG registers configuration defined by
* LIBERO_SETTING_SEG0_0, define it here and it will take precedence.
* #define LIBERO_SETTING_SEG0_0 0x80007F80UL
*
*/
#endif /* USER_CONFIG_MSS_USER_CONFIG_H_ */

2
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/platform_config/mpfs_hal_config/readme.txt Normal file
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contains user configuration of the platform
e.g. division of memory between harts etc.

481
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/platform/drivers/mss/mss_gpio/mss_gpio.c Normal file
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/*******************************************************************************
* Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* PolarFire SoC microprocessor subsystem GPIO bare metal driver implementation.
*
* This driver is based on SmartFusion2 MSS GPIO driver v2.1.102
*
*/
#include <drivers/mss/mss_gpio/mss_gpio.h>
#include "mpfs_hal/mss_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
/*-------------------------------------------------------------------------*//**
* Defines.
*/
#define GPIO_INT_ENABLE_MASK ((uint32_t)0x00000008)
#define OUTPUT_BUFFER_ENABLE_MASK ((uint32_t)0x00000004)
/*These constants define the number of GPIO bits available on each GPIO
* hardware block*/
#define NB_OF_GPIO_GPIO0 ((uint32_t)14)
#define NB_OF_GPIO_GPIO1 ((uint32_t)24)
#define NB_OF_GPIO_GPIO2 ((uint32_t)32)
/*This constant indicates the total number of GPIO interrupt inputs at the PLIC
* (includes the direct and non-direct GPIO interrupts)*/
#define NB_OF_GPIO_INTR ((uint32_t)41)
/*-------------------------------------------------------------------------*//**
* Lookup table of GPIO interrupt number indexed on GPIO ID.
* The GPIO interrupts are multiplexed. Total GPIO interrupts are 41.
* 41 = (14 from GPIO0 + 24 from GPIO1 + 3 non direct interrupts)
* GPIO2 interrupts are not available by default. Setting the corresponding bit
* in GPIO_INTERRUPT_FAB_CR(31:0) will enable GPIO2(31:0) corresponding
* interrupt on PLIC.
*
* PLIC GPIO_INTERRUPT_FAB_CR
0 1
0 GPIO0 bit 0 GPIO2 bit 0
1 GPIO0 bit 1 GPIO2 bit 1
.
.
12 GPIO0 bit 12 GPIO2 bit 12
13 GPIO0 bit 13 GPIO2 bit 13
14 GPIO1 bit 0 GPIO2 bit 14
15 GPIO1 bit 1 GPIO2 bit 15
.
.
.
30 GPIO1 bit 16 GPIO2 bit 30
31 GPIO1 bit 17 GPIO2 bit 31
32 GPIO1 bit 18
33 GPIO1 bit 19
34 GPIO1 bit 20
35 GPIO1 bit 21
36 GPIO1 bit 22
37 GPIO1 bit 23
38 Or of all GPIO0 interrupts who do not have a direct connection enabled
39 Or of all GPIO1 interrupts who do not have a direct connection enabled
40 Or of all GPIO2 interrupts who do not have a direct connection enabled
*
*/
static const PLIC_IRQn_Type g_gpio_irqn_lut[NB_OF_GPIO_INTR] =
{
GPIO0_BIT0_or_GPIO2_BIT0_PLIC_0,
GPIO0_BIT1_or_GPIO2_BIT1_PLIC_1,
GPIO0_BIT2_or_GPIO2_BIT2_PLIC_2,
GPIO0_BIT3_or_GPIO2_BIT3_PLIC_3,
GPIO0_BIT4_or_GPIO2_BIT4_PLIC_4,
GPIO0_BIT5_or_GPIO2_BIT5_PLIC_5,
GPIO0_BIT6_or_GPIO2_BIT6_PLIC_6,
GPIO0_BIT7_or_GPIO2_BIT7_PLIC_7,
GPIO0_BIT8_or_GPIO2_BIT8_PLIC_8,
GPIO0_BIT9_or_GPIO2_BIT9_PLIC_9,
GPIO0_BIT10_or_GPIO2_BIT10_PLIC_10,
GPIO0_BIT11_or_GPIO2_BIT11_PLIC_11,
GPIO0_BIT12_or_GPIO2_BIT12_PLIC_12,
GPIO0_BIT13_or_GPIO2_BIT13_PLIC_13,
GPIO1_BIT0_or_GPIO2_BIT14_PLIC_14,
GPIO1_BIT1_or_GPIO2_BIT15_PLIC_15,
GPIO1_BIT2_or_GPIO2_BIT16_PLIC_16,
GPIO1_BIT3_or_GPIO2_BIT17_PLIC_17,
GPIO1_BIT4_or_GPIO2_BIT18_PLIC_18,
GPIO1_BIT5_or_GPIO2_BIT19_PLIC_19,
GPIO1_BIT6_or_GPIO2_BIT20_PLIC_20,
GPIO1_BIT7_or_GPIO2_BIT21_PLIC_21,
GPIO1_BIT8_or_GPIO2_BIT22_PLIC_22,
GPIO1_BIT9_or_GPIO2_BIT23_PLIC_23,
GPIO1_BIT10_or_GPIO2_BIT24_PLIC_24,
GPIO1_BIT11_or_GPIO2_BIT25_PLIC_25,
GPIO1_BIT12_or_GPIO2_BIT26_PLIC_26,
GPIO1_BIT13_or_GPIO2_BIT27_PLIC_27,
GPIO1_BIT14_or_GPIO2_BIT28_PLIC_28,
GPIO1_BIT15_or_GPIO2_BIT29_PLIC_29,
GPIO1_BIT16_or_GPIO2_BIT30_PLIC_30,
GPIO1_BIT17_or_GPIO2_BIT31_PLIC_31,
GPIO1_BIT18_PLIC_32,
GPIO1_BIT19_PLIC_33,
GPIO1_BIT20_PLIC_34,
GPIO1_BIT21_PLIC_35,
GPIO1_BIT22_PLIC_36,
GPIO1_BIT23_PLIC_37,
GPIO0_NON_DIRECT_PLIC,
GPIO1_NON_DIRECT_PLIC,
GPIO2_NON_DIRECT_PLIC
};
/*-------------------------------------------------------------------------*//**
* Local functions
*/
static uint8_t gpio_number_validate(GPIO_TypeDef const * gpio, mss_gpio_id_t gpio_idx);
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_init
* See "mss_gpio.h" for details of how to use this function.
*/
void
MSS_GPIO_init
(
GPIO_TypeDef * gpio
)
{
/* clear all pending interrupts*/
gpio->GPIO_IRQ = 0xFFFFFFFFU;
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_config
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_config
(
GPIO_TypeDef * gpio,
mss_gpio_id_t port_id,
uint32_t config
)
{
if (0U == gpio_number_validate(gpio, port_id))
{
gpio->GPIO_CFG[port_id] = config;
}
else
{
ASSERT(0); /*LDRA warning*/
}
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_config_byte
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_config_byte
(
GPIO_TypeDef * gpio,
mss_gpio_byte_num_t byte_num,
uint32_t config
)
{
if (((GPIO0_LO == gpio) || (GPIO0_HI == gpio)) &&
(byte_num >= MSS_GPIO_BYTE_1))
{
ASSERT(0);
}
else if (((GPIO1_LO == gpio) || (GPIO1_HI == gpio)) &&
(byte_num > MSS_GPIO_BYTE_2))
{
ASSERT(0);
}
else if (((GPIO2_LO == gpio) || (GPIO2_HI == gpio)) &&
(byte_num > MSS_GPIO_BYTE_3))
{
ASSERT(0);
}
else
{
gpio->GPIO_CFG_BYTE[byte_num] = config;
}
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_config_all
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_config_all
(
GPIO_TypeDef * gpio,
uint32_t config
)
{
gpio->GPIO_CFG_ALL = config;
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_set_output
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_set_output
(
GPIO_TypeDef * gpio,
mss_gpio_id_t port_id,
uint8_t value
)
{
uint32_t gpio_setting;
if (0U == gpio_number_validate(gpio, port_id))
{
/* Setting the bit in GPIO_SET_BITS (offset 0xA4) sets the corresponding
* output port.
* Setting the bit in GPIO_CLR_BITS (offset 0xA0) clears the
* corresponding output port.*/
if (value > 0u)
{
gpio->GPIO_SET_BITS = ((uint32_t)0x01 << port_id);
}
else
{
gpio->GPIO_CLR_BITS = ((uint32_t)0x01 << port_id);
}
}
else
{
ASSERT(0); /*LDRA warning*/
}
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_drive_inout
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_drive_inout
(
GPIO_TypeDef * gpio,
mss_gpio_id_t port_id,
mss_gpio_inout_state_t inout_state
)
{
uint32_t outputs_state;
uint32_t config;
if (0U == gpio_number_validate(gpio, port_id))
{
switch (inout_state)
{
case MSS_GPIO_DRIVE_HIGH:
/* Set output high */
gpio->GPIO_SET_BITS = ((uint32_t)1 << port_id);
/* Enable output buffer */
config = gpio->GPIO_CFG[port_id];
config |= OUTPUT_BUFFER_ENABLE_MASK;
gpio->GPIO_CFG[port_id] = config;
break;
case MSS_GPIO_DRIVE_LOW:
/* Set output low */
gpio->GPIO_CLR_BITS = (uint32_t)1 << port_id;
/* Enable output buffer */
config = gpio->GPIO_CFG[port_id];
config |= OUTPUT_BUFFER_ENABLE_MASK;
gpio->GPIO_CFG[port_id] = config;
break;
case MSS_GPIO_HIGH_Z:
/* Disable output buffer */
config = gpio->GPIO_CFG[port_id];
config &= ~OUTPUT_BUFFER_ENABLE_MASK;
gpio->GPIO_CFG[port_id] = config;
break;
default:
ASSERT(0);
break;
}
}
else
{
ASSERT(0); /*LDRA warning*/
}
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_enable_irq
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_enable_irq
(
GPIO_TypeDef * gpio,
mss_gpio_id_t port_id
)
{
uint32_t cfg_value;
if (0U == gpio_number_validate(gpio, port_id))
{
cfg_value = gpio->GPIO_CFG[(uint8_t)port_id];
gpio->GPIO_CFG[(uint8_t)port_id] = (cfg_value | GPIO_INT_ENABLE_MASK);
if ((GPIO0_LO == gpio) || (GPIO0_HI == gpio))
{
PLIC_EnableIRQ(g_gpio_irqn_lut[port_id]);
}
else if ((GPIO1_LO == gpio) || (GPIO1_HI == gpio))
{
PLIC_EnableIRQ(g_gpio_irqn_lut[port_id +
GPIO1_BIT0_or_GPIO2_BIT14_PLIC_14]);
}
else if ((GPIO2_LO == gpio) || (GPIO2_HI == gpio))
{
PLIC_EnableIRQ(g_gpio_irqn_lut[port_id]);
}
else
{
ASSERT(0); /*LDRA warning*/
}
}
else
{
ASSERT(0); /*LDRA warning*/
}
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_disable_irq
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_disable_irq
(
GPIO_TypeDef * gpio,
mss_gpio_id_t port_id
)
{
uint32_t cfg_value;
if (0U == gpio_number_validate(gpio, port_id))
{
cfg_value = gpio->GPIO_CFG[(uint8_t)port_id];
gpio->GPIO_CFG[(uint8_t)port_id] = (cfg_value & (~GPIO_INT_ENABLE_MASK));
if ((GPIO0_LO == gpio) || (GPIO0_HI == gpio))
{
PLIC_DisableIRQ(g_gpio_irqn_lut[port_id]);
}
else if ((GPIO1_LO == gpio) || (GPIO1_HI == gpio))
{
PLIC_DisableIRQ(g_gpio_irqn_lut[port_id +
GPIO1_BIT0_or_GPIO2_BIT14_PLIC_14]);
}
else if ((GPIO2_LO == gpio) || (GPIO2_HI == gpio))
{
PLIC_DisableIRQ(GPIO2_NON_DIRECT_PLIC);
}
else
{
ASSERT(0); /*LDRA warning*/
}
}
else
{
ASSERT(0); /*LDRA warning*/
}
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_enable_nondirect_irq
* See "mss_gpio.h" for details of how to use this function.
*/
void
MSS_GPIO_enable_nondirect_irq
(
GPIO_TypeDef const * gpio
)
{
if ((GPIO0_LO == gpio) || (GPIO0_HI == gpio))
{
PLIC_EnableIRQ(GPIO0_NON_DIRECT_PLIC);
}
else if ((GPIO1_LO == gpio) || (GPIO1_HI == gpio))
{
PLIC_EnableIRQ(GPIO1_NON_DIRECT_PLIC);
}
else if ((GPIO2_LO == gpio) || (GPIO2_HI == gpio))
{
PLIC_EnableIRQ(GPIO2_NON_DIRECT_PLIC);
}
else
{
ASSERT(0); /*LDRA warning*/
}
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_disable_nondirect_irq
* See "mss_gpio.h" for details of how to use this function.
*/
void
MSS_GPIO_disable_nondirect_irq
(
GPIO_TypeDef const * gpio
)
{
if ((GPIO0_LO == gpio) || (GPIO0_HI == gpio))
{
PLIC_DisableIRQ(GPIO0_NON_DIRECT_PLIC);
}
else if ((GPIO1_LO == gpio) || (GPIO1_HI == gpio))
{
PLIC_DisableIRQ(GPIO1_NON_DIRECT_PLIC);
}
else if ((GPIO2_LO == gpio) || (GPIO2_HI == gpio))
{
PLIC_DisableIRQ(GPIO2_NON_DIRECT_PLIC);
}
else
{
ASSERT(0); /*LDRA warning*/
}
}
/*-------------------------------------------------------------------------*//**
* MSS_GPIO_clear_irq
* See "mss_gpio.h" for details of how to use this function.
*/
void MSS_GPIO_clear_irq
(
GPIO_TypeDef * gpio,
mss_gpio_id_t port_id
)
{
if (0U == gpio_number_validate(gpio, port_id))
{
gpio->GPIO_IRQ = ((uint32_t)1) << port_id;
__asm("fence");
}
else
{
ASSERT(0); /*LDRA warning*/
}
}
static uint8_t gpio_number_validate(GPIO_TypeDef const * gpio, mss_gpio_id_t gpio_idx)
{
uint8_t ret;
if (((GPIO0_LO == gpio) || (GPIO0_HI == gpio)) &&
(gpio_idx >= NB_OF_GPIO_GPIO0))
{
ret = 1u;
}
else if (((GPIO1_LO == gpio) || (GPIO1_HI == gpio)) &&
(gpio_idx >= NB_OF_GPIO_GPIO1))
{
ret = 1u;
}
else if (((GPIO2_LO == gpio) || (GPIO2_HI == gpio)) &&
(gpio_idx >= NB_OF_GPIO_GPIO2))
{
ret = 1u;
}
else
{
ret = 0u;
}
return ret;
}
#ifdef __cplusplus
}
#endif

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/*******************************************************************************
* Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* Register bit offsets and masks definitions for PolarFire SoC MSS MMUART
*
*/
#ifndef MSS_UART_REGS_H_
#define MSS_UART_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
Register Bit definitions
*/
/* Line Control register bit definitions */
#define SB 6u /* Set break */
#define DLAB 7u /* Divisor latch access bit */
/* Line Control register bit masks */
#define SB_MASK (0x01u << SB) /* Set break */
#define DLAB_MASK (0x01u << DLAB) /* Divisor latch access bit */
/* FIFO Control register bit definitions */
#define RXRDY_TXRDYN_EN 0u /* Enable TXRDY and RXRDY signals */
#define CLEAR_RX_FIFO 1u /* Clear receiver FIFO */
#define CLEAR_TX_FIFO 2u /* Clear transmitter FIFO */
#define RDYMODE 3u /* Mode 0 or Mode 1 for TXRDY and RXRDY */
/* FIFO Control register bit MASKS */
#define RXRDY_TXRDYN_EN_MASK (0x01u << 0u) /* Enable TXRDY and RXRDY signals */
#define CLEAR_RX_FIFO_MASK (0x01u << 1u) /* Clear receiver FIFO */
#define CLEAR_TX_FIFO_MASK (0x01u << 2u) /* Clear transmitter FIFO */
#define RDYMODE_MASK (0x01u << 3u) /* Mode 0 or Mode 1 for TXRDY and RXRDY */
/* Modem Control register bit definitions */
#define LOOP 4u /* Local loopback */
#define RLOOP 5u /* Remote loopback */
#define ECHO 6u /* Automatic echo */
/* Modem Control register bit MASKS */
#define LOOP_MASK (0x01u << 4u) /* Local loopback */
#define RLOOP_MASK (0x01u << 5u) /* Remote loopback & Automatic echo*/
#define ECHO_MASK (0x01u << 6u) /* Automatic echo */
/* Line Status register bit definitions */
#define DR 0u /* Data ready */
#define THRE 5u /* Transmitter holding register empty */
#define TEMT 6u /* Transmitter empty */
/* Line Status register bit MASKS */
#define DR_MASK (0x01u << 0u) /* Data ready */
#define THRE_MASK (0x01u << 5u) /* Transmitter holding register empty */
#define TEMT_MASK (0x01u << 6u) /* Transmitter empty */
/* Interrupt Enable register bit definitions */
#define ERBFI 0u /* Enable receiver buffer full interrupt */
#define ETBEI 1u /* Enable transmitter buffer empty interrupt */
#define ELSI 2u /* Enable line status interrupt */
#define EDSSI 3u /* Enable modem status interrupt */
/* Interrupt Enable register bit MASKS */
#define ERBFI_MASK (0x01u << 0u) /* Enable receiver buffer full interrupt */
#define ETBEI_MASK (0x01u << 1u) /* Enable transmitter buffer empty interrupt */
#define ELSI_MASK (0x01u << 2u) /* Enable line status interrupt */
#define EDSSI_MASK (0x01u << 3u) /* Enable modem status interrupt */
/* Multimode register 0 bit definitions */
#define ELIN 3u /* Enable LIN header detection */
#define ETTG 5u /* Enable transmitter time guard */
#define ERTO 6u /* Enable receiver time-out */
#define EFBR 7u /* Enable fractional baud rate mode */
/* Multimode register 0 bit MASKS */
#define ELIN_MASK (0x01u << 3u) /* Enable LIN header detection */
#define ETTG_MASK (0x01u << 5u) /* Enable transmitter time guard */
#define ERTO_MASK (0x01u << 6u) /* Enable receiver time-out */
#define EFBR_MASK (0x01u << 7u) /* Enable fractional baud rate mode */
/* Multimode register 1 bit definitions */
#define E_MSB_RX 0u /* MSB / LSB first for receiver */
#define E_MSB_TX 1u /* MSB / LSB first for transmitter */
#define EIRD 2u /* Enable IrDA modem */
#define EIRX 3u /* Input polarity for IrDA modem */
#define EITX 4u /* Output polarity for IrDA modem */
#define EITP 5u /* Output pulse width for IrDA modem */
/* Multimode register 1 bit MASKS */
#define E_MSB_RX_MASK (0x01u << 0u) /* MSB / LSB first for receiver */
#define E_MSB_TX_MASK (0x01u << 1u) /* MSB / LSB first for transmitter */
#define EIRD_MASK (0x01u << 2u) /* Enable IrDA modem */
#define EIRX_MASK (0x01u << 3u) /* Input polarity for IrDA modem */
#define EITX_MASK (0x01u << 4u) /* Output polarity for IrDA modem */
#define EITP_MASK (0x01u << 5u) /* Output pulse width for IrDA modem */
/* Multimode register 2 bit definitions */
#define EERR 0u /* Enable ERR / NACK during stop time */
#define EAFM 1u /* Enable 9-bit address flag mode */
#define EAFC 2u /* Enable address flag clear */
#define ESWM 3u /* Enable single wire half-duplex mode */
/* Multimode register 2 bit MASKS */
#define EERR_MASK (0x01u << 0u) /* Enable ERR / NACK during stop time */
#define EAFM_MASK (0x01u << 1u) /* Enable 9-bit address flag mode */
#define EAFC_MASK (0x01u << 2u) /* Enable address flag clear */
#define ESWM_MASK (0x01u << 3u) /* Enable single wire half-duplex mode */
/* Multimode Interrupt Enable register and
Multimode Interrupt Identification register definitions */
#define ERTOI 0u /* Enable receiver timeout interrupt */
#define ENACKI 1u /* Enable NACK / ERR interrupt */
#define EPID_PEI 2u /* Enable PID parity error interrupt */
#define ELINBI 3u /* Enable LIN break interrupt */
#define ELINSI 4u /* Enable LIN sync detection interrupt */
/* Multimode Interrupt Enable register and
Multimode Interrupt Identification register MASKS */
#define ERTOI_MASK (0x01u << 0u) /* Enable receiver timeout interrupt */
#define ENACKI_MASK (0x01u << 1u) /* Enable NACK / ERR interrupt */
#define EPID_PEI_MASK (0x01u << 2u) /* Enable PID parity error interrupt */
#define ELINBI_MASK (0x01u << 3u) /* Enable LIN break interrupt */
#define ELINSI_MASK (0x01u << 4u) /* Enable LIN sync detection interrupt */
#ifdef __cplusplus
}
#endif
#endif /* MSS_UART_REGS_H_ */

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/*******************************************************************************
* Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
#ifndef CPU_TYPES_H
#define CPU_TYPES_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef unsigned long size_t;
/*------------------------------------------------------------------------------
* addr_t: address type.
* Used to specify the address of peripherals present in the processor's memory
* map.
*/
typedef unsigned long addr_t;
/*------------------------------------------------------------------------------
* psr_t: processor state register.
* Used by HAL_disable_interrupts() and HAL_restore_interrupts() to store the
* processor's state between disabling and restoring interrupts.
*/
typedef unsigned long psr_t;
#ifdef __cplusplus
}
#endif
#endif /* CPU_TYPES_H */

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/***************************************************************************//**
* Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
* deal in the Software without restriction, including without limitation the
* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*
* MPFS HAL Embedded Software
*
*/
/***************************************************************************//**
*
* Hardware abstraction layer functions.
*
* Legacy register interrupt functions
* Pointers are now recommended for use in drivers
*
*/
#ifndef HAL_H
#define HAL_H
#ifdef __cplusplus
extern "C" {
#endif
#include "cpu_types.h"
#include "hw_reg_access.h"
#include "hal/hal_assert.h"
/***************************************************************************//**
* Enable all interrupts at the processor level.
*/
void HAL_enable_interrupts( void );
/***************************************************************************//**
* Disable all interrupts at the processor core level.
* Return the interrupts enable state before disabling occurred so that it can
* later be restored.
*/
psr_t HAL_disable_interrupts( void );
/***************************************************************************//**
* Restore the interrupts enable state at the processor core level.
* This function is normally passed the value returned from a previous call to
* HAL_disable_interrupts().
*/
void HAL_restore_interrupts( psr_t saved_psr );
/***************************************************************************//**
*/
#define FIELD_OFFSET(FIELD_NAME) (FIELD_NAME##_OFFSET)
#define FIELD_SHIFT(FIELD_NAME) (FIELD_NAME##_SHIFT)
#define FIELD_MASK(FIELD_NAME) (FIELD_NAME##_MASK)
/***************************************************************************//**
* The macro HAL_set_32bit_reg() allows writing a 32 bits wide register.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* REG_NAME: A string identifying the register to write. These strings are
* specified in a header file associated with the peripheral.
* VALUE: A variable of type uint32_t containing the value to write.
*/
#define HAL_set_32bit_reg(BASE_ADDR, REG_NAME, VALUE) \
(HW_set_32bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))
/***************************************************************************//**
* The macro HAL_get_32bit_reg() is used to read the value of a 32 bits wide
* register.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* REG_NAME: A string identifying the register to read. These strings are
* specified in a header file associated with the peripheral.
* RETURN: This function-like macro returns a uint32_t value.
*/
#define HAL_get_32bit_reg(BASE_ADDR, REG_NAME) \
(HW_get_32bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)) ))
/***************************************************************************//**
* The macro HAL_set_32bit_reg_field() is used to write a field within a
* 32 bits wide register. The field written can be one or more bits.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* FIELD_NAME: A string identifying the register field to write. These strings
* are specified in a header file associated with the peripheral.
* VALUE: A variable of type uint32_t containing the field value to write.
*/
#define HAL_set_32bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \
(HW_set_32bit_reg_field(\
(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
FIELD_SHIFT(FIELD_NAME),\
FIELD_MASK(FIELD_NAME),\
(VALUE)))
/***************************************************************************//**
* The macro HAL_get_32bit_reg_field() is used to read a register field from
* within a 32 bit wide peripheral register. The field can be one or more bits.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* FIELD_NAME: A string identifying the register field to write. These strings
* are specified in a header file associated with the peripheral.
* RETURN: This function-like macro returns a uint32_t value.
*/
#define HAL_get_32bit_reg_field(BASE_ADDR, FIELD_NAME) \
(HW_get_32bit_reg_field(\
(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
FIELD_SHIFT(FIELD_NAME),\
FIELD_MASK(FIELD_NAME)))
/***************************************************************************//**
* The macro HAL_set_16bit_reg() allows writing a 16 bits wide register.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* REG_NAME: A string identifying the register to write. These strings are
* specified in a header file associated with the peripheral.
* VALUE: A variable of type uint_fast16_t containing the value to write.
*/
#define HAL_set_16bit_reg(BASE_ADDR, REG_NAME, VALUE) \
(HW_set_16bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))
/***************************************************************************//**
* The macro HAL_get_16bit_reg() is used to read the value of a 16 bits wide
* register.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* REG_NAME: A string identifying the register to read. These strings are
* specified in a header file associated with the peripheral.
* RETURN: This function-like macro returns a uint16_t value.
*/
#define HAL_get_16bit_reg(BASE_ADDR, REG_NAME) \
(HW_get_16bit_reg( (BASE_ADDR) + (REG_NAME##_REG_OFFSET) ))
/***************************************************************************//**
* The macro HAL_set_16bit_reg_field() is used to write a field within a
* 16 bits wide register. The field written can be one or more bits.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* FIELD_NAME: A string identifying the register field to write. These strings
* are specified in a header file associated with the peripheral.
* VALUE: A variable of type uint16_t containing the field value to write.
*/
#define HAL_set_16bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \
(HW_set_16bit_reg_field(\
(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
FIELD_SHIFT(FIELD_NAME),\
FIELD_MASK(FIELD_NAME),\
(VALUE)))
/***************************************************************************//**
* The macro HAL_get_16bit_reg_field() is used to read a register field from
* within a 8 bit wide peripheral register. The field can be one or more bits.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* FIELD_NAME: A string identifying the register field to write. These strings
* are specified in a header file associated with the peripheral.
* RETURN: This function-like macro returns a uint16_t value.
*/
#define HAL_get_16bit_reg_field(BASE_ADDR, FIELD_NAME) \
(HW_get_16bit_reg_field(\
(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
FIELD_SHIFT(FIELD_NAME),\
FIELD_MASK(FIELD_NAME)))
/***************************************************************************//**
* The macro HAL_set_8bit_reg() allows writing a 8 bits wide register.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* REG_NAME: A string identifying the register to write. These strings are
* specified in a header file associated with the peripheral.
* VALUE: A variable of type uint_fast8_t containing the value to write.
*/
#define HAL_set_8bit_reg(BASE_ADDR, REG_NAME, VALUE) \
(HW_set_8bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))
/***************************************************************************//**
* The macro HAL_get_8bit_reg() is used to read the value of a 8 bits wide
* register.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* REG_NAME: A string identifying the register to read. These strings are
* specified in a header file associated with the peripheral.
* RETURN: This function-like macro returns a uint8_t value.
*/
#define HAL_get_8bit_reg(BASE_ADDR, REG_NAME) \
(HW_get_8bit_reg( (BASE_ADDR) + (REG_NAME##_REG_OFFSET) ))
/***************************************************************************//**
*/
#define HAL_set_8bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \
(HW_set_8bit_reg_field(\
(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
FIELD_SHIFT(FIELD_NAME),\
FIELD_MASK(FIELD_NAME),\
(VALUE)))
/***************************************************************************//**
* The macro HAL_get_8bit_reg_field() is used to read a register field from
* within a 8 bit wide peripheral register. The field can be one or more bits.
*
* BASE_ADDR: A variable of type addr_t specifying the base address of the
* peripheral containing the register.
* FIELD_NAME: A string identifying the register field to write. These strings
* are specified in a header file associated with the peripheral.
* RETURN: This function-like macro returns a uint8_t value.
*/
#define HAL_get_8bit_reg_field(BASE_ADDR, FIELD_NAME) \
(HW_get_8bit_reg_field(\
(BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
FIELD_SHIFT(FIELD_NAME),\
FIELD_MASK(FIELD_NAME)))
#ifdef __cplusplus
}
#endif
#endif /*HAL_H*/

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/*******************************************************************************
* Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
#ifndef HAL_ASSERT_HEADER
#define HAL_ASSERT_HEADER
#ifdef __cplusplus
extern "C" {
#endif
/***************************************************************************//**
* ASSERT() implementation.
******************************************************************************/
/* Disable assertions if we do not recognize the compiler. */
#if defined ( __GNUC__ )
#if defined(NDEBUG)
#define ASSERT(CHECK)
#else
#define ASSERT(CHECK)\
do { \
if (!(CHECK)) \
{ \
__asm volatile ("ebreak"); \
}\
} while(0);
#endif /* NDEBUG check */
#endif /* compiler check */
#if defined(NDEBUG)
/***************************************************************************//**
* HAL_ASSERT() is defined out when the NDEBUG symbol is used.
******************************************************************************/
#define HAL_ASSERT(CHECK)
#else
/***************************************************************************//**
* Default behaviour for HAL_ASSERT() macro:
*------------------------------------------------------------------------------
The behaviour is toolchain specific and project setting specific.
******************************************************************************/
#define HAL_ASSERT(CHECK) ASSERT(CHECK);
#endif /* NDEBUG */
#ifdef __cplusplus
}
#endif
#endif /* HAL_ASSERT_HEADER */

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/*******************************************************************************
* Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/***************************************************************************//**
*
* Legacy interrupt control functions for the Microchip driver library hardware
* abstraction layer.
*
*/
#include <stdio.h>
#include "hal/hal.h"
#include "mpfs_hal/common/mss_util.h"
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------
*
*/
void HAL_enable_interrupts(void) {
__enable_irq();
}
/*------------------------------------------------------------------------------
*
*/
psr_t HAL_disable_interrupts(void) {
psr_t psr;
psr = read_csr(mstatus);
__disable_irq();
return(psr);
}
/*------------------------------------------------------------------------------
*
*/
void HAL_restore_interrupts(psr_t saved_psr) {
write_csr(mstatus, saved_psr);
}
#ifdef __cplusplus
}
#endif

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#ifndef HAL_VERSION_H
#define HAL_VERSION_H
/*******************************************************************************
* Copyright 2019-2020 Microchip Corporation.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
* deal in the Software without restriction, including without limitation the
* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*
*
*
*/
/*******************************************************************************
* @file mpfs_halversion.h
* @author Microchip-FPGA Embedded Systems Solutions
* @brief MICROCHIP FPGA Embedded Software Hardware Abstraction layer - HAL
*
*/
#ifdef __cplusplus
extern "C" {
#endif
#define HAL_VERSION_MAJOR 1
#define HAL_VERSION_MINOR 8
#define HAL_VERSION_PATCH 0
#ifdef __cplusplus
}
#endif
#endif

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/*******************************************************************************
* Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/*******************************************************************************
*
* Hardware registers access macros.
*
* THE MACROS DEFINED IN THIS FILE ARE DEPRECATED. DO NOT USE FOR NEW
* DEVELOPMENT.
*
* These macros are used to access peripheral registers. They allow access to
* 8, 16 and 32 bit wide registers. All accesses to peripheral registers should
* be done through these macros in order to ease porting across different
* processors/bus architectures.
*
* Some of these macros also allow access to a specific register field.
*
*/
#ifndef HW_MACROS_H
#define HW_MACROS_H
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------
* 32 bits registers access:
*/
#define HW_get_uint32_reg(BASE_ADDR, REG_OFFSET) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
#define HW_set_uint32_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
#define HW_set_uint32_reg_field(BASE_ADDR, FIELD, VALUE) \
(*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
( \
(uint32_t) \
( \
(*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
(uint32_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
) \
)
#define HW_get_uint32_reg_field( BASE_ADDR, FIELD ) \
(( (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
/*------------------------------------------------------------------------------
* 32 bits memory access:
*/
#define HW_get_uint32(BASE_ADDR) (*((uint32_t volatile *)(BASE_ADDR)))
#define HW_set_uint32(BASE_ADDR, VALUE) (*((uint32_t volatile *)(BASE_ADDR)) = (VALUE))
/*------------------------------------------------------------------------------
* 16 bits registers access:
*/
#define HW_get_uint16_reg(BASE_ADDR, REG_OFFSET) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
#define HW_set_uint16_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
#define HW_set_uint16_reg_field(BASE_ADDR, FIELD, VALUE) \
(*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
( \
(uint16_t) \
( \
(*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
(uint16_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
) \
)
#define HW_get_uint16_reg_field( BASE_ADDR, FIELD ) \
(( (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
/*------------------------------------------------------------------------------
* 8 bits registers access:
*/
#define HW_get_uint8_reg(BASE_ADDR, REG_OFFSET) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
#define HW_set_uint8_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
#define HW_set_uint8_reg_field(BASE_ADDR, FIELD, VALUE) \
(*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) = \
( \
(uint8_t) \
( \
(*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
(uint8_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
) \
)
#define HW_get_uint8_reg_field( BASE_ADDR, FIELD ) \
(( (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
/*------------------------------------------------------------------------------
* 8 bits memory access:
*/
#define HW_get_uint8(BASE_ADDR) (*((uint8_t volatile *)(BASE_ADDR)))
#define HW_set_uint8(BASE_ADDR, VALUE) (*((uint8_t volatile *)(BASE_ADDR)) = (VALUE))
#ifdef __cplusplus
extern "C" {
#endif
#endif /* HW_MACROS_ */

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/***************************************************************************//**
* Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
* Hardware registers access functions.
* The implementation of these function is platform and toolchain specific.
* The functions declared here are implemented using assembler as part of the
* processor/toolchain specific HAL.
*
*/
.section .text
.globl HW_set_32bit_reg
.globl HW_get_32bit_reg
.globl HW_set_32bit_reg_field
.globl HW_get_32bit_reg_field
.globl HW_set_16bit_reg
.globl HW_get_16bit_reg
.globl HW_set_16bit_reg_field
.globl HW_get_16bit_reg_field
.globl HW_set_8bit_reg
.globl HW_get_8bit_reg
.globl HW_set_8bit_reg_field
.globl HW_get_8bit_reg_field
/***************************************************************************//**
* HW_set_32bit_reg is used to write the content of a 32 bits wide peripheral
* register.
*
* a0: addr_t reg_addr
* a1: uint32_t value
*/
HW_set_32bit_reg:
sw a1, 0(a0)
ret
/***************************************************************************//**
* HW_get_32bit_reg is used to read the content of a 32 bits wide peripheral
* register.
*
* a0: addr_t reg_addr
* @return 32 bits value read from the peripheral register.
*/
HW_get_32bit_reg:
lw a0, 0(a0)
ret
/***************************************************************************//**
* HW_set_32bit_reg_field is used to set the content of a field in a 32 bits
* wide peripheral register.
*
* a0: addr_t reg_addr
* a1: int_fast8_t shift
* a2: uint32_t mask
* a3: uint32_t value
*/
HW_set_32bit_reg_field:
mv t3, a3
sll t3, t3, a1
and t3, t3, a2
lw t1, 0(a0)
mv t2, a2
not t2, t2
and t1, t1, t2
or t1, t1, t3
sw t1, 0(a0)
ret
/***************************************************************************//**
* HW_get_32bit_reg_field is used to read the content of a field out of a
* 32 bits wide peripheral register.
*
* a0: addr_t reg_addr
* a1: int_fast8_t shift
* a2: uint32_t mask
*
* @return 32 bits value containing the register field value specified
* as parameter.
*/
HW_get_32bit_reg_field:
lw a0, 0(a0)
and a0, a0, a2
srl a0, a0, a1
ret
/***************************************************************************//**
* HW_set_16bit_reg is used to write the content of a 16 bits wide peripheral
* register.
*
* a0: addr_t reg_addr
* a1: uint_fast16_t value
*/
HW_set_16bit_reg:
sh a1, 0(a0)
ret
/***************************************************************************//**
* HW_get_16bit_reg is used to read the content of a 16 bits wide peripheral
* register.
*
* a0: addr_t reg_addr
* @return 16 bits value read from the peripheral register.
*/
HW_get_16bit_reg:
lh a0, (a0)
ret
/***************************************************************************//**
* HW_set_16bit_reg_field is used to set the content of a field in a 16 bits
* wide peripheral register.
*
* a0: addr_t reg_addr
* a1: int_fast8_t shift
* a2: uint_fast16_t mask
* a3: uint_fast16_t value
* @param value Value to be written in the specified field.
*/
HW_set_16bit_reg_field:
mv t3, a3
sll t3, t3, a1
and t3, t3, a2
lh t1, 0(a0)
mv t2, a2
not t2, t2
and t1, t1, t2
or t1, t1, t3
sh t1, 0(a0)
ret
/***************************************************************************//**
* HW_get_16bit_reg_field is used to read the content of a field from a
* 16 bits wide peripheral register.
*
* a0: addr_t reg_addr
* a1: int_fast8_t shift
* a2: uint_fast16_t mask
*
* @return 16 bits value containing the register field value specified
* as parameter.
*/
HW_get_16bit_reg_field:
lh a0, 0(a0)
and a0, a0, a2
srl a0, a0, a1
ret
/***************************************************************************//**
* HW_set_8bit_reg is used to write the content of a 8 bits wide peripheral
* register.
*
* a0: addr_t reg_addr
* a1: uint_fast8_t value
*/
HW_set_8bit_reg:
sb a1, 0(a0)
ret
/***************************************************************************//**
* HW_get_8bit_reg is used to read the content of a 8 bits wide peripheral
* register.
*
* a0: addr_t reg_addr
* @return 8 bits value read from the peripheral register.
*/
HW_get_8bit_reg:
lb a0, 0(a0)
ret
/***************************************************************************//**
* HW_set_8bit_reg_field is used to set the content of a field in a 8 bits
* wide peripheral register.
*
* a0: addr_t reg_addr,
* a1: int_fast8_t shift
* a2: uint_fast8_t mask
* a3: uint_fast8_t value
*/
HW_set_8bit_reg_field:
mv t3, a3
sll t3, t3, a1
and t3, t3, a2
lb t1, 0(a0)
mv t2, a2
not t2, t2
and t1, t1, t2
or t1, t1, t3
sb t1, 0(a0)
ret
/***************************************************************************//**
* HW_get_8bit_reg_field is used to read the content of a field from a
* 8 bits wide peripheral register.
*
* a0: addr_t reg_addr
* a1: int_fast8_t shift
* a2: uint_fast8_t mask
*
* @return 8 bits value containing the register field value specified
* as parameter.
*/
HW_get_8bit_reg_field:
lb a0, 0(a0)
and a0, a0, a2
srl a0, a0, a1
ret
.end

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/*******************************************************************************
* Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/***************************************************************************//**
*
* Hardware registers access functions.
* The implementation of these function is platform and tool-chain specific.
* The functions declared here are implemented using assembler as part of the
* processor/tool-chain specific HAL.
*
*/
#ifndef HW_REG_ACCESS
#define HW_REG_ACCESS
#ifdef __cplusplus
extern "C" {
#endif
#include "cpu_types.h"
/***************************************************************************//**
* HW_set_32bit_reg is used to write the content of a 32 bits wide peripheral
* register.
*
* @param reg_addr Address in the processor's memory map of the register to
* write.
* @param value Value to be written into the peripheral register.
*/
void
HW_set_32bit_reg
(
addr_t reg_addr,
uint32_t value
);
/***************************************************************************//**
* HW_get_32bit_reg is used to read the content of a 32 bits wide peripheral
* register.
*
* @param reg_addr Address in the processor's memory map of the register to
* read.
* @return 32 bits value read from the peripheral register.
*/
uint32_t
HW_get_32bit_reg
(
addr_t reg_addr
);
/***************************************************************************//**
* HW_set_32bit_reg_field is used to set the content of a field in a 32 bits
* wide peripheral register.
*
* @param reg_addr Address in the processor's memory map of the register to
* be written.
* @param shift Bit offset of the register field to be read within the
* register.
* @param mask Bit mask to be applied to the raw register value to filter
* out the other register fields values.
* @param value Value to be written in the specified field.
*/
void
HW_set_32bit_reg_field
(
addr_t reg_addr,
int_fast8_t shift,
uint32_t mask,
uint32_t value
);
/***************************************************************************//**
* HW_get_32bit_reg_field is used to read the content of a field out of a
* 32 bits wide peripheral register.
*
* @param reg_addr Address in the processor's memory map of the register to
* read.
* @param shift Bit offset of the register field to be written within the
* register.
* @param mask Bit mask to be applied to the raw register value to filter
* out the other register fields values.
*
* @return 32 bits value containing the register field value specified
* as parameter.
*/
uint32_t
HW_get_32bit_reg_field
(
addr_t reg_addr,
int_fast8_t shift,
uint32_t mask
);
/***************************************************************************//**
* HW_set_16bit_reg is used to write the content of a 16 bits wide peripheral
* register.
*
* @param reg_addr Address in the processor's memory map of the register to
* write.
* @param value Value to be written into the peripheral register.
*/
void
HW_set_16bit_reg
(
addr_t reg_addr,
uint_fast16_t value
);
/***************************************************************************//**
* HW_get_16bit_reg is used to read the content of a 16 bits wide peripheral
* register.
*
* @param reg_addr Address in the processor's memory map of the register to
* read.
* @return 16 bits value read from the peripheral register.
*/
uint16_t
HW_get_16bit_reg
(
addr_t reg_addr
);
/***************************************************************************//**
* HW_set_16bit_reg_field is used to set the content of a field in a 16 bits
* wide peripheral register.
*
* @param reg_addr Address in the processor's memory map of the register to
* be written.
* @param shift Bit offset of the register field to be read within the
* register.
* @param mask Bit mask to be applied to the raw register value to filter
* out the other register fields values.
* @param value Value to be written in the specified field.
*/
void HW_set_16bit_reg_field
(
addr_t reg_addr,
int_fast8_t shift,
uint_fast16_t mask,
uint_fast16_t value
);
/***************************************************************************//**
* HW_get_16bit_reg_field is used to read the content of a field from a
* 16 bits wide peripheral register.
*
* @param reg_addr Address in the processor's memory map of the register to
* read.
* @param shift Bit offset of the register field to be written within the
* register.
* @param mask Bit mask to be applied to the raw register value to filter
* out the other register fields values.
*
* @return 16 bits value containing the register field value specified
* as parameter.
*/
uint16_t HW_get_16bit_reg_field
(
addr_t reg_addr,
int_fast8_t shift,
uint_fast16_t mask
);
/***************************************************************************//**
* HW_set_8bit_reg is used to write the content of a 8 bits wide peripheral
* register.
*
* @param reg_addr Address in the processor's memory map of the register to
* write.
* @param value Value to be written into the peripheral register.
*/
void
HW_set_8bit_reg
(
addr_t reg_addr,
uint_fast8_t value
);
/***************************************************************************//**
* HW_get_8bit_reg is used to read the content of a 8 bits wide peripheral
* register.
*
* @param reg_addr Address in the processor's memory map of the register to
* read.
* @return 8 bits value read from the peripheral register.
*/
uint8_t
HW_get_8bit_reg
(
addr_t reg_addr
);
/***************************************************************************//**
* HW_set_8bit_reg_field is used to set the content of a field in a 8 bits
* wide peripheral register.
*
* @param reg_addr Address in the processor's memory map of the register to
* be written.
* @param shift Bit offset of the register field to be read within the
* register.
* @param mask Bit mask to be applied to the raw register value to filter
* out the other register fields values.
* @param value Value to be written in the specified field.
*/
void HW_set_8bit_reg_field
(
addr_t reg_addr,
int_fast8_t shift,
uint_fast8_t mask,
uint_fast8_t value
);
/***************************************************************************//**
* HW_get_8bit_reg_field is used to read the content of a field from a
* 8 bits wide peripheral register.
*
* @param reg_addr Address in the processor's memory map of the register to
* read.
* @param shift Bit offset of the register field to be written within the
* register.
* @param mask Bit mask to be applied to the raw register value to filter
* out the other register fields values.
*
* @return 8 bits value containing the register field value specified
* as parameter.
*/
uint8_t HW_get_8bit_reg_field
(
addr_t reg_addr,
int_fast8_t shift,
uint_fast8_t mask
);
#ifdef __cplusplus
}
#endif
#endif /* HW_REG_ACCESS */

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===============================================================================
# hal folder
===============================================================================
The HAL folder provides support code for use by the bare metal drivers for the
fabric IP cores.
The HAL folder contains files using a combination of C and assembly source code.
The hal folder should be included in a PolarFire SoC Embedded project under the
platform directory. See location in the drawing below.
The hal folder contains:
* register access functions
* assert macros
### Project directory strucutre, showing where hal folder sits.
+---------+ +-----------+
| src +----->|application|
+---------+ | +-----------+
|
| +-----------+
+-->|modules |
| +-----------+
|
| +-----------+ +---------+
+-->|platform +---->|config |
+-----------+ | +---------+
|
| +---------+
+->|drivers |
| +---------+
|
| +---------+
+->|hal |
| +---------+
|
| +---------+
+->|mpfs_hal |
+---------+

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/*
Copyright (c) 2013, The Regents of the University of California (Regents).
All Rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Regents nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
*/
/***********************************************************************************
* Record of Microchip changes
*/
#ifndef RISCV_ATOMIC_H
#define RISCV_ATOMIC_H
#ifdef __cplusplus
extern "C" {
#endif
#define mb() asm volatile ("fence" ::: "memory")
#define atomic_set(ptr, val) (*(volatile typeof(*(ptr)) *)(ptr) = val)
#define atomic_read(ptr) (*(volatile typeof(*(ptr)) *)(ptr))
#ifdef __riscv_atomic
# define atomic_swap(ptr, swp) __sync_lock_test_and_set(ptr, swp)
# define atomic_or(ptr, inc) __sync_fetch_and_or(ptr, inc)
#else
#define atomic_binop(ptr, inc, op) ({ \
long flags = disable_irqsave(); \
typeof(*(ptr)) res = atomic_read(ptr); \
atomic_set(ptr, op); \
enable_irqrestore(flags); \
res; })
#define atomic_or(ptr, inc) atomic_binop(ptr, inc, res | (inc))
#define atomic_swap(ptr, swp) atomic_binop(ptr, swp, (swp))
#endif
#ifdef __cplusplus
}
#endif
#endif //RISCV_ATOMIC_H

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/*
Copyright (c) 2013, The Regents of the University of California (Regents).
All Rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Regents nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
*/
/***********************************************************************************
* Record of Microchip changes
*/
#ifndef RISCV_BITS_H
#define RISCV_BITS_H
#ifdef __cplusplus
extern "C" {
#endif
#define likely(x) __builtin_expect((x), 1)
#define unlikely(x) __builtin_expect((x), 0)
#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
#define ROUNDDOWN(a, b) ((a)/(b)*(b))
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
#define STR(x) XSTR(x)
#define XSTR(x) #x
#if __riscv_xlen == 64
# define SLL32 sllw
# define STORE sd
# define LOAD ld
# define LWU lwu
# define LOG_REGBYTES 3
#else
# define SLL32 sll
# define STORE sw
# define LOAD lw
# define LWU lw
# define LOG_REGBYTES 2
#endif
#define REGBYTES (1 << LOG_REGBYTES)
#ifdef __cplusplus
}
#endif
#endif //RISCV_BITS_H

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
#ifndef HAL_ASSERT_HEADER
#define HAL_ASSERT_HEADER
#ifdef __cplusplus
extern "C" {
#endif
/***************************************************************************//**
* ASSERT() implementation.
******************************************************************************/
/* Disable assertions if we do not recognize the compiler. */
#if defined ( __GNUC__ )
#if defined(NDEBUG)
#define ASSERT(CHECK)
#else
#define ASSERT(CHECK)\
do { \
if (!(CHECK)) \
{ \
__asm volatile ("ebreak"); \
}\
} while(0);
#endif /* NDEBUG check */
#endif /* compiler check */
#ifdef __cplusplus
}
#endif
#endif /* HAL_ASSERT_HEADER */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/*******************************************************************************
* @file mss_axiswitch.c
* @author Microchip-FPGA Embedded Systems Solutions
* @brief PolarFire SoC MSS AXI switch configuration
*
*/
#include <stddef.h>
#include <stdint.h>
#include "mpfs_hal/mss_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
/*Returns the value of AXI_HW_CFG_REG register*/
uint32_t MSS_AXISW_get_hwcfg(void)
{
return (AXISW->HWCFG);
}
/*Returns the value of AXI_VERSION_ID_REG register*/
uint32_t MSS_AXISW_get_vid(void)
{
return (AXISW->VID);
}
/*Performs write operation on the AXI SWITCH APB interface,
* Parameters:
* master_port_num = AXI Master Port number. See Enum mss_axisw_mport_t above.
Note: QoS values are programmable through registers only for AXI3 configurations.
We have AXI4 so the QoS value programming should not be attempted.
IF you try to write/read QoS value you will get return value =1 (AXI_ERR_BIT)
Burstiness peak rate and transaction rate can be configured using other APIs.
data: QoS value to be programmed
return value: As received form AXI_ERR_BIT in CMD register.
* */
uint32_t MSS_AXISW_write_qos_val(mss_axisw_mport_t master_port_num,
uint32_t data)
{
while(AXISW->CMD & AXISW_CMD_EN_MASK); /*make sure previous command completed*/
AXISW->DATA = data & AXISW_DATA_QOSVAL_MASK; /*only valid values of bits[3:0]*/
AXISW->CMD = (AXISW_CMD_RW_MASK |
(master_port_num << AXISW_CMD_RWCHAN) |
MSS_AXISW_QOS_VAL |
AXISW_CMD_EN_MASK);
while(AXISW->CMD & AXISW_CMD_EN_MASK); /*Wait for command to complete*/
return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR); /*return error bit value*/
}
/*Performs read operation on the AXI SWITCH APB interface,
* Parameters:
* master_port_num = AXI Master Port number. See Enum mss_axisw_mport_t above.
*
* Note: QoS values are programmable through registers only for AXI3 configurations.
We have AXI4 so the QoS value programming should not be attempted.
IF you try to write/read QoS value you will get return value =1 (AXI_ERR_BIT)
*
* returns the data returned by AXI SWITCH read operation for QoS command
*
* return value: As received form AXI_ERR_BIT in CMD register.
*/
uint32_t MSS_AXISW_read_qos_val(mss_axisw_mport_t master_port_num,
uint32_t* rd_data)
{
while(AXISW->CMD & AXISW_CMD_EN_MASK);
AXISW->CMD &= ~(AXISW_CMD_RW_MASK); /*Clear read/write bit*/
AXISW->CMD = ((master_port_num << AXISW_CMD_RWCHAN) | (MSS_AXISW_QOS_VAL) | AXISW_CMD_EN_MASK);
while(AXISW->CMD & AXISW_CMD_EN_MASK);
*rd_data = AXISW->DATA & AXISW_DATA_QOSVAL_MASK;
return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR); /*return error bit value*/
}
/* Programs the peak rate and transaction rate value for the given master port
read/write address channel
NOTE: Peak rate and transaction rate are programmed simultaneously in one command.
So we must make sure that both desired valid values must be provided.
* return value: As received form AXI_ERR_BIT in CMD register.
*/
uint32_t MSS_AXISW_write_rate(mss_axisw_mport_t master_port_num,
mss_axisw_rate_t peak_rate,
mss_axisw_rate_t xct_rate)
{
while(AXISW->CMD & AXISW_CMD_EN_MASK); /*make sure previous command completed*/
AXISW->DATA = ((peak_rate) << AXISW_DATA_PEAKRT) | ((xct_rate) << AXISW_DATA_XCTRT) ;
AXISW->CMD = (AXISW_CMD_RW_MASK |
(master_port_num << AXISW_CMD_RWCHAN) |
(MSS_AXISW_PEAKRT_XCTRT) |
AXISW_CMD_EN_MASK);
while(AXISW->CMD & AXISW_CMD_EN_MASK); /*Wait for command to complete*/
return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR); /*return error bit value*/
}
/* Reads the peak rate and transaction rate value for the given master port
read/write address channel
peak_rate: returns the value of peak rate
xct_rate: returns the value of transaction rate
return value: As received form AXI_ERR_BIT in CMD register.
*/
uint32_t MSS_AXISW_read_rate(mss_axisw_mport_t master_port_num,
mss_axisw_rate_t* peak_rate,
mss_axisw_rate_t* xct_rate)
{
uint32_t temp = 0u;
while(AXISW->CMD & AXISW_CMD_EN_MASK);
AXISW->CMD &= ~(AXISW_CMD_RW_MASK); /*Clear read/write and command EN bit*/
AXISW->CMD = ((master_port_num << AXISW_CMD_RWCHAN) |
(MSS_AXISW_PEAKRT_XCTRT) |
AXISW_CMD_EN_MASK);
while(AXISW->CMD & AXISW_CMD_EN_MASK);
temp = AXISW->DATA;
*peak_rate = (temp & AXISW_DATA_PEAKRT_MASK) >> AXISW_DATA_PEAKRT;
*xct_rate = (temp & AXISW_DATA_XCTRT_MASK) >> AXISW_DATA_XCTRT;
return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR); /*return error bit value*/
}
/* Programs the burstiness value for the given master port read/write address channel
burstiness_val: burstiness value to be programmed
NOTE: Burstiness value formula as mentioned in AXISW document is Burstiness = DataReg[23:16] + 1
regulator_en: QoS regulator Enable 1= enable, 0 = disable
* return value: As received form AXI_ERR_BIT in CMD register.
*/
int32_t MSS_AXISW_write_burstiness(mss_axisw_mport_t master_port_num,
uint32_t burstiness_val,
uint32_t regulator_en)
{
while(AXISW->CMD & AXISW_CMD_EN_MASK); /*make sure previous command completed*/
/*Write burstiness value and enable burstiness regulator.
* Burstiness_val=0 is not valid.
Burstiness value formula as mentioned in AXISW document is Burstiness = DataReg[23:16] + 1*/
if(burstiness_val == 0)
{
return -1;
}
else
{
AXISW->DATA = ((burstiness_val - 1u) << AXISW_DATA_BURSTI) | (regulator_en & 0x01);
}
AXISW->CMD = (AXISW_CMD_RW_MASK |
(master_port_num << AXISW_CMD_RWCHAN) |
(MSS_AXISW_BURSTINESS_EN) |
AXISW_CMD_EN_MASK);
while(AXISW->CMD & AXISW_CMD_EN_MASK); /*Wait for command to complete*/
return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR); /*return error bit value*/
}
/* Reads the burstiness value for the given master port read/write address channel
burstiness_val: Return parameter bit 23:16 shows the burstiness value.
NOTE: Burstiness value formula as mentioned in AXISW document is Burstiness = DataReg[23:16] + 1
* return value: As received form AXI_ERR_BIT in CMD register.
*/
uint32_t MSS_AXISW_read_burstiness(mss_axisw_mport_t master_port_num,
uint32_t* burstiness_val)
{
while(AXISW->CMD & AXISW_CMD_EN_MASK);
AXISW->CMD &= ~(AXISW_CMD_RW_MASK); /*Clear read/write and command EN bit*/
AXISW->CMD = ((master_port_num << AXISW_CMD_RWCHAN) |
(MSS_AXISW_BURSTINESS_EN) |
AXISW_CMD_EN_MASK);
while(AXISW->CMD & AXISW_CMD_EN_MASK);
*burstiness_val = ((AXISW->DATA & AXISW_DATA_BURSTI_MASK) >> AXISW_DATA_BURSTI) + 1u;
return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR); /*return error bit value*/
}
uint32_t MSS_AXISW_write_slave_ready(mss_axisw_mport_t master_port_num,
uint8_t slave_ready_en)
{
while(AXISW->CMD & AXISW_CMD_EN_MASK); /*make sure previous command completed*/
AXISW->DATA = slave_ready_en & 0x01; /*only valid value of bit0*/
AXISW->CMD = (AXISW_CMD_RW_MASK |
(master_port_num << AXISW_CMD_RWCHAN) |
MSS_AXISW_SLV_RDY |
AXISW_CMD_EN_MASK);
while(AXISW->CMD & AXISW_CMD_EN_MASK); /*Wait for command to complete*/
return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR); /*return error bit value*/
}
/*Performs read operation on the AXI SWITCH APB interface,
* Parameters:
* master_port_num = AXI Master Port number. See Enum mss_axisw_mport_t above.
*
*
* slave_ready_en: returns the data returned by AXI SWITCH read operation for slave ready command
* return value: As received form AXI_ERR_BIT in CMD register.
*
*/
uint32_t MSS_AXISW_read_slave_ready(mss_axisw_mport_t master_port_num,
uint8_t* slave_ready_en)
{
while(AXISW->CMD & AXISW_CMD_EN_MASK);
AXISW->CMD &= ~(AXISW_CMD_RW_MASK); /*Clear read/write bit*/
AXISW->CMD = ((master_port_num << AXISW_CMD_RWCHAN) |
(MSS_AXISW_SLV_RDY) |
AXISW_CMD_EN_MASK);
while(AXISW->CMD & AXISW_CMD_EN_MASK);
*slave_ready_en = AXISW->DATA & 0x01;
return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR); /*return error bit value*/
}
#ifdef __cplusplus
}
#endif

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/*=========================================================================*//**
*//*=========================================================================*/
#ifndef __MSS_AXISW_H_
#define __MSS_AXISW_H_ 1
#include <stddef.h>
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/***************************************************************************//**
*/
typedef enum {
MSS_AXISW_FIC0_RD_CHAN = 0x000,
MSS_AXISW_FIC0_WR_CHAN,
MSS_AXISW_FIC1_RD_CHAN,
MSS_AXISW_FIC1_WR_CHAN,
MSS_AXISW_FIC2_RD_CHAN,
MSS_AXISW_FIC2_WR_CHAN,
MSS_AXISW_ATHENA_RD_CHAN,
MSS_AXISW_ATHENA_WR_CHAN,
MSS_AXISW_GEM0_RD_CHAN,
MSS_AXISW_GEM0_WR_CHAN,
MSS_AXISW_GEM1_RD_CHAN,
MSS_AXISW_GEM1_WR_CHAN,
MSS_AXISW_MMC_RD_CHAN,
MSS_AXISW_MMC_WR_CHAN,
MSS_AXISW_USB_RD_CHAN,
MSS_AXISW_USB_WR_CHAN,
MSS_AXISW_SCB_RD_CHAN,
MSS_AXISW_SCB_WR_CHAN,
MSS_AXISW_CPLEX_D0_RD_CHAN,
MSS_AXISW_CPLEX_D0_WR_CHAN,
MSS_AXISW_CPLEX_D1_RD_CHAN,
MSS_AXISW_CPLEX_D1_WR_CHAN,
MSS_AXISW_CPLEX_F0_RD_CHAN,
MSS_AXISW_CPLEX_F0_WR_CHAN,
MSS_AXISW_CPLEX_F1_RD_CHAN,
MSS_AXISW_CPLEX_F1_WR_CHAN,
MSS_AXISW_CPLEX_NC_RD_CHAN,
MSS_AXISW_CPLEX_NC_WR_CHAN,
MSS_AXISW_TRACE_RD_CHAN,
MSS_AXISW_TRACE_WR_CHAN,
} mss_axisw_mport_t;
typedef enum {
MSS_AXISW_BURSTINESS_EN = 0x00,
MSS_AXISW_PEAKRT_XCTRT,
MSS_AXISW_QOS_VAL,
MSS_AXISW_SLV_RDY,
} mss_axisw_cmd_t;
typedef enum {
MSS_AXISW_MASTER_RD_CHAN = 0x00,
MSS_AXISW_MASTER_WR_CHAN = 0x01,
} mss_axisw_mchan_t;
/*
The Peak rate and transaction rates are encoded as follows.
1000_0000_0000 1/2
0100_0000_0000 1/4
0010_0000_0000 1/8
0001_0000_0000 1/16
0000_1000_0000 1/32
0000_0100_0000 1/64
0000_0010_0000 1/128
0000_0001_0000 1/256
0000_0000_1000 1/512
0000_0000_0100 1/1024
0000_0000_0010 1/2048
0000_0000_0001 1/4096
Programming the transaction rate as 0000_0000_0000 disables token generation and
traffic is not regulated based on the tokens.
Programming the peak rate as 0000_0000_0000 disables the peak rate control logic and
traffic is not regulated by the peak rate logic.
*/
typedef enum {
MSS_AXISW_TXNRATE_BY4096 = 0x001,
MSS_AXISW_TXNRATE_BY2098 = 0x002,
MSS_AXISW_TXNRATE_BY1024 = 0x004,
MSS_AXISW_TXNRATE_BY512 = 0x008,
MSS_AXISW_TXNRATE_BY256 = 0x010,
MSS_AXISW_TXNRATE_BY128 = 0x020,
MSS_AXISW_TXNRATE_BY64 = 0x040,
MSS_AXISW_TXNRATE_BY32 = 0x080,
MSS_AXISW_TXNRATE_BY16 = 0x100,
MSS_AXISW_TXNRATE_BY8 = 0x200,
MSS_AXISW_TXNRATE_BY4 = 0x400,
MSS_AXISW_TXNRATE_BY2 = 0x800,
MSS_AXISW_TXNRATE_DISABLE = 0x0,
} mss_axisw_rate_t;
#define AXISW_CMD_EN 31U
#define AXISW_CMD_EN_MASK (uint32_t)(0x01U << AXISW_CMD_EN)
#define AXISW_CMD_RW 30U
#define AXISW_CMD_RW_MASK (uint32_t)(0x01U << AXISW_CMD_RW)
#define AXISW_CMD_SWRST 29U
#define AXISW_CMD_SWRST_MASK (uint32_t)(0x01U << AXISW_CMD_SWRST)
#define AXISW_CMD_ERR 28U
#define AXISW_CMD_ERR_MASK (uint32_t)(0x01U << AXISW_CMD_ERR)
//#define AXISW_CMD_MPORT 8U
//#define AXISW_CMD_MPORT_MASK (0x0F << AXISW_CMD_MPORT)
#define AXISW_CMD_RWCHAN 7U
#define AXISW_CMD_RWCHAN_MASK (uint32_t)(0x1F << AXISW_CMD_RWCHAN)
#define AXISW_CMD_CMD 0U
#define AXISW_CMD_CMD_MASK (0x01U << AXISW_CMD_CMD)
#define AXISW_DATA_PEAKRT 20U
#define AXISW_DATA_PEAKRT_MASK (0xFFFU << AXISW_DATA_PEAKRT)
#define AXISW_DATA_XCTRT 4U
#define AXISW_DATA_XCTRT_MASK (0xFFFU << AXISW_DATA_XCTRT)
#define AXISW_DATA_BURSTI 16U
#define AXISW_DATA_BURSTI_MASK (0xFFU << AXISW_DATA_BURSTI)
#define AXISW_DATA_QOSVAL 0U
#define AXISW_DATA_QOSVAL_MASK (0xFU << AXISW_DATA_QOSVAL)
typedef struct
{
__IO uint32_t VID;
__IO uint32_t HWCFG;
__IO uint32_t CMD;
__IO uint32_t DATA;
} AXISW_TypeDef;
#define AXISW ((AXISW_TypeDef*)0x20004000UL)
uint32_t MSS_AXISW_get_hwcfg(void);
uint32_t MSS_AXISW_get_vid(void);
uint32_t MSS_AXISW_write_qos_val(mss_axisw_mport_t master_port_num,
uint32_t data);
uint32_t MSS_AXISW_read_qos_val(mss_axisw_mport_t master_port_num,
uint32_t* rd_data);
uint32_t MSS_AXISW_write_rate(mss_axisw_mport_t master_port_num,
mss_axisw_rate_t peak_rate,
mss_axisw_rate_t xct_rate);
uint32_t MSS_AXISW_read_rate(mss_axisw_mport_t master_port_num,
mss_axisw_rate_t* peak_rate,
mss_axisw_rate_t* xct_rate);
int32_t MSS_AXISW_write_burstiness(mss_axisw_mport_t master_port_num,
uint32_t burstiness_val,
uint32_t regulator_en);
uint32_t MSS_AXISW_read_burstiness(mss_axisw_mport_t master_port_num,
uint32_t* burstiness_val);
uint32_t MSS_AXISW_write_slave_ready(mss_axisw_mport_t master_port_num,
uint8_t slave_ready_en);
uint32_t MSS_AXISW_read_slave_ready(mss_axisw_mport_t master_port_num,
uint8_t* slave_ready_en);
#ifdef __cplusplus
}
#endif
#endif /* __MSS_AXISW_H_ */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/*******************************************************************************
*
* @file mss_clint.c
* @author Microchip-FPGA Embedded Systems Solutions
* @brief CLINT access data structures and functions.
*
*/
#include <stdint.h>
#include "mpfs_hal/mss_hal.h"
static uint64_t g_systick_increment[5] = {0ULL,0ULL,0ULL,0ULL,0ULL};
/**
* call once at startup
* @return
*/
void reset_mtime(void)
{
#if ROLLOVER_TEST
CLINT->MTIME = 0xFFFFFFFFFFFFF000ULL;
#else
CLINT->MTIME = 0ULL;
#endif
}
/**
* readmtime
* @return mtime
*/
uint64_t readmtime(void)
{
return (CLINT->MTIME);
}
/**
* Configure system tick
* @return SUCCESS or FAIL
*/
uint32_t SysTick_Config(void)
{
const uint32_t tick_rate[5] = {HART0_TICK_RATE_MS, HART1_TICK_RATE_MS ,HART2_TICK_RATE_MS ,HART3_TICK_RATE_MS ,HART4_TICK_RATE_MS};
volatile uint32_t ret_val = ERROR;
uint64_t mhart_id = read_csr(mhartid);
/*
* We are assuming the tick rate is in milli-seconds
*
* convert RTC frequency into milliseconds and multiple by the tick rate
*
*/
g_systick_increment[mhart_id] = ((LIBERO_SETTING_MSS_RTC_TOGGLE_CLK/1000U) * tick_rate[mhart_id]);
if (g_systick_increment[mhart_id] > 0ULL)
{
CLINT->MTIMECMP[mhart_id] = CLINT->MTIME + g_systick_increment[mhart_id];
set_csr(mie, MIP_MTIP); /* mie Register - Machine Timer Interrupt Enable */
__enable_irq();
ret_val = SUCCESS;
}
return (ret_val);
}
/**
* Disable system tick interrupt
*/
void disable_systick(void)
{
clear_csr(mie, MIP_MTIP); /* mie Register - Machine Timer Interrupt Enable */
return;
}
/*------------------------------------------------------------------------------
* RISC-V interrupt handler for machine timer interrupts.
*/
void handle_m_timer_interrupt(void)
{
volatile uint64_t hart_id = read_csr(mhartid);
volatile uint32_t error_loop;
clear_csr(mie, MIP_MTIP);
switch(hart_id)
{
case 0U:
SysTick_Handler_h0_IRQHandler();
break;
case 1U:
SysTick_Handler_h1_IRQHandler();
break;
case 2U:
SysTick_Handler_h2_IRQHandler();
break;
case 3U:
SysTick_Handler_h3_IRQHandler();
break;
case 4U:
SysTick_Handler_h4_IRQHandler();
break;
default:
while (hart_id != 0U)
{
error_loop++;
}
break;
}
CLINT->MTIMECMP[read_csr(mhartid)] = CLINT->MTIME + g_systick_increment[hart_id];
set_csr(mie, MIP_MTIP);
}
/**
*
*/
void handle_m_soft_interrupt(void)
{
volatile uint64_t hart_id = read_csr(mhartid);
volatile uint32_t error_loop;
switch(hart_id)
{
case 0U:
Software_h0_IRQHandler();
break;
case 1U:
Software_h1_IRQHandler();
break;
case 2U:
Software_h2_IRQHandler();
break;
case 3U:
Software_h3_IRQHandler();
break;
case 4U:
Software_h4_IRQHandler();
break;
default:
while (hart_id != 0U)
{
error_loop++;
}
break;
}
/*Clear software interrupt*/
clear_soft_interrupt();
}

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/*******************************************************************************
*
* @file mss_clint.h
* @author Microchip-FPGA Embedded Systems Solutions
* @brief CLINT access data structures and functions.
*
*/
#ifndef MSS_CLINT_H
#define MSS_CLINT_H
#include <stdint.h>
#include "encoding.h"
#include "atomic.h"
#ifdef __cplusplus
extern "C" {
#endif
#define RTC_PRESCALER 100U
#define SUCCESS 0U
#define ERROR 1U
/*==============================================================================
* CLINT: Core Local Interrupter
*/
typedef struct CLINT_Type_t
{
volatile uint32_t MSIP[5];
volatile uint32_t reserved1[(0x4000U - 0x14U)/4U];
volatile uint64_t MTIMECMP[5]; /* mtime compare value for each hart. When mtime equals this value, interrupt is generated for particular hart */
volatile uint32_t reserved2[((0xbff8U - 0x4028U)/4U)];
volatile uint64_t MTIME; /* contains the current mtime value */
} CLINT_Type;
#define CLINT ((CLINT_Type *)CLINT_BASE)
/*==============================================================================
* The function raise_soft_interrupt() raises a synchronous software interrupt by
* writing into the MSIP register.
*/
static inline void raise_soft_interrupt(unsigned long hart_id)
{
/*You need to make sure that the global interrupt is enabled*/
/*Note: set_csr(mie, MIP_MSIP) needs to be set on hart you are setting sw interrupt */
CLINT->MSIP[hart_id] = 0x01U; /*raise soft interrupt for hart(x) where x== hart ID*/
mb();
}
/*==============================================================================
* The function clear_soft_interrupt() clears a synchronous software interrupt by
* clearing the MSIP register.
*/
static inline void clear_soft_interrupt(void)
{
volatile uint32_t reg;
uint64_t hart_id = read_csr(mhartid);
CLINT->MSIP[hart_id] = 0x00U; /*clear soft interrupt for hart0*/
reg = CLINT->MSIP[hart_id]; /* we read back to make sure it has been written before moving on */
/* todo: verify line above guaranteed and best way to achieve result */
(void)reg; /* use reg to avoid compiler warning */
}
/*
* return mtime
*/
uint64_t readmtime(void);
/**
* call once at startup
* @return
*/
void reset_mtime(void);
/**
* Configure system tick
* @return SUCCESS or FAIL
*/
uint32_t SysTick_Config(void);
/**
* Disable system tick interrupt
*/
void disable_systick(void);
/*------------------------------------------------------------------------------
* RISC-V interrupt handler for machine timer interrupts.
*/
void handle_m_timer_interrupt(void);
/**
*
*/
void handle_m_soft_interrupt(void);
#ifdef __cplusplus
}
#endif
#endif /* MSS_CLINT_H */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/*******************************************************************************
*
* @file mss_h2f.c
* @author Microchip-FPGA Embedded Systems Solutions
* @brief H2F access data structures and functions.
*
*/
#include "mss_plic.h"
#include "mss_h2f.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifndef SIFIVE_HIFIVE_UNLEASHED
#define H2F_MAPPING_INVALID 255U
/*==============================================================================
* H2F_int_mapping, source to H2F output lines
* The internal interrupt are multiplexed to fabric I/O lines.
* That is, each line will contain several interrupts.
*/
const uint8_t H2F_int_mapping[BUS_ERROR_UNIT_HART_4]= { \
H2F_MAPPING_INVALID /*INVALID_IRQn = 0*/, \
H2F_MAPPING_INVALID /*L2_METADATA_CORR_IRQn = 1*/, \
H2F_MAPPING_INVALID /*L2_METADAT_UNCORR_IRQn = 2*/, \
H2F_MAPPING_INVALID /*L2_DATA_CORR_IRQn = 3*/, \
H2F_MAPPING_INVALID /*L2_DATA_UNCORR_IRQn = 4*/, \
H2F_MAPPING_INVALID /*DMA_CH0_DONE_IRQn = 5*/, \
H2F_MAPPING_INVALID /*DMA_CH0_ERR_IRQn = 6*/, \
H2F_MAPPING_INVALID /*DMA_CH1_DONE_IRQn = 7*/, \
H2F_MAPPING_INVALID /*DMA_CH1_ERR_IRQn = 8*/, \
H2F_MAPPING_INVALID /*DMA_CH2_DONE_IRQn = 9*/, \
H2F_MAPPING_INVALID /*DMA_CH2_ERR_IRQn = 10*/, \
H2F_MAPPING_INVALID /*DMA_CH3_DONE_IRQn = 11*/, \
H2F_MAPPING_INVALID /*DMA_CH3_ERR_IRQn = 12*/, \
0x00U /*GPIO0_BIT0_or_GPIO2_BIT0_PLIC_0 = 0 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO0_BIT1_or_GPIO2_BIT1_PLIC_1 = 1 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO0_BIT2_or_GPIO2_BIT2_PLIC_2 = 2 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO0_BIT3_or_GPIO2_BIT3_PLIC_3 = 3 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO0_BIT4_or_GPIO2_BIT4_PLIC_4 = 4 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO0_BIT5_or_GPIO2_BIT5_PLIC_5 = 5 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO0_BIT6_or_GPIO2_BIT6_PLIC_6 = 6 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO0_BIT7_or_GPIO2_BIT7_PLIC_7 = 7 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO0_BIT8_or_GPIO2_BIT8_PLIC_8 = 8 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO0_BIT9_or_GPIO2_BIT9_PLIC_9 = 9 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO0_BIT10_or_GPIO2_BIT10_PLIC_10 = 10 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO0_BIT11_or_GPIO2_BIT11_PLIC_11 = 11 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO0_BIT12_or_GPIO2_BIT12_PLIC_12 = 12 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO0_BIT14_or_GPIO2_BIT13_PLIC_13 = 13 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT0_or_GPIO2_BIT14_PLIC_14 = 14 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT1_or_GPIO2_BIT15_PLIC_15 = 15 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT2_or_GPIO2_BIT16_PLIC_16 = 16 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT3_or_GPIO2_BIT17_PLIC_17 = 17 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT4_or_GPIO2_BIT18_PLIC_18 = 18 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT5_or_GPIO2_BIT19_PLIC_19 = 19 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT6_or_GPIO2_BIT20_PLIC_20 = 20 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT7_or_GPIO2_BIT21_PLIC_21 = 21 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT8_or_GPIO2_BIT22_PLIC_22 = 22 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT9_or_GPIO2_BIT23_PLIC_23 = 23 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT10_or_GPIO2_BIT24_PLIC_24 = 24 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT11_or_GPIO2_BIT25_PLIC_25 = 25 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT12_or_GPIO2_BIT26_PLIC_26 = 26 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT13_or_GPIO2_BIT27_PLIC_27 = 27 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT14_or_GPIO2_BIT28_PLIC_28 = 28 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT15_or_GPIO2_BIT29_PLIC_29 = 29 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT16_or_GPIO2_BIT30_PLIC_30 = 30 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT17_or_GPIO2_BIT31_PLIC_31 = 31 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT18_PLIC_32 = 32 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT19_PLIC_33 = 33 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT20_PLIC_34 = 34 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT21_PLIC_35 = 35 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT22_PLIC_36 = 36 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_BIT23_PLIC_37 = 37 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO0_NON_DIRECT_PLI =38 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO1_NON_DIRECT_PLIC =39 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x00U /*GPIO2_NON_DIRECT_PLIC =40 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x01U /*SPI0_PLIC =41 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x01U /*SPI1_PLIC =42 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x01U /*CAN0_PLIC =43 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x01U /*CAN1_PLIC =44 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x02U /*I2C0_MAIN_PLIC =45 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x02U /*I2C0_ALERT_PLIC =46 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x02U /*I2C0_SUS_PLIC =47 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x02U /*I2C1_MAIN_PLIC =48 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x02U /*I2C1_ALERT_PLIC =49 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x02U /*I2C1_SUS_PLIC =50 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x03U /*MAC0_INT_PLIC =51 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x03U /*MAC0_QUEUE1_PLIC =52 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x03U /*MAC0_QUEUE2_PLIC =53 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x03U /*MAC0_QUEUE3_PLIC =54 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x03U /*MAC0_eMAC_PLIC =55 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x03U /*MAC0_MMSL_PLIC =56 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x04U /*MAC1_int_PLIC =57 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x04U /*MAC1_QUEUE1_PLIC =58 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x04U /*MAC1_QUEUE2_PLIC =59 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x04U /*MAC1_QUEUE3_PLIC =60 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x04U /*MAC1_EMAC_PLIC =61 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x04U /*MAC1_MMSL_PLIC =62 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x09U /*DDRC_TRAIN_PLIC =63 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x07U /*SCB_INTERRUPT_PLIC =64 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x06U /*ECC_ERROR_PLIC =65 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x06U /*ECC_CORRECT_PLIC =66 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x0BU /*RTC_WAKEUP_PLIC =67 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x0BU /*RTC_MATCH_PLIC =68 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x0CU /*TIMER1_PLIC =69 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x0CU /*TIMER2_PLIC =70 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x0DU /*ENVM_PLIC =71 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x0DU /*QSPI_PLIC =72 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x0EU /*USB_DMA_PLIC =73 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x0EU /*USB_MC_PLIC =74 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x0FU /*MMC_main_PLIC =75 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x0FU /*MMC_wakeup_PLIC =76 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x01U /*MMUART0_PLIC_77 =77 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x01U /*MMUART1_PLIC =78 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x01U /*MMUART2_PLIC =79 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x01U /*MMUART3_PLIC =80 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x01U /*MMUART4_PLIC =81 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x0AU /*G5C_DEVRST_PLIC =82 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x08U /*g5c_MESSAGE_PLIC =83 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x0BU /*USOC_VC_INTERRUPT_PLIC =84 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x0BU /*USOC_SMB_INTERRUPT_PLIC =85 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x06U /*E51_0_MAINTENACE_PLIC =86 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x05U /*WDOG0_MRVP_PLIC =87 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x05U /*WDOG1_MRVP_PLIC =88 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x05U /*WDOG2_MRVP_PLIC =89 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x05U /*WDOG3_MRVP_PLIC =90 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x05U /*WDOG4_MRVP_PLIC =91 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x05U /*WDOG0_TOUT_PLIC =92 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x05U /*WDOG1_TOUT_PLIC =93 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x05U /*WDOG2_TOUT_PLIC =94 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x05U /*WDOG3_TOUT_PLIC =95 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x05U /*WDOG4_TOUT_PLIC =96 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x0DU /*G5C_MSS_SPI_PLIC =97 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*VOLT_TEMP_ALARM_PLIC =98 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*ATHENA_COMPLETE_PLIC =99 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*ATHENA_ALARM_PLIC =100 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*ATHENA_BUS_ERROR_PLIC =101 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x0BU /*USOC_AXIC_US_PLIC =102 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
0x0BU /*USOC_AXIC_DS_PLIC =103 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_0_PLIC = 105 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_1_PLIC = 106 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_2_PLIC = 107 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_3_PLIC = 108 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_4_PLIC = 109 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_5_PLIC = 110 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_6_PLIC = 111 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_7_PLIC = 112 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_8_PLIC = 113 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_9_PLIC = 114 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_10_PLIC = 115 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_11_PLIC = 116 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_12_PLIC = 117 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_13_PLIC = 118 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_14_PLIC = 119 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_15_PLIC = 120 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_16_PLIC = 121 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_17_PLIC = 122 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_18_PLIC = 123 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_19_PLIC = 124 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_20_PLIC = 125 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_21_PLIC = 126 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_22_PLIC = 127 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_23_PLIC = 128 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_24_PLIC = 129 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_25_PLIC = 130 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_26_PLIC = 131 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_27_PLIC = 132 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_28_PLIC = 133 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_29_PLIC = 134 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_30_PLIC = 135 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_31_PLIC = 136 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_32_PLIC = 137 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_33_PLIC = 138 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_34_PLIC = 139 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_35_PLIC = 140 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_36_PLIC = 141 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_37_PLIC = 142 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_38_PLIC = 143 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_39_PLIC = 144 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_40_PLIC = 145 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_41_PLIC = 146 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_42_PLIC = 147 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_43_PLIC = 148 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_44_PLIC = 149 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_45_PLIC = 150 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_46_PLIC = 151 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_47_PLIC = 152 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_48_PLIC = 153 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_49_PLIC = 154 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_50_PLIC = 155 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_51_PLIC = 156 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_52_PLIC = 157 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_53_PLIC = 158 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_54_PLIC = 159 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_55_PLIC = 160 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_56_PLIC = 161 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_57_PLIC = 162 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_58_PLIC = 163 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_59_PLIC = 164 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_60_PLIC = 165 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_61_PLIC = 166 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_62_PLIC = 167 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*FABRIC_F2H_63_PLIC = 168 + OFFSET_TO_MSS_GLOBAL_INTS*/, \
H2F_MAPPING_INVALID /*BUS_ERROR_UNIT_HART_0 = 182*/, \
H2F_MAPPING_INVALID /*BUS_ERROR_UNIT_HART_1 = 183*/, \
H2F_MAPPING_INVALID /*BUS_ERROR_UNIT_HART_2 = 184*/, \
H2F_MAPPING_INVALID /*BUS_ERROR_UNIT_HART_3 = 185*/, \
H2F_MAPPING_INVALID /*BUS_ERROR_UNIT_HART_4 = 186 */
};
/**
* get source to fabric signal mapping
* @param source_int
* @return
*/
static uint32_t get_corresponding_h2f_output(uint32_t source_int)
{
uint32_t h2f_line = H2F_int_mapping[source_int];
if(h2f_line < H2F_MAPPING_INVALID) /* if no error */
{
return(0x01U << h2f_line);
}
return(h2f_line);
}
/**
* set H2F controller to reset to defaults- disabled
*/
void reset_h2f(void)
{
uint8_t index = 0U;
H2F_CONTROLLER->ENABLE = 0U;
while(index < 4U)
{
H2F_CONTROLLER->PLENABLE[index] = 0U;
index++;
}
}
/**
* enables output which will mirror PLIC input. PLIC mapping given above for reference
* @param source_int
*/
void enable_h2f_int_output(uint32_t source_int)
{
uint32_t output_signal = get_corresponding_h2f_output(source_int);
if(output_signal != H2F_MAPPING_INVALID)
{
source_int -= OFFSET_TO_MSS_GLOBAL_INTS;
/* enable the input */
H2F_CONTROLLER->PLENABLE[source_int/32U] |= (0x01U << (source_int % 32U));
/* enable the output */
H2F_CONTROLLER->ENABLE |= ((output_signal<<16U) | 0x01U);
}
}
/**
* enables output which will mirror PLIC input. PLIC mapping given above for reference
* @param source_int
*/
void disable_h2f_int_output(uint32_t source_int)
{
uint32_t output_signal = get_corresponding_h2f_output(source_int);
if(output_signal != H2F_MAPPING_INVALID)
{
/* enable the input */
H2F_CONTROLLER->PLENABLE[source_int/32U] &= ~(source_int % 32U);
/* enable the output */
H2F_CONTROLLER->ENABLE &= ~(((output_signal<<16U)));
}
}
#ifdef __cplusplus
}
#endif
#endif

88
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/platform/mpfs_hal/common/mss_h2f.h Normal file
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@ -0,0 +1,88 @@
/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/*******************************************************************************
*
* @file mss_h2f.h
* @author Microchip-FPGA Embedded Systems Solutions
* @brief H2F access data structures and functions.
*
* Definitions and functions associated with host to fabric interrupt controller.
*
*/
#ifndef MSS_H2F_H
#define MSS_H2F_H
#include "mpfs_hal_config/mss_sw_config.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
H2F line Group Ored (no of interrupts ored to one output line)
0 GPIO 41
1 MMUART,SPI,CAN 9
2 I2C 6
3 MAC0 6
4 MAC1 6
5 WATCHDOGS 10
6 Maintenance 3
7 SCB 1
8 G5C-Message 1
9 DDRC 1
10 G5C-DEVRST 2
11 RTC/USOC 4
12 TIMER 2
13 ENVM, QSPI 2
14 USB 2
15 MMC/SDIO 2
*/
/*==============================================================================
* Host to Fabric interrupt controller
*
* For an interrupt to activate the PENABLE and appropriate HENABLE and PENABLE bits must be set.
*
* Note. Since Interrupts 127:94 are not used in the system the enable registers are non-write-able and always read as zeros.
*
*/
typedef struct
{
volatile uint32_t ENABLE; /* bit o: Enables all the H2FINT outputs, bit 31:16 Enables individual H2F outputs */
volatile uint32_t H2FSTATUS; /* 15:0 Read back of the 16-bit H2F Interrupts before the H2F and global enable */
uint32_t filler[2U]; /* fill the gap in the memory map */
volatile uint32_t PLSTATUS[4U]; /* Indicates that the PLINT interrupt is active before the PLINT enable
i.e. direct read of the PLINT inputs [31:0] from PLSTATUS[0]
direct read of the PLINT inputs [63:32] from PLSTATUS[1]
etc */
volatile uint32_t PLENABLE[4U]; /* Enables PLINT interrupts PLENABLE[0] 31:0, PLENABLE[1] 63:32, 95:64, 127:96 */
} H2F_CONTROLLER_Type;
#ifndef H2F_BASE_ADDRESS
#if (LIBERO_SETTING_APBBUS_CR & (1U<<23U))
#define H2F_BASE_ADDRESS 0x28126000
#else
#define H2F_BASE_ADDRESS 0x20126000
#endif
#endif
#define H2F_CONTROLLER ((H2F_CONTROLLER_Type *)H2F_BASE_ADDRESS)
void reset_h2f(void);
void enable_h2f_int_output(uint32_t source_int);
void disable_h2f_int_output(uint32_t source_int);
#ifdef __cplusplus
}
#endif
#endif /* MSS_H2F_H */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/*******************************************************************************
*
* @file mss_hart_ints.h
* @author Microchip-FPGA Embedded Systems Solutions
* @brief MPFS local interrupt definitions
*
* Definitions and functions associated with local interrupts for each hart.
*
*/
#ifndef MSS_HART_INTS_H
#define MSS_HART_INTS_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct BEU_Type_
{
volatile uint64_t CAUSE;
volatile uint64_t VALUE;
volatile uint64_t ENABLE;
volatile uint64_t PLIC_INT;
volatile uint64_t ACCRUED;
volatile uint64_t LOCAL_INT;
volatile uint64_t reserved2[((0x1000U/8U) - 0x6U)];
} BEU_Type;
typedef struct BEU_Types_
{
volatile BEU_Type regs[5];
} BEU_Types;
#define MSS_BUS_ERROR_UNIT_H0 0x01700000UL
#define MSS_BUS_ERROR_UNIT_H1 0x01701000UL
#define MSS_BUS_ERROR_UNIT_H2 0x01702000UL
#define MSS_BUS_ERROR_UNIT_H3 0x01703000UL
#define MSS_BUS_ERROR_UNIT_H4 0x01704000UL
#define BEU ((BEU_Types *)MSS_BUS_ERROR_UNIT_H0)
/*
* Interrupt numbers U0
*/
#define MAINTENANCE_E51_INT 0
#define USOC_SMB_INTERRUPT_E51_INT 1
#define USOC_VC_INTERRUPT_E51_INT 2
#define G5C_MESSAGE_E51_INT 3
#define G5C_DEVRST_E51_INT 4
#define WDOG4_TOUT_E51_INT 5
#define WDOG3_TOUT_E51_INT 6
#define WDOG2_TOUT_E51_INT 7
#define WDOG1_TOUT_E51_INT 8
#define WDOG0_TOUT_E51_INT 9
#define WDOG0_MVRP_E51_INT 10
#define MMUART0_E51_INT 11
#define ENVM_E51_INT 12
#define ECC_CORRECT_E51_INT 13
#define ECC_ERROR_E51_INT 14
#define scb_INTERRUPT_E51_INT 15
#define FABRIC_F2H_32_E51_INT 16
#define FABRIC_F2H_33_E51_INT 17
#define FABRIC_F2H_34_E51_INT 18
#define FABRIC_F2H_35_E51_INT 19
#define FABRIC_F2H_36_E51_INT 20
#define FABRIC_F2H_37_E51_INT 21
#define FABRIC_F2H_38_E51_INT 22
#define FABRIC_F2H_39_E51_INT 23
#define FABRIC_F2H_40_E51_INT 24
#define FABRIC_F2H_41_E51_INT 25
#define FABRIC_F2H_42_E51_INT 26
#define FABRIC_F2H_43_E51_INT 27
#define FABRIC_F2H_44_E51_INT 28
#define FABRIC_F2H_45_E51_INT 29
#define FABRIC_F2H_46_E51_INT 30
#define FABRIC_F2H_47_E51_INT 31
#define FABRIC_F2H_48_E51_INT 32
#define FABRIC_F2H_49_E51_INT 33
#define FABRIC_F2H_50_E51_INT 34
#define FABRIC_F2H_51_E51_INT 35
#define FABRIC_F2H_52_E51_INT 36
#define FABRIC_F2H_53_E51_INT 37
#define FABRIC_F2H_54_E51_INT 38
#define FABRIC_F2H_55_E51_INT 39
#define FABRIC_F2H_56_E51_INT 40
#define FABRIC_F2H_57_E51_INT 41
#define FABRIC_F2H_58_E51_INT 42
#define FABRIC_F2H_59_E51_INT 43
#define FABRIC_F2H_60_E51_INT 44
#define FABRIC_F2H_61_E51_INT 45
#define FABRIC_F2H_62_E51_INT 46
#define FABRIC_F2H_63_E51_INT 47
#define LOCAL_INT_MAX 47U /* Highest numbered */
#define LOCAL_INT_UNUSED 127U /* Signifies unused interrupt */
/*
* Interrupts associated with
* MAINTENANCE_E51_INT
*
* A group of interrupt events are grouped into a single maintenance interrupt to the E51 CPU,
* on receiving this interrupt the E51 should read the maintenance system register to find out
* the interrupt source. The maintenance interrupts are defined below
*/
#define MAINTENANCE_E51_pll_INT 0
#define MAINTENANCE_E51_mpu_INT 1
#define MAINTENANCE_E51_lp_state_enter_INT 2
#define MAINTENANCE_E51_lp_state_exit_INT 3
#define MAINTENANCE_E51_ff_start_INT 4
#define MAINTENANCE_E51_ff_end_INT 5
#define MAINTENANCE_E51_fpga_on_INT 6
#define MAINTENANCE_E51_fpga_off_INT 7
#define MAINTENANCE_E51_scb_error_INT 8
#define MAINTENANCE_E51_scb_fault_INT 9
#define MAINTENANCE_E51_mesh_error_INT 10
#define MAINTENANCE_E51_io_bank_b2_on_INT 12
#define MAINTENANCE_E51_io_bank_b4_on_INT 13
#define MAINTENANCE_E51_io_bank_b5_on_INT 14
#define MAINTENANCE_E51_io_bank_b6_on_INT 15
#define MAINTENANCE_E51_io_bank_b2_off_INT 16
#define MAINTENANCE_E51_io_bank_b4_off_INT 17
#define MAINTENANCE_E51_io_bank_b5_off_INT 18
#define MAINTENANCE_E51_io_bank_b6_off_INT 19
/*
* E51-0 is Maintenance Interrupt CPU needs to read status register to determine exact cause:
* These defines added here for clarity need to replay with status register defines
* for determining interrupt cause
*/
#ifndef FOR_CLARITY
# define FOR_CLARITY 0
#endif
#if FOR_CLARITY
# define mpu_fail_plic 0
# define lp_state_enter_plic 1
# define lp_state_exit_plic 2
# define ff_start_plic 3
# define ff_end_plic 4
# define fpga_on_plic 5
# define fpga_off_plic 6
# define scb_error_plic 7
# define scb_fault_plic 8
# define mesh_fail_plic 9
#endif
/*
* Interrupt numbers U54's
*/
/* U0 (first U54) and U1 connected to mac0 */
#define MAC0_INT_U54_INT 8 /* determine source mac using hart ID */
#define MAC0_QUEUE1_U54_INT 7
#define MAC0_QUEUE2_U54_INT 6
#define MAC0_QUEUE3_U54_INT 5
#define MAC0_EMAC_U54_INT 4
#define MAC0_MMSL_U54_INT 3
/* U2 and U3 connected to mac1 */
#define MAC1_INT_U54_INT 8 /* determine source mac using hart ID */
#define MAC1_QUEUE1_U54_INT 7
#define MAC1_QUEUE2_U54_INT 6
#define MAC1_QUEUE3_U54_INT 5
#define MAC1_EMAC_U54_INT 4
#define MAC1_MMSL_U54_INT 3
/* MMUART1 connected to U54 0 */
/* MMUART2 connected to U54 1 */
/* MMUART3 connected to U54 2 */
/* MMUART4 connected to U54 3 */
#define MMUARTx_U54_INT 11 /* MMUART1 connected to U54 0 */
#define WDOGx_MVRP_U54_INT 10 /* determine source mac using hart ID */
#define WDOGx_TOUT_U54_INT 9 /* determine source mac using hart ID */
#define H2_FABRIC_F2H_0_U54_INT 16
#define H2_FABRIC_F2H_1_U54_INT 17
#define H2_FABRIC_F2H_2_U54_INT 18
#define H2_FABRIC_F2H_3_U54_INT 19
#define H2_FABRIC_F2H_4_U54_INT 20
#define H2_FABRIC_F2H_5_U54_INT 21
#define H2_FABRIC_F2H_6_U54_INT 22
#define H2_FABRIC_F2H_7_U54_INT 23
#define H2_FABRIC_F2H_8_U54_INT 24
#define H2_FABRIC_F2H_9_U54_INT 25
#define H2_FABRIC_F2H_10_U54_INT 26
#define H2_FABRIC_F2H_11_U54_INT 27
#define H2_FABRIC_F2H_12_U54_INT 28
#define H2_FABRIC_F2H_13_U54_INT 29
#define H2_FABRIC_F2H_14_U54_INT 30
#define H2_FABRIC_F2H_15_U54_INT 31
#define H2_FABRIC_F2H_16_U54_INT 32
#define H2_FABRIC_F2H_17_U54_INT 33
#define H2_FABRIC_F2H_18_U54_INT 34
#define H2_FABRIC_F2H_19_U54_INT 35
#define H2_FABRIC_F2H_20_U54_INT 36
#define H2_FABRIC_F2H_21_U54_INT 37
#define H2_FABRIC_F2H_22_U54_INT 38
#define H2_FABRIC_F2H_23_U54_INT 39
#define H2_FABRIC_F2H_24_U54_INT 40
#define H2_FABRIC_F2H_25_U54_INT 41
#define H2_FABRIC_F2H_26_U54_INT 42
#define H2_FABRIC_F2H_27_U54_INT 43
#define H2_FABRIC_F2H_28_U54_INT 44
#define H2_FABRIC_F2H_29_U54_INT 45
#define H2_FABRIC_F2H_30_U54_INT 46
#define H2_FABRIC_F2H_31_U54_INT 47
void handle_m_ext_interrupt(void);
void Software_h0_IRQHandler(void);
void Software_h1_IRQHandler(void);
void Software_h2_IRQHandler(void);
void Software_h3_IRQHandler(void);
void Software_h4_IRQHandler(void);
void SysTick_Handler_h0_IRQHandler(void);
void SysTick_Handler_h1_IRQHandler(void);
void SysTick_Handler_h2_IRQHandler(void);
void SysTick_Handler_h3_IRQHandler(void);
void SysTick_Handler_h4_IRQHandler(void);
/*
*
* Local interrupt defines
*
*/
void maintenance_e51_local_IRQHandler_0(void);
void usoc_smb_interrupt_e51_local_IRQHandler_1(void);
void usoc_vc_interrupt_e51_local_IRQHandler_2(void);
void g5c_message_e51_local_IRQHandler_3(void);
void g5c_devrst_e51_local_IRQHandler_4(void);
void wdog4_tout_e51_local_IRQHandler_5(void);
void wdog3_tout_e51_local_IRQHandler_6(void);
void wdog2_tout_e51_local_IRQHandler_7(void);
void wdog1_tout_e51_local_IRQHandler_8(void);
void wdog0_tout_e51_local_IRQHandler_9(void);
void wdog0_mvrp_e51_local_IRQHandler_10(void);
void mmuart0_e51_local_IRQHandler_11(void);
void envm_e51_local_IRQHandler_12(void);
void ecc_correct_e51_local_IRQHandler_13(void);
void ecc_error_e51_local_IRQHandler_14(void);
void scb_interrupt_e51_local_IRQHandler_15(void);
void fabric_f2h_32_e51_local_IRQHandler_16(void);
void fabric_f2h_33_e51_local_IRQHandler_17(void);
void fabric_f2h_34_e51_local_IRQHandler_18(void);
void fabric_f2h_35_e51_local_IRQHandler_19(void);
void fabric_f2h_36_e51_local_IRQHandler_20(void);
void fabric_f2h_37_e51_local_IRQHandler_21(void);
void fabric_f2h_38_e51_local_IRQHandler_22(void);
void fabric_f2h_39_e51_local_IRQHandler_23(void);
void fabric_f2h_40_e51_local_IRQHandler_24(void);
void fabric_f2h_41_e51_local_IRQHandler_25(void);
void fabric_f2h_42_e51_local_IRQHandler_26(void);
void fabric_f2h_43_e51_local_IRQHandler_27(void);
void fabric_f2h_44_e51_local_IRQHandler_28(void);
void fabric_f2h_45_e51_local_IRQHandler_29(void);
void fabric_f2h_46_e51_local_IRQHandler_30(void);
void fabric_f2h_47_e51_local_IRQHandler_31(void);
void fabric_f2h_48_e51_local_IRQHandler_32(void);
void fabric_f2h_49_e51_local_IRQHandler_33(void);
void fabric_f2h_50_e51_local_IRQHandler_34(void);
void fabric_f2h_51_e51_local_IRQHandler_35(void);
void fabric_f2h_52_e51_local_IRQHandler_36(void);
void fabric_f2h_53_e51_local_IRQHandler_37(void);
void fabric_f2h_54_e51_local_IRQHandler_38(void);
void fabric_f2h_55_e51_local_IRQHandler_39(void);
void fabric_f2h_56_e51_local_IRQHandler_40(void);
void fabric_f2h_57_e51_local_IRQHandler_41(void);
void fabric_f2h_58_e51_local_IRQHandler_42(void);
void fabric_f2h_59_e51_local_IRQHandler_43(void);
void fabric_f2h_60_e51_local_IRQHandler_44(void);
void fabric_f2h_61_e51_local_IRQHandler_45(void);
void fabric_f2h_62_e51_local_IRQHandler_46(void);
void fabric_f2h_63_e51_local_IRQHandler_47(void);
/*
* U54
*/
void spare_u54_local_IRQHandler_0(void);
void spare_u54_local_IRQHandler_1(void);
void spare_u54_local_IRQHandler_2(void);
void mac_mmsl_u54_1_local_IRQHandler_3(void);
void mac_emac_u54_1_local_IRQHandler_4(void);
void mac_queue3_u54_1_local_IRQHandler_5(void);
void mac_queue2_u54_1_local_IRQHandler_6(void);
void mac_queue1_u54_1_local_IRQHandler_7(void);
void mac_int_u54_1_local_IRQHandler_8(void);
void mac_mmsl_u54_2_local_IRQHandler_3(void);
void mac_emac_u54_2_local_IRQHandler_4(void);
void mac_queue3_u54_2_local_IRQHandler_5(void);
void mac_queue2_u54_2_local_IRQHandler_6(void);
void mac_queue1_u54_2_local_IRQHandler_7(void);
void mac_int_u54_2_local_IRQHandler_8(void);
void mac_mmsl_u54_3_local_IRQHandler_3(void);
void mac_emac_u54_3_local_IRQHandler_4(void);
void mac_queue3_u54_3_local_IRQHandler_5(void);
void mac_queue2_u54_3_local_IRQHandler_6(void);
void mac_queue1_u54_3_local_IRQHandler_7(void);
void mac_int_u54_3_local_IRQHandler_8(void);
void mac_mmsl_u54_4_local_IRQHandler_3(void);
void mac_emac_u54_4_local_IRQHandler_4(void);
void mac_queue3_u54_4_local_IRQHandler_5(void);
void mac_queue2_u54_4_local_IRQHandler_6(void);
void mac_queue1_u54_4_local_IRQHandler_7(void);
void mac_int_u54_4_local_IRQHandler_8(void);
void wdog_tout_u54_h1_local_IRQHandler_9(void);
void wdog_tout_u54_h2_local_IRQHandler_9(void);
void wdog_tout_u54_h3_local_IRQHandler_9(void);
void wdog_tout_u54_h4_local_IRQHandler_9(void);
void mvrp_u54_local_IRQHandler_10(void);
void mmuart_u54_h1_local_IRQHandler_11(void);
void mmuart_u54_h2_local_IRQHandler_11(void);
void mmuart_u54_h3_local_IRQHandler_11(void);
void mmuart_u54_h4_local_IRQHandler_11(void);
void spare_u54_local_IRQHandler_12(void);
void spare_u54_local_IRQHandler_13(void);
void spare_u54_local_IRQHandler_14(void);
void spare_u54_local_IRQHandler_15(void);
void fabric_f2h_0_u54_local_IRQHandler_16(void);
void fabric_f2h_1_u54_local_IRQHandler_17(void);
void fabric_f2h_2_u54_local_IRQHandler_18(void);
void fabric_f2h_3_u54_local_IRQHandler_19(void);
void fabric_f2h_4_u54_local_IRQHandler_20(void);
void fabric_f2h_5_u54_local_IRQHandler_21(void);
void fabric_f2h_6_u54_local_IRQHandler_22(void);
void fabric_f2h_7_u54_local_IRQHandler_23(void);
void fabric_f2h_8_u54_local_IRQHandler_24(void);
void fabric_f2h_9_u54_local_IRQHandler_25(void);
void fabric_f2h_10_u54_local_IRQHandler_26(void);
void fabric_f2h_11_u54_local_IRQHandler_27(void);
void fabric_f2h_12_u54_local_IRQHandler_28(void);
void fabric_f2h_13_u54_local_IRQHandler_29(void);
void fabric_f2h_14_u54_local_IRQHandler_30(void);
void fabric_f2h_15_u54_local_IRQHandler_31(void);
void fabric_f2h_16_u54_local_IRQHandler_32(void);
void fabric_f2h_17_u54_local_IRQHandler_33(void);
void fabric_f2h_18_u54_local_IRQHandler_34(void);
void fabric_f2h_19_u54_local_IRQHandler_35(void);
void fabric_f2h_20_u54_local_IRQHandler_36(void);
void fabric_f2h_21_u54_local_IRQHandler_37(void);
void fabric_f2h_22_u54_local_IRQHandler_38(void);
void fabric_f2h_23_u54_local_IRQHandler_39(void);
void fabric_f2h_24_u54_local_IRQHandler_40(void);
void fabric_f2h_25_u54_local_IRQHandler_41(void);
void fabric_f2h_26_u54_local_IRQHandler_42(void);
void fabric_f2h_27_u54_local_IRQHandler_43(void);
void fabric_f2h_28_u54_local_IRQHandler_44(void);
void fabric_f2h_29_u54_local_IRQHandler_45(void);
void fabric_f2h_30_u54_local_IRQHandler_46(void);
void fabric_f2h_31_u54_local_IRQHandler_47(void);
#ifdef __cplusplus
}
#endif
#endif /* MSS_HART_INTS_H */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/*******************************************************************************
* @file mss_l2_cache.c
* @author Microchip-FPGA Embedded Systems Solutions
* @brief The code in this file is executed before any code/data sections are
* copied. This code must not rely sdata/data section content. Hence, global
* variables should not be used unless they are constants.
*
*/
/*==============================================================================
*
*/
#include <stdio.h>
#include <string.h>
#include "mpfs_hal/mss_hal.h"
#include "mss_l2_cache.h"
/*==============================================================================
* Local defines
*/
#if (LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS != 0)
static const uint64_t g_init_marker = INIT_MARKER;
#endif
/*==============================================================================
* Local functions.
*/
static void check_config_l2_scratchpad(void);
/*==============================================================================
* This code should only be executed from E51 to be functional.
* Configure the L2 cache memory:
* - Set the number of cache ways used as cache based on the MSS Configurator
* settings.
* - Configure some of the enabled ways as scratchpad based on linker
* configuration and space allocated by configurator.
*/
__attribute__((weak)) void config_l2_cache(void)
{
ASSERT(LIBERO_SETTING_WAY_ENABLE < 16U);
/*
* Set the number of ways that will be shared between cache and scratchpad.
*/
CACHE_CTRL->WAY_ENABLE = LIBERO_SETTING_WAY_ENABLE;
/*
* shutdown L2 as directed
*/
SYSREG->L2_SHUTDOWN_CR = LIBERO_SETTING_L2_SHUTDOWN_CR;
/* The scratchpad has already been set-up, first check enough space before copying */
check_config_l2_scratchpad();
/* If you are not using scratchpad, no need to include the following code */
ASSERT(LIBERO_SETTING_WAY_ENABLE >= LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS);
/*
* Compute the mask used to specify ways that will be used by the
* scratchpad.
*/
uint32_t scratchpad_ways_mask = 0U;
#if (LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS != 0)
uint32_t inc;
uint32_t seed_ways_mask = 0x1U << LIBERO_SETTING_WAY_ENABLE;
for(inc = 0; inc < LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS; ++inc)
{
scratchpad_ways_mask |= (seed_ways_mask >> inc) ;
}
#else
(void)scratchpad_ways_mask;
#endif
/*
* Make sure ways are masked if being used as scratchpad
*/
ASSERT((LIBERO_SETTING_WAY_MASK_DMA & scratchpad_ways_mask) == 0UL);
ASSERT((LIBERO_SETTING_WAY_MASK_AXI4_PORT_0 & scratchpad_ways_mask) == 0UL);
ASSERT((LIBERO_SETTING_WAY_MASK_AXI4_PORT_1 & scratchpad_ways_mask) == 0UL);
ASSERT((LIBERO_SETTING_WAY_MASK_AXI4_PORT_2 & scratchpad_ways_mask) == 0UL);
ASSERT((LIBERO_SETTING_WAY_MASK_AXI4_PORT_3 & scratchpad_ways_mask) == 0UL);
ASSERT((LIBERO_SETTING_WAY_MASK_E51_DCACHE & scratchpad_ways_mask) == 0UL);
ASSERT((LIBERO_SETTING_WAY_MASK_E51_ICACHE & scratchpad_ways_mask) == 0UL);
ASSERT((LIBERO_SETTING_WAY_MASK_U54_1_DCACHE & scratchpad_ways_mask) == 0UL);
ASSERT((LIBERO_SETTING_WAY_MASK_U54_2_DCACHE & scratchpad_ways_mask) == 0UL);
ASSERT((LIBERO_SETTING_WAY_MASK_U54_3_DCACHE & scratchpad_ways_mask) == 0UL);
ASSERT((LIBERO_SETTING_WAY_MASK_U54_4_DCACHE & scratchpad_ways_mask) == 0UL);
ASSERT((LIBERO_SETTING_WAY_MASK_U54_1_ICACHE & scratchpad_ways_mask) == 0UL);
ASSERT((LIBERO_SETTING_WAY_MASK_U54_2_ICACHE & scratchpad_ways_mask) == 0UL);
ASSERT((LIBERO_SETTING_WAY_MASK_U54_3_ICACHE & scratchpad_ways_mask) == 0UL);
ASSERT((LIBERO_SETTING_WAY_MASK_U54_4_ICACHE & scratchpad_ways_mask) == 0UL);
/*
* Setup all masters, apart from one we are using to setup scratch
*/
CACHE_CTRL->WAY_MASK_DMA = LIBERO_SETTING_WAY_MASK_DMA;
CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_0 = LIBERO_SETTING_WAY_MASK_AXI4_PORT_0;
CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_1 = LIBERO_SETTING_WAY_MASK_AXI4_PORT_1;
CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_2 = LIBERO_SETTING_WAY_MASK_AXI4_PORT_2;
CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_3 = LIBERO_SETTING_WAY_MASK_AXI4_PORT_3;
CACHE_CTRL->WAY_MASK_E51_ICACHE = LIBERO_SETTING_WAY_MASK_E51_ICACHE;
CACHE_CTRL->WAY_MASK_U54_1_DCACHE = LIBERO_SETTING_WAY_MASK_U54_1_DCACHE;
CACHE_CTRL->WAY_MASK_U54_1_ICACHE = LIBERO_SETTING_WAY_MASK_U54_1_ICACHE;
CACHE_CTRL->WAY_MASK_U54_2_DCACHE = LIBERO_SETTING_WAY_MASK_U54_2_DCACHE;
CACHE_CTRL->WAY_MASK_U54_2_ICACHE = LIBERO_SETTING_WAY_MASK_U54_2_ICACHE;
CACHE_CTRL->WAY_MASK_U54_3_DCACHE = LIBERO_SETTING_WAY_MASK_U54_3_DCACHE;
CACHE_CTRL->WAY_MASK_U54_3_ICACHE = LIBERO_SETTING_WAY_MASK_U54_3_ICACHE;
CACHE_CTRL->WAY_MASK_U54_4_DCACHE = LIBERO_SETTING_WAY_MASK_U54_4_DCACHE;
CACHE_CTRL->WAY_MASK_U54_4_ICACHE = LIBERO_SETTING_WAY_MASK_U54_4_ICACHE;
#if (LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS != 0)
/*
* Assign ways to Zero Device
*/
uint64_t * p_scratchpad = (uint64_t *)ZERO_DEVICE_BOTTOM;
uint32_t ways_inc;
uint64_t current_way = 0x1U << (((LIBERO_SETTING_WAY_ENABLE + 1U) - LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS) );
for(ways_inc = 0; ways_inc < LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS; ++ways_inc)
{
/*
* Populate the scratchpad memory one way at a time.
*/
CACHE_CTRL->WAY_MASK_E51_DCACHE = current_way;
mb();
/*
* Write to the first 64-bit location of each cache block.
*/
for(inc = 0; inc < (WAY_BYTE_LENGTH / CACHE_BLOCK_BYTE_LENGTH); ++inc)
{
*p_scratchpad = g_init_marker + inc;
p_scratchpad += CACHE_BLOCK_BYTE_LENGTH / UINT64_BYTE_LENGTH;
}
current_way = current_way << 1U;
mb();
}
#endif /* (LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS != 0) */
/*
* Prevent E51 from evicting from scratchpad ways.
*/
CACHE_CTRL->WAY_MASK_E51_DCACHE = LIBERO_SETTING_WAY_MASK_E51_DCACHE;
mb();
}
/*==============================================================================
* Configure the L2 scratchpad based on linker symbols:
* __l2_scratchpad_vma_start
* __l2_scratchpad_vma_end
*
* These linker symbols specify the start address and length of the scratchpad.
* The scratchpad must be located within the Zero Device memory range.
*/
static void check_config_l2_scratchpad(void)
{
extern char __l2_scratchpad_vma_start;
extern char __l2_scratchpad_vma_end;
uint8_t n_scratchpad_ways;
const uint64_t end = (const uint64_t)&__l2_scratchpad_vma_end;
const uint64_t start = (const uint64_t)&__l2_scratchpad_vma_start;
uint64_t modulo;
ASSERT(start >= (uint64_t)ZERO_DEVICE_BOTTOM);
ASSERT(end < (uint64_t)ZERO_DEVICE_TOP);
ASSERT(end >= start);
/*
* Figure out how many cache ways will be required from linker script
* symbols.
*/
n_scratchpad_ways = (uint8_t)((end - start) / WAY_BYTE_LENGTH);
modulo = (end - start) % WAY_BYTE_LENGTH;
if(modulo > 0)
{
++n_scratchpad_ways;
}
ASSERT(LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS >= n_scratchpad_ways);
}
#if 0 // todo - remove, no longer used
/*==============================================================================
* Reserve a number of cache ways to be used as scratchpad memory.
*
* @param nways
* Number of ways to be used as scratchpad. One way is 128Kbytes.
*
* @param scratchpad_start
* Start address within the Zero Device memory range in which the scratchpad
* will be located.
*/
static void reserve_scratchpad_ways(uint8_t nways, uint64_t * scratchpad_start)
{
uint8_t way_enable;
uint64_t available_ways = 1;
uint64_t scratchpad_ways = 0;
uint64_t non_scratchpad_ways;
uint32_t inc;
ASSERT(scratchpad_start >= (uint64_t *)ZERO_DEVICE_BOTTOM);
ASSERT(scratchpad_start < (uint64_t *)ZERO_DEVICE_TOP);
/*
* Ensure at least one way remains available as cache.
*/
way_enable = CACHE_CTRL->WAY_ENABLE;
ASSERT(nways <= way_enable);
if(nways <= way_enable)
{
/*
* Compute the mask used to specify ways that will be used by the
* scratchpad.
*/
for(inc = 0; inc < way_enable; ++inc)
{
available_ways = (available_ways << 1) | (uint64_t)0x01;
if(inc < nways)
{
scratchpad_ways = (scratchpad_ways << 1) | (uint64_t)0x01;
}
}
/*
* Prevent other masters from evicting cache lines from scratchpad ways.
* Only allow E51 to evict from scratchpad ways.
*/
non_scratchpad_ways = available_ways & ~scratchpad_ways;
CACHE_CTRL->WAY_MASK_DMA = non_scratchpad_ways;
CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_0 = non_scratchpad_ways;
CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_1 = non_scratchpad_ways;
CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_2 = non_scratchpad_ways;
CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_3 = non_scratchpad_ways;
CACHE_CTRL->WAY_MASK_E51_ICACHE = non_scratchpad_ways;
CACHE_CTRL->WAY_MASK_U54_1_DCACHE = non_scratchpad_ways;
CACHE_CTRL->WAY_MASK_U54_1_ICACHE = non_scratchpad_ways;
CACHE_CTRL->WAY_MASK_U54_2_DCACHE = non_scratchpad_ways;
CACHE_CTRL->WAY_MASK_U54_2_ICACHE = non_scratchpad_ways;
CACHE_CTRL->WAY_MASK_U54_3_DCACHE = non_scratchpad_ways;
CACHE_CTRL->WAY_MASK_U54_3_ICACHE = non_scratchpad_ways;
CACHE_CTRL->WAY_MASK_U54_4_DCACHE = non_scratchpad_ways;
CACHE_CTRL->WAY_MASK_U54_4_ICACHE = non_scratchpad_ways;
/*
* Assign ways to Zero Device
*/
uint64_t * p_scratchpad = scratchpad_start;
int ways_inc;
uint64_t current_way = 1;
for(ways_inc = 0; ways_inc < nways; ++ways_inc)
{
/*
* Populate the scratchpad memory one way at a time.
*/
CACHE_CTRL->WAY_MASK_E51_DCACHE = current_way;
/*
* Write to the first 64-bit location of each cache block.
*/
for(inc = 0; inc < (WAY_BYTE_LENGTH / CACHE_BLOCK_BYTE_LENGTH); ++inc)
{
*p_scratchpad = g_init_marker + inc;
p_scratchpad += CACHE_BLOCK_BYTE_LENGTH / UINT64_BYTE_LENGTH;
}
current_way = current_way << 1U;
mb();
}
/*
* Prevent E51 from evicting from scratchpad ways.
*/
CACHE_CTRL->WAY_MASK_E51_DCACHE = non_scratchpad_ways;
}
}
#endif

532
FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/platform/mpfs_hal/common/mss_l2_cache.h Normal file
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@ -0,0 +1,532 @@
/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/***************************************************************************
* @file mss_l2_cache.h
* @author Microchip-FPGA Embedded Systems Solutions
* @brief MACROs defines and prototypes associated with L2 Cache
*
*/
#ifndef MSS_L2_CACHE_H
#define MSS_L2_CACHE_H
#include <stdint.h>
#include "encoding.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
* The following defines will be present in configurator generated xml Q1 2021
* In the interim, you can manually edit if required.
*/
#if !defined (LIBERO_SETTING_WAY_ENABLE)
/*Way indexes less than or equal to this register value may be used by the
cache. E.g. set to 0x7, will allocate 8 cache ways, 0-7 to cache, and leave
8-15 as LIM. Note 1: Way 0 is always allocated as cache. Note 2: each way is
128KB. */
#define LIBERO_SETTING_WAY_ENABLE 0x00000007UL
/* WAY_ENABLE [0:8] RW value= 0x7 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_DMA)
/*Way mask register master DMA. Set field to zero to disable way from this
master. The available cache ways are 0 to number set in WAY_ENABLE register. If
using scratch pad memory, the ways you want reserved for scrathpad are not
available for selection, you must set to 0. e.g. If three ways reserved for
scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all
masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_DMA 0x0000FFFFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x1 */
/* WAY_MASK_9 [9:1] RW value= 0x1 */
/* WAY_MASK_10 [10:1] RW value= 0x1 */
/* WAY_MASK_11 [11:1] RW value= 0x1 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_0)
/*Way mask register master DMA. Set field to zero to disable way from this
master. The available cache ways are 0 to number set in WAY_ENABLE register. If
using scratch pad memory, the ways you want reserved for scrathpad are not
available for selection, you must set to 0. e.g. If three ways reserved for
scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all
masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_0 0x0000FFFFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x1 */
/* WAY_MASK_9 [9:1] RW value= 0x1 */
/* WAY_MASK_10 [10:1] RW value= 0x1 */
/* WAY_MASK_11 [11:1] RW value= 0x1 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_1)
/*Way mask register master DMA. Set field to zero to disable way from this
master. The available cache ways are 0 to number set in WAY_ENABLE register. If
using scratch pad memory, the ways you want reserved for scrathpad are not
available for selection, you must set to 0. e.g. If three ways reserved for
scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all
masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_1 0x0000FFFFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x1 */
/* WAY_MASK_9 [9:1] RW value= 0x1 */
/* WAY_MASK_10 [10:1] RW value= 0x1 */
/* WAY_MASK_11 [11:1] RW value= 0x1 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_2)
/*Way mask registerAXI slave port 2. Set field to zero to disable way from this
master. The available cache ways are 0 to number set in WAY_ENABLE register. If
using scratch pad memory, the ways you want reserved for scrathpad are not
available for selection, you must set to 0. e.g. If three ways reserved for
scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all
masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_2 0x0000FFFFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x1 */
/* WAY_MASK_9 [9:1] RW value= 0x1 */
/* WAY_MASK_10 [10:1] RW value= 0x1 */
/* WAY_MASK_11 [11:1] RW value= 0x1 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_AXI4_PORT_3)
/*Way mask register AXI slave port 3. Set field to 1 to disable way from this
master. Set field to zero to disable way from this master. The available cache
ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory,
the ways you want reserved for scrathpad are not available for selection, you
must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0,
WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not
evict the way. */
#define LIBERO_SETTING_WAY_MASK_AXI4_PORT_3 0x0000FFFFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x1 */
/* WAY_MASK_9 [9:1] RW value= 0x1 */
/* WAY_MASK_10 [10:1] RW value= 0x1 */
/* WAY_MASK_11 [11:1] RW value= 0x1 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_E51_DCACHE)
/*Way mask register E51 data cache (hart0). Set field to zero to disable way
from this master. The available cache ways are 0 to number set in WAY_ENABLE
register. If using scratch pad memory, the ways you want reserved for scrathpad
are not available for selection, you must set to 0. e.g. If three ways reserved
for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for
all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_E51_DCACHE 0x0000FFFFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x1 */
/* WAY_MASK_9 [9:1] RW value= 0x1 */
/* WAY_MASK_10 [10:1] RW value= 0x1 */
/* WAY_MASK_11 [11:1] RW value= 0x1 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_E51_ICACHE)
/*Way mask registerE52 instruction cache (hart0). Set field to zero to disable
way from this master. The available cache ways are 0 to number set in
WAY_ENABLE register. If using scratch pad memory, the ways you want reserved
for scrathpad are not available for selection, you must set to 0. e.g. If three
ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set
to zero for all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_E51_ICACHE 0x0000FFFFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x1 */
/* WAY_MASK_9 [9:1] RW value= 0x1 */
/* WAY_MASK_10 [10:1] RW value= 0x1 */
/* WAY_MASK_11 [11:1] RW value= 0x1 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_1_DCACHE)
/*Way mask register data cache (hart1). Set field to zero to disable way from
this master. The available cache ways are 0 to number set in WAY_ENABLE
register. If using scratch pad memory, the ways you want reserved for scrathpad
are not available for selection, you must set to 0. e.g. If three ways reserved
for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for
all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_1_DCACHE 0x0000FFFFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x1 */
/* WAY_MASK_9 [9:1] RW value= 0x1 */
/* WAY_MASK_10 [10:1] RW value= 0x1 */
/* WAY_MASK_11 [11:1] RW value= 0x1 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_1_ICACHE)
/*Way mask register instruction cache (hart1). Set field to zero to disable way
from this master. The available cache ways are 0 to number set in WAY_ENABLE
register. If using scratch pad memory, the ways you want reserved for scrathpad
are not available for selection, you must set to 0. e.g. If three ways reserved
for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for
all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_1_ICACHE 0x0000FFFFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x1 */
/* WAY_MASK_9 [9:1] RW value= 0x1 */
/* WAY_MASK_10 [10:1] RW value= 0x1 */
/* WAY_MASK_11 [11:1] RW value= 0x1 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_2_DCACHE)
/*Way mask register data cache (hart2). Set field to 1 to disable way from this
master. Set field to zero to disable way from this master. The available cache
ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory,
the ways you want reserved for scrathpad are not available for selection, you
must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0,
WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not
evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_2_DCACHE 0x0000FFFFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x1 */
/* WAY_MASK_9 [9:1] RW value= 0x1 */
/* WAY_MASK_10 [10:1] RW value= 0x1 */
/* WAY_MASK_11 [11:1] RW value= 0x1 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_2_ICACHE)
/*Way mask register instruction cache (hart2). Set field to zero to disable way
from this master. The available cache ways are 0 to number set in WAY_ENABLE
register. If using scratch pad memory, the ways you want reserved for scrathpad
are not available for selection, you must set to 0. e.g. If three ways reserved
for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for
all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_2_ICACHE 0x0000FFFFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x1 */
/* WAY_MASK_9 [9:1] RW value= 0x1 */
/* WAY_MASK_10 [10:1] RW value= 0x1 */
/* WAY_MASK_11 [11:1] RW value= 0x1 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_3_DCACHE)
/*Way mask register data cache (hart3). Set field to 1 to disable way from this
master.Set field to zero to disable way from this master. The available cache
ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory,
the ways you want reserved for scrathpad are not available for selection, you
must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0,
WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not
evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_3_DCACHE 0x0000FFFFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x1 */
/* WAY_MASK_9 [9:1] RW value= 0x1 */
/* WAY_MASK_10 [10:1] RW value= 0x1 */
/* WAY_MASK_11 [11:1] RW value= 0x1 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_3_ICACHE)
/*Way mask register instruction cache(hart3). Set field to zero to disable way
from this master. The available cache ways are 0 to number set in WAY_ENABLE
register. If using scratch pad memory, the ways you want reserved for scrathpad
are not available for selection, you must set to 0. e.g. If three ways reserved
for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for
all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_3_ICACHE 0x0000FFFFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x1 */
/* WAY_MASK_9 [9:1] RW value= 0x1 */
/* WAY_MASK_10 [10:1] RW value= 0x1 */
/* WAY_MASK_11 [11:1] RW value= 0x1 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_4_DCACHE)
/*Way mask register data cache (hart4). Set field to 1 to disable way from this
master. Set field to zero to disable way from this master. The available cache
ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory,
the ways you want reserved for scrathpad are not available for selection, you
must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0,
WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not
evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_4_DCACHE 0x0000FFFFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x1 */
/* WAY_MASK_9 [9:1] RW value= 0x1 */
/* WAY_MASK_10 [10:1] RW value= 0x1 */
/* WAY_MASK_11 [11:1] RW value= 0x1 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_WAY_MASK_U54_4_ICACHE)
/*Way mask register instruction cache (hart4). Set field to zero to disable way
from this master. The available cache ways are 0 to number set in WAY_ENABLE
register. If using scratch pad memory, the ways you want reserved for scrathpad
are not available for selection, you must set to 0. e.g. If three ways reserved
for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for
all masters, so they can not evict the way. */
#define LIBERO_SETTING_WAY_MASK_U54_4_ICACHE 0x0000FFFFUL
/* WAY_MASK_0 [0:1] RW value= 0x1 */
/* WAY_MASK_1 [1:1] RW value= 0x1 */
/* WAY_MASK_2 [2:1] RW value= 0x1 */
/* WAY_MASK_3 [3:1] RW value= 0x1 */
/* WAY_MASK_4 [4:1] RW value= 0x1 */
/* WAY_MASK_5 [5:1] RW value= 0x1 */
/* WAY_MASK_6 [6:1] RW value= 0x1 */
/* WAY_MASK_7 [7:1] RW value= 0x1 */
/* WAY_MASK_8 [8:1] RW value= 0x1 */
/* WAY_MASK_9 [9:1] RW value= 0x1 */
/* WAY_MASK_10 [10:1] RW value= 0x1 */
/* WAY_MASK_11 [11:1] RW value= 0x1 */
/* WAY_MASK_12 [12:1] RW value= 0x1 */
/* WAY_MASK_13 [13:1] RW value= 0x1 */
/* WAY_MASK_14 [14:1] RW value= 0x1 */
/* WAY_MASK_15 [15:1] RW value= 0x1 */
#endif
#if !defined (LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS)
/*Number of ways reserved for scratchpad. Note 1: This is not a register Note
2: each way is 128KB. Note 3: Embedded software expects cache ways allocated
for scratchpad start at way 0, and work up. */
#define LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS 0x00000000UL
/* NUM_OF_WAYS [0:8] RW value= 0x0 */
#endif
#if !defined (LIBERO_SETTING_L2_SHUTDOWN_CR)
/*Number of ways reserved for scratchpad. Note 1: This is not a register Note
2: each way is 128KB. Note 3: Embedded software expects cache ways allocated
for scratchpad start at way 0, and work up. */
#define LIBERO_SETTING_L2_SHUTDOWN_CR 0x00000000UL
/* NUM_OF_WAYS [0:8] RW value= 0x0 */
#endif
/*==============================================================================
* Define describing cache characteristics.
*/
#define MAX_WAY_ENABLE 15
#define NB_SETS 512
#define NB_BANKS 4
#define CACHE_BLOCK_BYTE_LENGTH 64
#define UINT64_BYTE_LENGTH 8
#define WAY_BYTE_LENGTH (CACHE_BLOCK_BYTE_LENGTH * NB_SETS * NB_BANKS)
#define ZERO_DEVICE_BOTTOM 0x0A000000ULL
#define ZERO_DEVICE_TOP 0x0C000000ULL
#define CACHE_CTRL_BASE 0x02010000ULL
#define INIT_MARKER 0xC0FFEEBEC0010000ULL
#define SHUTDOWN_CACHE_CC24_00_07_MASK 0x01
#define SHUTDOWN_CACHE_CC24_08_15_MASK 0x02
#define SHUTDOWN_CACHE_CC24_16_23_MASK 0x04
#define SHUTDOWN_CACHE_CC24_24_31_MASK 0x08
/*==============================================================================
* Cache controller registers definitions
*/
#define RO volatile const
#define RW volatile
#define WO volatile
typedef struct {
RO uint8_t BANKS;
RO uint8_t WAYS;
RO uint8_t SETS;
RO uint8_t BYTES;
} CACHE_CONFIG_typedef;
typedef struct {
CACHE_CONFIG_typedef CONFIG;
RO uint32_t RESERVED;
RW uint8_t WAY_ENABLE;
RO uint8_t RESERVED0[55];
RW uint32_t ECC_INJECT_ERROR;
RO uint32_t RESERVED1[47];
RO uint64_t ECC_DIR_FIX_ADDR;
RO uint32_t ECC_DIR_FIX_COUNT;
RO uint32_t RESERVED2[13];
RO uint64_t ECC_DATA_FIX_ADDR;
RO uint32_t ECC_DATA_FIX_COUNT;
RO uint32_t RESERVED3[5];
RO uint64_t ECC_DATA_FAIL_ADDR;
RO uint32_t ECC_DATA_FAIL_COUNT;
RO uint32_t RESERVED4[37];
WO uint64_t FLUSH64;
RO uint64_t RESERVED5[7];
WO uint32_t FLUSH32;
RO uint32_t RESERVED6[367];
RW uint64_t WAY_MASK_DMA;
RW uint64_t WAY_MASK_AXI4_SLAVE_PORT_0;
RW uint64_t WAY_MASK_AXI4_SLAVE_PORT_1;
RW uint64_t WAY_MASK_AXI4_SLAVE_PORT_2;
RW uint64_t WAY_MASK_AXI4_SLAVE_PORT_3;
RW uint64_t WAY_MASK_E51_DCACHE;
RW uint64_t WAY_MASK_E51_ICACHE;
RW uint64_t WAY_MASK_U54_1_DCACHE;
RW uint64_t WAY_MASK_U54_1_ICACHE;
RW uint64_t WAY_MASK_U54_2_DCACHE;
RW uint64_t WAY_MASK_U54_2_ICACHE;
RW uint64_t WAY_MASK_U54_3_DCACHE;
RW uint64_t WAY_MASK_U54_3_ICACHE;
RW uint64_t WAY_MASK_U54_4_DCACHE;
RW uint64_t WAY_MASK_U54_4_ICACHE;
} CACHE_CTRL_typedef;
#define CACHE_CTRL ((volatile CACHE_CTRL_typedef *) CACHE_CTRL_BASE)
void config_l2_cache(void);
uint8_t check_num_scratch_ways(uint64_t *start, uint64_t *end);
#ifdef __cplusplus
}
#endif
#endif /* MSS_L2_CACHE_H */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/*******************************************************************************
* @file mss_mpu.c
* @author Microchip-FPGA Embedded Systems Solutions
* @brief PolarFire SoC MSS MPU driver for configuring access regions for the
* external masters.
*
*/
/*=========================================================================*//**
*//*=========================================================================*/
#include <stdio.h>
#include <string.h>
#include "mpfs_hal/mss_hal.h"
#ifndef SIFIVE_HIFIVE_UNLEASHED
static uint64_t pmp_get_napot_base_and_range(uint64_t reg, uint64_t *range);
uint8_t num_pmp_lut[10U] = {16U,16U,8U,4U,8U,8U,4U,4U,8U,2U};
/**
* \brief MPU configuration from Libero for FIC0
*
*/
const uint64_t mpu_fic0_values[] = {
LIBERO_SETTING_FIC0_MPU_CFG_PMP0,
LIBERO_SETTING_FIC0_MPU_CFG_PMP1,
LIBERO_SETTING_FIC0_MPU_CFG_PMP2,
LIBERO_SETTING_FIC0_MPU_CFG_PMP3,
LIBERO_SETTING_FIC0_MPU_CFG_PMP4,
LIBERO_SETTING_FIC0_MPU_CFG_PMP5,
LIBERO_SETTING_FIC0_MPU_CFG_PMP6,
LIBERO_SETTING_FIC0_MPU_CFG_PMP7,
LIBERO_SETTING_FIC0_MPU_CFG_PMP8,
LIBERO_SETTING_FIC0_MPU_CFG_PMP9,
LIBERO_SETTING_FIC0_MPU_CFG_PMP10,
LIBERO_SETTING_FIC0_MPU_CFG_PMP11,
LIBERO_SETTING_FIC0_MPU_CFG_PMP12,
LIBERO_SETTING_FIC0_MPU_CFG_PMP13,
LIBERO_SETTING_FIC0_MPU_CFG_PMP14,
LIBERO_SETTING_FIC0_MPU_CFG_PMP15
};
/**
* \brief MPU configuration from Libero for FIC1
*
*/
const uint64_t mpu_fic1_values[] = {
LIBERO_SETTING_FIC1_MPU_CFG_PMP0,
LIBERO_SETTING_FIC1_MPU_CFG_PMP1,
LIBERO_SETTING_FIC1_MPU_CFG_PMP2,
LIBERO_SETTING_FIC1_MPU_CFG_PMP3,
LIBERO_SETTING_FIC1_MPU_CFG_PMP4,
LIBERO_SETTING_FIC1_MPU_CFG_PMP5,
LIBERO_SETTING_FIC1_MPU_CFG_PMP6,
LIBERO_SETTING_FIC1_MPU_CFG_PMP7,
LIBERO_SETTING_FIC1_MPU_CFG_PMP8,
LIBERO_SETTING_FIC1_MPU_CFG_PMP9,
LIBERO_SETTING_FIC1_MPU_CFG_PMP10,
LIBERO_SETTING_FIC1_MPU_CFG_PMP11,
LIBERO_SETTING_FIC1_MPU_CFG_PMP12,
LIBERO_SETTING_FIC1_MPU_CFG_PMP13,
LIBERO_SETTING_FIC1_MPU_CFG_PMP14,
LIBERO_SETTING_FIC1_MPU_CFG_PMP15
};
/**
* \brief MPU configuration from Libero for FIC2
*
*/
const uint64_t mpu_fic2_values[] = {
LIBERO_SETTING_FIC2_MPU_CFG_PMP0,
LIBERO_SETTING_FIC2_MPU_CFG_PMP1,
LIBERO_SETTING_FIC2_MPU_CFG_PMP2,
LIBERO_SETTING_FIC2_MPU_CFG_PMP3,
LIBERO_SETTING_FIC2_MPU_CFG_PMP4,
LIBERO_SETTING_FIC2_MPU_CFG_PMP5,
LIBERO_SETTING_FIC2_MPU_CFG_PMP6,
LIBERO_SETTING_FIC2_MPU_CFG_PMP7,
};
/**
* \brief MPU configuration from Libero for ATHENA
*
*/
const uint64_t mpu_crypto_values[] = {
LIBERO_SETTING_CRYPTO_MPU_CFG_PMP0,
LIBERO_SETTING_CRYPTO_MPU_CFG_PMP1,
LIBERO_SETTING_CRYPTO_MPU_CFG_PMP2,
LIBERO_SETTING_CRYPTO_MPU_CFG_PMP3,
};
/**
* \brief MPU configuration from Libero for GEM0
*
*/
const uint64_t mpu_gem0_values[] = {
LIBERO_SETTING_GEM0_MPU_CFG_PMP0,
LIBERO_SETTING_GEM0_MPU_CFG_PMP1,
LIBERO_SETTING_GEM0_MPU_CFG_PMP2,
LIBERO_SETTING_GEM0_MPU_CFG_PMP3,
LIBERO_SETTING_GEM0_MPU_CFG_PMP4,
LIBERO_SETTING_GEM0_MPU_CFG_PMP5,
LIBERO_SETTING_GEM0_MPU_CFG_PMP6,
LIBERO_SETTING_GEM0_MPU_CFG_PMP7,
};
/**
* \brief MPU configuration from Libero for GEM1
*
*/
const uint64_t mpu_gem1_values[] = {
LIBERO_SETTING_GEM1_MPU_CFG_PMP0,
LIBERO_SETTING_GEM1_MPU_CFG_PMP1,
LIBERO_SETTING_GEM1_MPU_CFG_PMP2,
LIBERO_SETTING_GEM1_MPU_CFG_PMP3,
LIBERO_SETTING_GEM1_MPU_CFG_PMP4,
LIBERO_SETTING_GEM1_MPU_CFG_PMP5,
LIBERO_SETTING_GEM1_MPU_CFG_PMP6,
LIBERO_SETTING_GEM1_MPU_CFG_PMP7,
};
/**
* \brief MPU configuration from Libero for MMC
*
*/
const uint64_t mpu_mmc_values[] = {
LIBERO_SETTING_MMC_MPU_CFG_PMP0,
LIBERO_SETTING_MMC_MPU_CFG_PMP1,
LIBERO_SETTING_MMC_MPU_CFG_PMP2,
LIBERO_SETTING_MMC_MPU_CFG_PMP3,
};
/**
* \brief MPU configuration from Libero for SCB
*
*/
const uint64_t mpu_scb_values[] = {
LIBERO_SETTING_SCB_MPU_CFG_PMP0,
LIBERO_SETTING_SCB_MPU_CFG_PMP1,
LIBERO_SETTING_SCB_MPU_CFG_PMP2,
LIBERO_SETTING_SCB_MPU_CFG_PMP3,
LIBERO_SETTING_SCB_MPU_CFG_PMP4,
LIBERO_SETTING_SCB_MPU_CFG_PMP5,
LIBERO_SETTING_SCB_MPU_CFG_PMP6,
LIBERO_SETTING_SCB_MPU_CFG_PMP7,
};
/**
* \brief MPU configuration from Libero for USB
*
*/
const uint64_t mpu_usb_values[] = {
LIBERO_SETTING_USB_MPU_CFG_PMP0,
LIBERO_SETTING_USB_MPU_CFG_PMP1,
LIBERO_SETTING_USB_MPU_CFG_PMP2,
LIBERO_SETTING_USB_MPU_CFG_PMP3,
};
/**
* \brief MPU configuration from Libero for TRACE
*
*/
const uint64_t mpu_trace_values[] = {
LIBERO_SETTING_TRACE_MPU_CFG_PMP0,
LIBERO_SETTING_TRACE_MPU_CFG_PMP1,
};
/***************************************************************************//**
* MSS_MPU_auto_configure()
* Set MPU's up with configuration from Libero
*
*
* @return
*/
uint8_t mpu_configure(void)
{
config_64_copy((void *)(&(MSS_MPU(MSS_MPU_FIC0)->PMPCFG)),
&(mpu_fic0_values),
sizeof(mpu_fic0_values));
config_64_copy((void *)(&(MSS_MPU(MSS_MPU_FIC1)->PMPCFG)),
&(mpu_fic1_values),
sizeof(mpu_fic1_values));
config_64_copy((void *)(&(MSS_MPU(MSS_MPU_FIC2)->PMPCFG)),
&(mpu_fic2_values),
sizeof(mpu_fic2_values));
config_64_copy((void *)(&(MSS_MPU(MSS_MPU_CRYPTO)->PMPCFG)),
&(mpu_crypto_values),
sizeof(mpu_crypto_values));
config_64_copy((void *)(&(MSS_MPU(MSS_MPU_GEM0)->PMPCFG)),
&(mpu_gem0_values),
sizeof(mpu_gem0_values));
config_64_copy((void *)(&(MSS_MPU(MSS_MPU_GEM1)->PMPCFG)),
&(mpu_gem1_values),
sizeof(mpu_gem1_values));
config_64_copy((void *)(&(MSS_MPU(MSS_MPU_USB)->PMPCFG)),
&(mpu_usb_values),
sizeof(mpu_usb_values));
config_64_copy((void *)(&(MSS_MPU(MSS_MPU_MMC)->PMPCFG)),
&(mpu_mmc_values),
sizeof(mpu_mmc_values));
config_64_copy((void *)(&(MSS_MPU(MSS_MPU_SCB)->PMPCFG)),
&(mpu_scb_values),
sizeof(mpu_scb_values));
config_64_copy((void *)(&(MSS_MPU(MSS_MPU_TRACE)->PMPCFG)),
&(mpu_trace_values),
sizeof(mpu_trace_values));
return(0);
}
/***************************************************************************//**
*/
uint8_t MSS_MPU_configure(mss_mpu_mport_t master_port,
mss_mpu_pmp_region_t pmp_region,
uint64_t base,
uint64_t size,
uint8_t permission,
mss_mpu_addrm_t matching_mode,
uint8_t lock_en)
{
uint64_t temp = size, cnt=0ULL;
uint64_t range;
/*size must be minimum 4k
Size must be power of 2
different masters have different number of regions*/
if((size >= 4096ULL) && (0U == (size & (size - 1U))) && (pmp_region < num_pmp_lut[master_port]))
{
while((0 == (temp & 0x01U)))
{
cnt++;
temp >>= 1U;
}
range = (1ULL << (cnt-1U))-1U;
MSS_MPU(master_port)->PMPCFG[pmp_region].raw = (base | range) >> 2U;
MSS_MPU(master_port)->PMPCFG[pmp_region].MPUCFG_TypeDef.mode = (uint8_t)(permission |
(uint8_t)(matching_mode << 3U) |
(lock_en << 0x7U));
return ((uint8_t)0);
}
else
{
return ((uint8_t)1);
}
}
uint8_t MSS_MPU_get_config(mss_mpu_mport_t master_port,
mss_mpu_pmp_region_t pmp_region,
uint64_t* base,
uint64_t* size,
uint8_t* permission,
mss_mpu_addrm_t* matching_mode,
uint8_t* lock_en)
{
uint64_t reg;
/*All AXI external masters dont have same number of PMP regions*/
if(pmp_region < num_pmp_lut[master_port])
{
reg = MSS_MPU(master_port)->PMPCFG[pmp_region].MPUCFG_TypeDef.pmp;
*base = pmp_get_napot_base_and_range(reg, size);
reg = MSS_MPU(master_port)->PMPCFG[pmp_region].MPUCFG_TypeDef.mode;
*lock_en = ( reg >> 0x7U) & 0x1U;
*matching_mode = (mss_mpu_addrm_t)( (reg >> 3ULL) & 0x3U);
*permission = reg & 0x7U;
return ((uint8_t)0);
}
else
{
return ((uint8_t)1);
}
}
static uint64_t pmp_get_napot_base_and_range(uint64_t reg, uint64_t *range)
{
/* construct a mask of all bits bar the top bit */
uint64_t mask = 0U;
uint64_t base = reg;
uint64_t numbits = (sizeof(uint64_t) * 8U) + 2U;
mask = (mask - 1U) >> 1U;
while (mask)
{
if ((reg & mask) == mask)
{
/* this is the mask to use */
base = reg & ~mask;
break;
}
mask >>= 1U;
numbits--;
}
*range = (1LU << numbits);
return (base << 2U);
}
#endif

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/*******************************************************************************
* @file mss_mpu.h
* @author Microchip-FPGA Embedded Systems Solutions
* @brief PolarFire SoC MSS MPU driver APIs for configuring access regions for
* the external masters.
*
*/
/*=========================================================================*//**
*//*=========================================================================*/
#ifndef MSS_MPU_H
#define MSS_MPU_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef SIFIVE_HIFIVE_UNLEASHED
/***************************************************************************//**
*/
#define MPU_MODE_READ_ACCESS (1U << 0U)
#define MPU_MODE_WRITE_ACCESS (1U << 1U)
#define MPU_MODE_EXEC_ACCESS (1U << 2U)
typedef enum {
MSS_MPU_FIC0 = 0x00,
MSS_MPU_FIC1,
MSS_MPU_FIC2,
MSS_MPU_CRYPTO,
MSS_MPU_GEM0,
MSS_MPU_GEM1,
MSS_MPU_USB,
MSS_MPU_MMC,
MSS_MPU_SCB,
MSS_MPU_TRACE,
MSS_MPU_SEG0,
MSS_MPU_SEG1,
} mss_mpu_mport_t;
typedef enum {
MSS_MPU_AM_OFF = 0x00U,
MSS_MPU_AM_NAPOT = 0x03U,
} mss_mpu_addrm_t;
typedef enum {
MSS_MPU_PMP_REGION0 = 0x00,
MSS_MPU_PMP_REGION1,
MSS_MPU_PMP_REGION2,
MSS_MPU_PMP_REGION3,
MSS_MPU_PMP_REGION4,
MSS_MPU_PMP_REGION5,
MSS_MPU_PMP_REGION6,
MSS_MPU_PMP_REGION7,
MSS_MPU_PMP_REGION8,
MSS_MPU_PMP_REGION9,
MSS_MPU_PMP_REGION10,
MSS_MPU_PMP_REGION11,
MSS_MPU_PMP_REGION12,
MSS_MPU_PMP_REGION13,
MSS_MPU_PMP_REGION14,
MSS_MPU_PMP_REGION15,
} mss_mpu_pmp_region_t;
extern uint8_t num_pmp_lut[10];
#ifndef __I
#define __I const volatile
#endif
#ifndef __IO
#define __IO volatile
#endif
#ifndef __O
#define __O volatile
#endif
typedef struct {
union {
struct
{
__IO uint64_t pmp : 38;
__IO uint64_t rsrvd : 18;
__IO uint64_t mode : 8;
} MPUCFG_TypeDef;
uint64_t raw;
};
} MPU_CFG;
typedef struct
{
__IO uint64_t addr : 38;
__IO uint64_t rw : 1;
__IO uint64_t id : 4;
__IO uint64_t failed : 1;
__IO uint64_t padding : (64-44);
} MPU_FailStatus_TypeDef;
typedef struct
{
MPU_CFG PMPCFG[16U];
__IO MPU_FailStatus_TypeDef STATUS;
} MPU_TypeDef;
#define MSS_MPU(master) ( (MPU_TypeDef*) (0x20005000UL + ((master) << 8U)))
uint8_t mpu_configure(void);
uint8_t MSS_MPU_configure(mss_mpu_mport_t master_port,
mss_mpu_pmp_region_t pmp_region,
uint64_t base,
uint64_t size,
uint8_t permission,
mss_mpu_addrm_t matching_mode,
uint8_t lock_en);
uint8_t MSS_MPU_get_config(mss_mpu_mport_t master_port,
mss_mpu_pmp_region_t pmp_region,
uint64_t* base,
uint64_t* size,
uint8_t* permission,
mss_mpu_addrm_t* matching_mode,
uint8_t* lock_en);
static inline uint8_t MSS_MPU_lock_region(mss_mpu_mport_t master_port,
mss_mpu_pmp_region_t pmp_region)
{
if(pmp_region < num_pmp_lut[master_port])
{
MSS_MPU(master_port)->PMPCFG[pmp_region].MPUCFG_TypeDef.mode |= (0x1U << 7U);
return (0U);
}
else
{
return (1U);
}
}
/*permission value could be bitwise or of:
* MPU_MODE_READ_ACCESS
* MPU_MODE_WRITE_ACCESS
* MPU_MODE_EXEC_ACCESS
*
* */
static inline uint8_t MSS_MPU_set_permission(mss_mpu_mport_t master_port,
mss_mpu_pmp_region_t pmp_region,
uint8_t permission)
{
if(pmp_region < num_pmp_lut[master_port])
{
MSS_MPU(master_port)->PMPCFG[pmp_region].MPUCFG_TypeDef.mode |= permission;
return (0U);
}
else
{
return (1U);
}
}
static inline uint8_t MSS_MPU_get_permission(mss_mpu_mport_t master_port,
mss_mpu_pmp_region_t pmp_region,
uint8_t* permission)
{
if(pmp_region < num_pmp_lut[master_port])
{
*permission = MSS_MPU(master_port)->PMPCFG[pmp_region].MPUCFG_TypeDef.mode & 0x7U;
return (0U);
}
else
{
return (1U);
}
}
/*read the Fail status register when there is a MPU access failure.
See the return type MPU_FailStatus_TypeDef for the details of the STATUS bitfield.
The status failed bit(offset 42) needs to be reset using the corresponding bit
in SYSREG->mpu_violation_sr
*/
static inline MPU_FailStatus_TypeDef MSS_MPU_get_failstatus(mss_mpu_mport_t master_port)
{
return (MSS_MPU(master_port)->STATUS);
}
#endif /* ! SIFIVE_HIFIVE_UNLEASHED */
#ifdef __cplusplus
}
#endif
#endif /* MSS_MPU_H */

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FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/platform/mpfs_hal/common/mss_mtrap.c Normal file
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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/***************************************************************************
*
* @file mss_mtrap.c
* @author Microchip-FPGA Embedded Systems Solutions
* @brief trap functions
*
*/
#include "mpfs_hal/mss_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
void handle_local_interrupt(uint8_t interrupt_no);
void handle_m_soft_interrupt(void);
void handle_m_timer_interrupt(void);
void illegal_insn_trap(uintptr_t * regs, uintptr_t mcause, uintptr_t mepc);
void misaligned_store_trap(uintptr_t * regs, uintptr_t mcause, uintptr_t mepc);
void misaligned_load_trap(uintptr_t * regs, uintptr_t mcause, uintptr_t mepc);
void pmp_trap(uintptr_t * regs, uintptr_t mcause, uintptr_t mepc);
void trap_from_machine_mode(uintptr_t * regs, uintptr_t dummy, uintptr_t mepc);
void bad_trap(uintptr_t* regs, uintptr_t dummy, uintptr_t mepc);
void bad_trap(uintptr_t* regs, uintptr_t dummy, uintptr_t mepc)
{
(void)regs;
(void)dummy;
(void)mepc;
while(1)
{
}
}
void misaligned_store_trap(uintptr_t * regs, uintptr_t mcause, uintptr_t mepc)
{
(void)regs;
(void)mcause;
(void)mepc;
while(1)
{
}
}
void misaligned_load_trap(uintptr_t * regs, uintptr_t mcause, uintptr_t mepc)
{
(void)regs;
(void)mcause;
(void)mepc;
while(1)
{
}
}
void illegal_insn_trap(uintptr_t * regs, uintptr_t mcause, uintptr_t mepc)
{
(void)regs;
(void)mcause;
(void)mepc;
while(1)
{
}
}
void pmp_trap(uintptr_t * regs, uintptr_t mcause, uintptr_t mepc)
{
(void)regs;
(void)mcause;
(void)mepc;
while(1)
{
}
}
/*------------------------------------------------------------------------------
* RISC-V interrupt handler for external interrupts.
*/
#ifndef SIFIVE_HIFIVE_UNLEASHED
uint8_t (*ext_irq_handler_table[PLIC_NUM_SOURCES])(void) =
{
Invalid_IRQHandler,
l2_metadata_corr_IRQHandler,
l2_metadata_uncorr_IRQHandler,
l2_data_corr_IRQHandler,
l2_data_uncorr_IRQHandler,
dma_ch0_DONE_IRQHandler,
dma_ch0_ERR_IRQHandler,
dma_ch1_DONE_IRQHandler,
dma_ch1_ERR_IRQHandler,
dma_ch2_DONE_IRQHandler,
dma_ch2_ERR_IRQHandler,
dma_ch3_DONE_IRQHandler,
dma_ch3_ERR_IRQHandler,
gpio0_bit0_or_gpio2_bit13_plic_0_IRQHandler,
gpio0_bit1_or_gpio2_bit13_plic_1_IRQHandler,
gpio0_bit2_or_gpio2_bit13_plic_2_IRQHandler,
gpio0_bit3_or_gpio2_bit13_plic_3_IRQHandler,
gpio0_bit4_or_gpio2_bit13_plic_4_IRQHandler,
gpio0_bit5_or_gpio2_bit13_plic_5_IRQHandler,
gpio0_bit6_or_gpio2_bit13_plic_6_IRQHandler,
gpio0_bit7_or_gpio2_bit13_plic_7_IRQHandler,
gpio0_bit8_or_gpio2_bit13_plic_8_IRQHandler,
gpio0_bit9_or_gpio2_bit13_plic_9_IRQHandler,
gpio0_bit10_or_gpio2_bit13_plic_10_IRQHandler,
gpio0_bit11_or_gpio2_bit13_plic_11_IRQHandler,
gpio0_bit12_or_gpio2_bit13_plic_12_IRQHandler,
gpio0_bit13_or_gpio2_bit13_plic_13_IRQHandler,
gpio1_bit0_or_gpio2_bit14_plic_14_IRQHandler,
gpio1_bit1_or_gpio2_bit15_plic_15_IRQHandler,
gpio1_bit2_or_gpio2_bit16_plic_16_IRQHandler,
gpio1_bit3_or_gpio2_bit17_plic_17_IRQHandler,
gpio1_bit4_or_gpio2_bit18_plic_18_IRQHandler,
gpio1_bit5_or_gpio2_bit19_plic_19_IRQHandler,
gpio1_bit6_or_gpio2_bit20_plic_20_IRQHandler,
gpio1_bit7_or_gpio2_bit21_plic_21_IRQHandler,
gpio1_bit8_or_gpio2_bit22_plic_22_IRQHandler,
gpio1_bit9_or_gpio2_bit23_plic_23_IRQHandler,
gpio1_bit10_or_gpio2_bit24_plic_24_IRQHandler,
gpio1_bit11_or_gpio2_bit25_plic_25_IRQHandler,
gpio1_bit12_or_gpio2_bit26_plic_26_IRQHandler,
gpio1_bit13_or_gpio2_bit27_plic_27_IRQHandler,
gpio1_bit14_or_gpio2_bit28_plic_28_IRQHandler,
gpio1_bit15_or_gpio2_bit29_plic_29_IRQHandler,
gpio1_bit16_or_gpio2_bit30_plic_30_IRQHandler,
gpio1_bit17_or_gpio2_bit31_plic_31_IRQHandler,
gpio1_bit18_plic_32_IRQHandler,
gpio1_bit19_plic_33_IRQHandler,
gpio1_bit20_plic_34_IRQHandler,
gpio1_bit21_plic_35_IRQHandler,
gpio1_bit22_plic_36_IRQHandler,
gpio1_bit23_plic_37_IRQHandler,
gpio0_non_direct_plic_IRQHandler,
gpio1_non_direct_plic_IRQHandler,
gpio2_non_direct_plic_IRQHandler,
spi0_plic_IRQHandler,
spi1_plic_IRQHandler,
external_can0_plic_IRQHandler,
can1_IRQHandler,
External_i2c0_main_plic_IRQHandler,
External_i2c0_alert_plic_IRQHandler,
i2c0_sus_plic_IRQHandler,
i2c1_main_plic_IRQHandler,
i2c1_alert_plic_IRQHandler,
i2c1_sus_plic_IRQHandler,
mac0_int_plic_IRQHandler,
mac0_queue1_plic_IRQHandler,
mac0_queue2_plic_IRQHandler,
mac0_queue3_plic_IRQHandler,
mac0_emac_plic_IRQHandler,
mac0_mmsl_plic_IRQHandler,
mac1_int_plic_IRQHandler,
mac1_queue1_plic_IRQHandler,
mac1_queue2_plic_IRQHandler,
mac1_queue3_plic_IRQHandler,
mac1_emac_plic_IRQHandler,
mac1_mmsl_plic_IRQHandler,
ddrc_train_plic_IRQHandler,
scb_interrupt_plic_IRQHandler,
ecc_error_plic_IRQHandler,
ecc_correct_plic_IRQHandler,
rtc_wakeup_plic_IRQHandler,
rtc_match_plic_IRQHandler,
timer1_plic_IRQHandler,
timer2_plic_IRQHandler,
envm_plic_IRQHandler,
qspi_plic_IRQHandler,
usb_dma_plic_IRQHandler,
usb_mc_plic_IRQHandler,
mmc_main_plic_IRQHandler,
mmc_wakeup_plic_IRQHandler,
mmuart0_plic_77_IRQHandler,
mmuart1_plic_IRQHandler,
mmuart2_plic_IRQHandler,
mmuart3_plic_IRQHandler,
mmuart4_plic_IRQHandler,
g5c_devrst_plic_IRQHandler,
g5c_message_plic_IRQHandler,
usoc_vc_interrupt_plic_IRQHandler,
usoc_smb_interrupt_plic_IRQHandler,
e51_0_Maintence_plic_IRQHandler,
wdog0_mvrp_plic_IRQHandler,
wdog1_mvrp_plic_IRQHandler, /*100 contains multiple interrupts- */
wdog2_mvrp_plic_IRQHandler,
wdog3_mvrp_plic_IRQHandler,
wdog4_mvrp_plic_IRQHandler,
wdog0_tout_plic_IRQHandler,
wdog1_tout_plic_IRQHandler,
wdog2_tout_plic_IRQHandler,
wdog3_tout_plic_IRQHandler,
wdog4_tout_plic_IRQHandler,
g5c_mss_spi_plic_IRQHandler,
volt_temp_alarm_plic_IRQHandler,
athena_complete_plic_IRQHandler,
athena_alarm_plic_IRQHandler,
athena_bus_error_plic_IRQHandler,
usoc_axic_us_plic_IRQHandler,
usoc_axic_ds_plic_IRQHandler,
reserved_104_plic_IRQHandler,
fabric_f2h_0_plic_IRQHandler,
fabric_f2h_1_plic_IRQHandler,
fabric_f2h_2_plic_IRQHandler,
fabric_f2h_3_plic_IRQHandler,
fabric_f2h_4_plic_IRQHandler,
fabric_f2h_5_plic_IRQHandler,
fabric_f2h_6_plic_IRQHandler,
fabric_f2h_7_plic_IRQHandler,
fabric_f2h_8_plic_IRQHandler,
fabric_f2h_9_plic_IRQHandler,
fabric_f2h_10_plic_IRQHandler,
fabric_f2h_11_plic_IRQHandler,
fabric_f2h_12_plic_IRQHandler,
fabric_f2h_13_plic_IRQHandler,
fabric_f2h_14_plic_IRQHandler,
fabric_f2h_15_plic_IRQHandler,
fabric_f2h_16_plic_IRQHandler,
fabric_f2h_17_plic_IRQHandler,
fabric_f2h_18_plic_IRQHandler,
fabric_f2h_19_plic_IRQHandler,
fabric_f2h_20_plic_IRQHandler,
fabric_f2h_21_plic_IRQHandler,
fabric_f2h_22_plic_IRQHandler,
fabric_f2h_23_plic_IRQHandler,
fabric_f2h_24_plic_IRQHandler,
fabric_f2h_25_plic_IRQHandler,
fabric_f2h_26_plic_IRQHandler,
fabric_f2h_27_plic_IRQHandler,
fabric_f2h_28_plic_IRQHandler,
fabric_f2h_29_plic_IRQHandler,
fabric_f2h_30_plic_IRQHandler,
fabric_f2h_31_plic_IRQHandler,
fabric_f2h_32_plic_IRQHandler,
fabric_f2h_33_plic_IRQHandler,
fabric_f2h_34_plic_IRQHandler,
fabric_f2h_35_plic_IRQHandler,
fabric_f2h_36_plic_IRQHandler,
fabric_f2h_37_plic_IRQHandler,
fabric_f2h_38_plic_IRQHandler,
fabric_f2h_39_plic_IRQHandler,
fabric_f2h_40_plic_IRQHandler,
fabric_f2h_41_plic_IRQHandler,
fabric_f2h_42_plic_IRQHandler,
fabric_f2h_43_plic_IRQHandler,
fabric_f2h_44_plic_IRQHandler,
fabric_f2h_45_plic_IRQHandler,
fabric_f2h_46_plic_IRQHandler,
fabric_f2h_47_plic_IRQHandler,
fabric_f2h_48_plic_IRQHandler,
fabric_f2h_49_plic_IRQHandler,
fabric_f2h_50_plic_IRQHandler,
fabric_f2h_51_plic_IRQHandler,
fabric_f2h_52_plic_IRQHandler,
fabric_f2h_53_plic_IRQHandler,
fabric_f2h_54_plic_IRQHandler,
fabric_f2h_55_plic_IRQHandler,
fabric_f2h_56_plic_IRQHandler,
fabric_f2h_57_plic_IRQHandler,
fabric_f2h_58_plic_IRQHandler,
fabric_f2h_59_plic_IRQHandler,
fabric_f2h_60_plic_IRQHandler,
fabric_f2h_61_plic_IRQHandler,
fabric_f2h_62_plic_IRQHandler,
fabric_f2h_63_plic_IRQHandler,
bus_error_unit_hart_0_plic_IRQHandler,
bus_error_unit_hart_1_plic_IRQHandler,
bus_error_unit_hart_2_plic_IRQHandler,
bus_error_unit_hart_3_plic_IRQHandler,
bus_error_unit_hart_4_plic_IRQHandler
};
#define E51_LOCAL_NUM_SOURCES 48U
void (*local_irq_handler_e51_table[E51_LOCAL_NUM_SOURCES])(void) =
{
maintenance_e51_local_IRQHandler_0, /* reference multiple interrupts */
usoc_smb_interrupt_e51_local_IRQHandler_1,
usoc_vc_interrupt_e51_local_IRQHandler_2,
g5c_message_e51_local_IRQHandler_3,
g5c_devrst_e51_local_IRQHandler_4,
wdog4_tout_e51_local_IRQHandler_5,
wdog3_tout_e51_local_IRQHandler_6,
wdog2_tout_e51_local_IRQHandler_7,
wdog1_tout_e51_local_IRQHandler_8,
wdog0_tout_e51_local_IRQHandler_9,
wdog0_mvrp_e51_local_IRQHandler_10,
mmuart0_e51_local_IRQHandler_11,
envm_e51_local_IRQHandler_12,
ecc_correct_e51_local_IRQHandler_13,
ecc_error_e51_local_IRQHandler_14,
scb_interrupt_e51_local_IRQHandler_15,
fabric_f2h_32_e51_local_IRQHandler_16,
fabric_f2h_33_e51_local_IRQHandler_17,
fabric_f2h_34_e51_local_IRQHandler_18,
fabric_f2h_35_e51_local_IRQHandler_19,
fabric_f2h_36_e51_local_IRQHandler_20,
fabric_f2h_37_e51_local_IRQHandler_21,
fabric_f2h_38_e51_local_IRQHandler_22,
fabric_f2h_39_e51_local_IRQHandler_23,
fabric_f2h_40_e51_local_IRQHandler_24,
fabric_f2h_41_e51_local_IRQHandler_25,
fabric_f2h_42_e51_local_IRQHandler_26,
fabric_f2h_43_e51_local_IRQHandler_27,
fabric_f2h_44_e51_local_IRQHandler_28,
fabric_f2h_45_e51_local_IRQHandler_29,
fabric_f2h_46_e51_local_IRQHandler_30,
fabric_f2h_47_e51_local_IRQHandler_31,
fabric_f2h_48_e51_local_IRQHandler_32,
fabric_f2h_49_e51_local_IRQHandler_33,
fabric_f2h_50_e51_local_IRQHandler_34,
fabric_f2h_51_e51_local_IRQHandler_35,
fabric_f2h_52_e51_local_IRQHandler_36,
fabric_f2h_53_e51_local_IRQHandler_37,
fabric_f2h_54_e51_local_IRQHandler_38,
fabric_f2h_55_e51_local_IRQHandler_39,
fabric_f2h_56_e51_local_IRQHandler_40,
fabric_f2h_57_e51_local_IRQHandler_41,
fabric_f2h_58_e51_local_IRQHandler_42,
fabric_f2h_59_e51_local_IRQHandler_43,
fabric_f2h_60_e51_local_IRQHandler_44,
fabric_f2h_61_e51_local_IRQHandler_45,
fabric_f2h_62_e51_local_IRQHandler_46,
fabric_f2h_63_e51_local_IRQHandler_47
};
typedef void (*local_int_p_t)(void);
/* U54 1 */
local_int_p_t local_irq_handler_u54_1_table[E51_LOCAL_NUM_SOURCES] =
{
/*reference multiple interrupts*/
spare_u54_local_IRQHandler_0,
spare_u54_local_IRQHandler_1,
spare_u54_local_IRQHandler_2,
/*parse hart ID to discover which mac is the source*/
mac_mmsl_u54_1_local_IRQHandler_3,
mac_emac_u54_1_local_IRQHandler_4,
mac_queue3_u54_1_local_IRQHandler_5,
mac_queue2_u54_1_local_IRQHandler_6,
mac_queue1_u54_1_local_IRQHandler_7,
mac_int_u54_1_local_IRQHandler_8,
/*parse hart ID to discover which wdog is the source*/
wdog_tout_u54_h1_local_IRQHandler_9,
mvrp_u54_local_IRQHandler_10,
mmuart_u54_h1_local_IRQHandler_11,
spare_u54_local_IRQHandler_12,
spare_u54_local_IRQHandler_13,
spare_u54_local_IRQHandler_14,
spare_u54_local_IRQHandler_15,
fabric_f2h_0_u54_local_IRQHandler_16,
fabric_f2h_1_u54_local_IRQHandler_17,
fabric_f2h_2_u54_local_IRQHandler_18,
fabric_f2h_3_u54_local_IRQHandler_19,
fabric_f2h_4_u54_local_IRQHandler_20,
fabric_f2h_5_u54_local_IRQHandler_21,
fabric_f2h_6_u54_local_IRQHandler_22,
fabric_f2h_7_u54_local_IRQHandler_23,
fabric_f2h_8_u54_local_IRQHandler_24,
fabric_f2h_9_u54_local_IRQHandler_25,
fabric_f2h_10_u54_local_IRQHandler_26,
fabric_f2h_11_u54_local_IRQHandler_27,
fabric_f2h_12_u54_local_IRQHandler_28,
fabric_f2h_13_u54_local_IRQHandler_29,
fabric_f2h_14_u54_local_IRQHandler_30,
fabric_f2h_15_u54_local_IRQHandler_31,
fabric_f2h_16_u54_local_IRQHandler_32,
fabric_f2h_17_u54_local_IRQHandler_33,
fabric_f2h_18_u54_local_IRQHandler_34,
fabric_f2h_19_u54_local_IRQHandler_35,
fabric_f2h_20_u54_local_IRQHandler_36,
fabric_f2h_21_u54_local_IRQHandler_37,
fabric_f2h_22_u54_local_IRQHandler_38,
fabric_f2h_23_u54_local_IRQHandler_39,
fabric_f2h_24_u54_local_IRQHandler_40,
fabric_f2h_25_u54_local_IRQHandler_41,
fabric_f2h_26_u54_local_IRQHandler_42,
fabric_f2h_27_u54_local_IRQHandler_43,
fabric_f2h_28_u54_local_IRQHandler_44,
fabric_f2h_29_u54_local_IRQHandler_45,
fabric_f2h_30_u54_local_IRQHandler_46,
fabric_f2h_31_u54_local_IRQHandler_47
};
/* U54 2 */
local_int_p_t local_irq_handler_u54_2_table[E51_LOCAL_NUM_SOURCES] =
{
/*reference multiple interrupts*/
spare_u54_local_IRQHandler_0,
spare_u54_local_IRQHandler_1,
spare_u54_local_IRQHandler_2,
/*parse hart ID to discover which mac is the source*/
mac_mmsl_u54_2_local_IRQHandler_3,
mac_emac_u54_2_local_IRQHandler_4,
mac_queue3_u54_2_local_IRQHandler_5,
mac_queue2_u54_2_local_IRQHandler_6,
mac_queue1_u54_2_local_IRQHandler_7,
mac_int_u54_2_local_IRQHandler_8,
/*parse hart ID to discover which wdog is the source*/
wdog_tout_u54_h2_local_IRQHandler_9,
mvrp_u54_local_IRQHandler_10,
mmuart_u54_h2_local_IRQHandler_11,
spare_u54_local_IRQHandler_12,
spare_u54_local_IRQHandler_13,
spare_u54_local_IRQHandler_14,
spare_u54_local_IRQHandler_15,
fabric_f2h_0_u54_local_IRQHandler_16,
fabric_f2h_1_u54_local_IRQHandler_17,
fabric_f2h_2_u54_local_IRQHandler_18,
fabric_f2h_3_u54_local_IRQHandler_19,
fabric_f2h_4_u54_local_IRQHandler_20,
fabric_f2h_5_u54_local_IRQHandler_21,
fabric_f2h_6_u54_local_IRQHandler_22,
fabric_f2h_7_u54_local_IRQHandler_23,
fabric_f2h_8_u54_local_IRQHandler_24,
fabric_f2h_9_u54_local_IRQHandler_25,
fabric_f2h_10_u54_local_IRQHandler_26,
fabric_f2h_11_u54_local_IRQHandler_27,
fabric_f2h_12_u54_local_IRQHandler_28,
fabric_f2h_13_u54_local_IRQHandler_29,
fabric_f2h_14_u54_local_IRQHandler_30,
fabric_f2h_15_u54_local_IRQHandler_31,
fabric_f2h_16_u54_local_IRQHandler_32,
fabric_f2h_17_u54_local_IRQHandler_33,
fabric_f2h_18_u54_local_IRQHandler_34,
fabric_f2h_19_u54_local_IRQHandler_35,
fabric_f2h_20_u54_local_IRQHandler_36,
fabric_f2h_21_u54_local_IRQHandler_37,
fabric_f2h_22_u54_local_IRQHandler_38,
fabric_f2h_23_u54_local_IRQHandler_39,
fabric_f2h_24_u54_local_IRQHandler_40,
fabric_f2h_25_u54_local_IRQHandler_41,
fabric_f2h_26_u54_local_IRQHandler_42,
fabric_f2h_27_u54_local_IRQHandler_43,
fabric_f2h_28_u54_local_IRQHandler_44,
fabric_f2h_29_u54_local_IRQHandler_45,
fabric_f2h_30_u54_local_IRQHandler_46,
fabric_f2h_31_u54_local_IRQHandler_47
};
/* U54 3 */
local_int_p_t local_irq_handler_u54_3_table[E51_LOCAL_NUM_SOURCES] =
{
/*reference multiple interrupts*/
spare_u54_local_IRQHandler_0,
spare_u54_local_IRQHandler_1,
spare_u54_local_IRQHandler_2,
/*parse hart ID to discover which mac is the source*/
mac_mmsl_u54_3_local_IRQHandler_3,
mac_emac_u54_3_local_IRQHandler_4,
mac_queue3_u54_3_local_IRQHandler_5,
mac_queue2_u54_3_local_IRQHandler_6,
mac_queue1_u54_3_local_IRQHandler_7,
mac_int_u54_3_local_IRQHandler_8,
/*parse hart ID to discover which wdog is the source*/
wdog_tout_u54_h3_local_IRQHandler_9,
mvrp_u54_local_IRQHandler_10,
mmuart_u54_h3_local_IRQHandler_11,
spare_u54_local_IRQHandler_12,
spare_u54_local_IRQHandler_13,
spare_u54_local_IRQHandler_14,
spare_u54_local_IRQHandler_15,
fabric_f2h_0_u54_local_IRQHandler_16,
fabric_f2h_1_u54_local_IRQHandler_17,
fabric_f2h_2_u54_local_IRQHandler_18,
fabric_f2h_3_u54_local_IRQHandler_19,
fabric_f2h_4_u54_local_IRQHandler_20,
fabric_f2h_5_u54_local_IRQHandler_21,
fabric_f2h_6_u54_local_IRQHandler_22,
fabric_f2h_7_u54_local_IRQHandler_23,
fabric_f2h_8_u54_local_IRQHandler_24,
fabric_f2h_9_u54_local_IRQHandler_25,
fabric_f2h_10_u54_local_IRQHandler_26,
fabric_f2h_11_u54_local_IRQHandler_27,
fabric_f2h_12_u54_local_IRQHandler_28,
fabric_f2h_13_u54_local_IRQHandler_29,
fabric_f2h_14_u54_local_IRQHandler_30,
fabric_f2h_15_u54_local_IRQHandler_31,
fabric_f2h_16_u54_local_IRQHandler_32,
fabric_f2h_17_u54_local_IRQHandler_33,
fabric_f2h_18_u54_local_IRQHandler_34,
fabric_f2h_19_u54_local_IRQHandler_35,
fabric_f2h_20_u54_local_IRQHandler_36,
fabric_f2h_21_u54_local_IRQHandler_37,
fabric_f2h_22_u54_local_IRQHandler_38,
fabric_f2h_23_u54_local_IRQHandler_39,
fabric_f2h_24_u54_local_IRQHandler_40,
fabric_f2h_25_u54_local_IRQHandler_41,
fabric_f2h_26_u54_local_IRQHandler_42,
fabric_f2h_27_u54_local_IRQHandler_43,
fabric_f2h_28_u54_local_IRQHandler_44,
fabric_f2h_29_u54_local_IRQHandler_45,
fabric_f2h_30_u54_local_IRQHandler_46,
fabric_f2h_31_u54_local_IRQHandler_47
};
/* U54 4 */
local_int_p_t local_irq_handler_u54_4_table[E51_LOCAL_NUM_SOURCES] =
{
/*reference multiple interrupts*/
spare_u54_local_IRQHandler_0,
spare_u54_local_IRQHandler_1,
spare_u54_local_IRQHandler_2,
/*parse hart ID to discover which mac is the source*/
mac_mmsl_u54_4_local_IRQHandler_3,
mac_emac_u54_4_local_IRQHandler_4,
mac_queue3_u54_4_local_IRQHandler_5,
mac_queue2_u54_4_local_IRQHandler_6,
mac_queue1_u54_4_local_IRQHandler_7,
mac_int_u54_4_local_IRQHandler_8,
/*parse hart ID to discover which wdog is the source*/
wdog_tout_u54_h4_local_IRQHandler_9,
mvrp_u54_local_IRQHandler_10,
mmuart_u54_h4_local_IRQHandler_11,
spare_u54_local_IRQHandler_12,
spare_u54_local_IRQHandler_13,
spare_u54_local_IRQHandler_14,
spare_u54_local_IRQHandler_15,
fabric_f2h_0_u54_local_IRQHandler_16,
fabric_f2h_1_u54_local_IRQHandler_17,
fabric_f2h_2_u54_local_IRQHandler_18,
fabric_f2h_3_u54_local_IRQHandler_19,
fabric_f2h_4_u54_local_IRQHandler_20,
fabric_f2h_5_u54_local_IRQHandler_21,
fabric_f2h_6_u54_local_IRQHandler_22,
fabric_f2h_7_u54_local_IRQHandler_23,
fabric_f2h_8_u54_local_IRQHandler_24,
fabric_f2h_9_u54_local_IRQHandler_25,
fabric_f2h_10_u54_local_IRQHandler_26,
fabric_f2h_11_u54_local_IRQHandler_27,
fabric_f2h_12_u54_local_IRQHandler_28,
fabric_f2h_13_u54_local_IRQHandler_29,
fabric_f2h_14_u54_local_IRQHandler_30,
fabric_f2h_15_u54_local_IRQHandler_31,
fabric_f2h_16_u54_local_IRQHandler_32,
fabric_f2h_17_u54_local_IRQHandler_33,
fabric_f2h_18_u54_local_IRQHandler_34,
fabric_f2h_19_u54_local_IRQHandler_35,
fabric_f2h_20_u54_local_IRQHandler_36,
fabric_f2h_21_u54_local_IRQHandler_37,
fabric_f2h_22_u54_local_IRQHandler_38,
fabric_f2h_23_u54_local_IRQHandler_39,
fabric_f2h_24_u54_local_IRQHandler_40,
fabric_f2h_25_u54_local_IRQHandler_41,
fabric_f2h_26_u54_local_IRQHandler_42,
fabric_f2h_27_u54_local_IRQHandler_43,
fabric_f2h_28_u54_local_IRQHandler_44,
fabric_f2h_29_u54_local_IRQHandler_45,
fabric_f2h_30_u54_local_IRQHandler_46,
fabric_f2h_31_u54_local_IRQHandler_47
};
local_int_p_t *local_int_mux[5] =
{
local_irq_handler_e51_table,
local_irq_handler_u54_1_table,
local_irq_handler_u54_2_table,
local_irq_handler_u54_3_table,
local_irq_handler_u54_4_table
};
#else
uint8_t (*ext_irq_handler_table[PLIC_NUM_SOURCES])(void) =
{
Invalid_IRQHandler,
External_1_IRQHandler,
External_2_IRQHandler,
External_3_IRQHandler,
USART0_plic_4_IRQHandler,
External_5_IRQHandler,
External_6_IRQHandler,
External_7_IRQHandler,
External_8_IRQHandler,
External_9_IRQHandler,
External_10_IRQHandler,
External_11_IRQHandler,
External_12_IRQHandler,
External_13_IRQHandler,
External_14_IRQHandler,
External_15_IRQHandler,
External_16_IRQHandler,
External_17_IRQHandler,
External_18_IRQHandler,
External_19_IRQHandler,
External_20_IRQHandler,
External_21_IRQHandler,
External_22_IRQHandler,
dma_ch0_DONE_IRQHandler,
dma_ch0_ERR_IRQHandler,
dma_ch1_DONE_IRQHandler,
dma_ch1_ERR_IRQHandler,
dma_ch2_DONE_IRQHandler,
dma_ch2_ERR_IRQHandler,
dma_ch3_DONE_IRQHandler,
dma_ch3_ERR_IRQHandler,
External_31_IRQHandler,
External_32_IRQHandler,
External_33_IRQHandler,
External_34_IRQHandler,
External_35_IRQHandler,
External_36_IRQHandler,
External_37_IRQHandler,
External_38_IRQHandler,
External_39_IRQHandler,
External_40_IRQHandler,
External_41_IRQHandler,
External_42_IRQHandler,
External_43_IRQHandler,
External_44_IRQHandler,
External_45_IRQHandler,
External_46_IRQHandler,
External_47_IRQHandler,
External_48_IRQHandler,
External_49_IRQHandler,
External_50_IRQHandler,
External_51_IRQHandler,
External_52_IRQHandler,
MAC0_plic_53_IRQHandler
};
#endif
/*------------------------------------------------------------------------------
*
*/
void handle_m_ext_interrupt(void)
{
volatile uint32_t int_num = PLIC_ClaimIRQ();
if (INVALID_IRQn == int_num)
{
return;
}
uint8_t disable = EXT_IRQ_KEEP_ENABLED;
#ifndef SIFIVE_HIFIVE_UNLEASHED
disable = ext_irq_handler_table[int_num /* + OFFSET_TO_MSS_GLOBAL_INTS Think this was required in early bitfile */]();
#else
disable = ext_irq_handler_table[int_num]();
#endif
PLIC_CompleteIRQ(int_num);
if(EXT_IRQ_DISABLE == disable)
{
PLIC_DisableIRQ((PLIC_IRQn_Type)int_num);
}
}
/*------------------------------------------------------------------------------
*
*/
void handle_local_interrupt(uint8_t interrupt_no)
{
#ifndef SIFIVE_HIFIVE_UNLEASHED /* no local interrupts on unleashed */
uint64_t mhart_id = read_csr(mhartid);
uint8_t local_interrupt_no = (uint8_t)(interrupt_no - 16U);
local_int_p_t *local_int_table = local_int_mux[mhart_id];
(*local_int_table[local_interrupt_no])();
#endif
}
/*------------------------------------------------------------------------------
*
*/
void trap_from_machine_mode(uintptr_t * regs, uintptr_t dummy, uintptr_t mepc)
{
volatile uintptr_t mcause = read_csr(mcause);
if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) > 15U)&& ((mcause & MCAUSE_CAUSE) < 64U))
{
handle_local_interrupt((uint8_t)(mcause & MCAUSE_CAUSE));
}
else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT))
{
handle_m_ext_interrupt();
}
else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT))
{
handle_m_soft_interrupt();
}
else if (((mcause & MCAUSE_INT) == MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER))
{
handle_m_timer_interrupt();
}
else
{
uint32_t i = 0U;
while(1)
{
/* wait for watchdog */
i++; /* added some code as SC debugger hangs if in loop doing nothing */
if(i == 0x1000U)
{
i = mcause; /* so mcause is not optimised out */
}
}
switch(mcause)
{
case CAUSE_LOAD_PAGE_FAULT:
break;
case CAUSE_STORE_PAGE_FAULT:
break;
case CAUSE_FETCH_ACCESS:
break;
case CAUSE_LOAD_ACCESS:
break;
case CAUSE_STORE_ACCESS:
break;
default:
bad_trap(regs, dummy, mepc);
break;
}
}
}
#ifdef __cplusplus
}
#endif

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/*
Copyright (c) 2013, The Regents of the University of California (Regents).
All Rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Regents nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
*/
/***********************************************************************************
* Record of Microchip changes
*/
#ifndef RISCV_MTRAP_H
#define RISCV_MTRAP_H
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __ASSEMBLER__
#define read_const_csr(reg) ({ unsigned long __tmp; \
asm ("csrr %0, " #reg : "=r"(__tmp)); \
__tmp; })
#endif
#define IPI_SOFT 0x01
#define IPI_FENCE_I 0x02
#define IPI_SFENCE_VMA 0x04
#define MACHINE_STACK_SIZE (RISCV_PGSIZE) /* this is 4k for HLS and 4k for the stack*/
#define MENTRY_HLS_OFFSET (INTEGER_CONTEXT_SIZE + SOFT_FLOAT_CONTEXT_SIZE)
#define MENTRY_FRAME_SIZE (MENTRY_HLS_OFFSET + HLS_SIZE)
#define MENTRY_IPI_OFFSET (MENTRY_HLS_OFFSET)
#define MENTRY_IPI_PENDING_OFFSET (MENTRY_HLS_OFFSET + REGBYTES)
#ifdef __riscv_flen
# define SOFT_FLOAT_CONTEXT_SIZE (0)
#else
# define SOFT_FLOAT_CONTEXT_SIZE (8 * 32)
#endif
#define HLS_SIZE (64)
#define INTEGER_CONTEXT_SIZE (32 * REGBYTES)
#ifndef __ASSEMBLER__
typedef struct {
volatile uint32_t * ipi;
volatile int mipi_pending;
volatile int padding;
volatile uint64_t * timecmp;
volatile uint32_t * plic_m_thresh;
volatile uintptr_t * plic_m_ie;
volatile uint32_t * plic_s_thresh;
volatile uintptr_t * plic_s_ie;
} hls_t;
/* This code relies on the stack being allocated on a 4K boundary */
/* also can not be bigger than 4k */
#define MACHINE_STACK_TOP() ({ \
register uintptr_t sp asm ("sp"); \
(void *)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); })
// hart-local storage
#define HLS() ((hls_t*)(MACHINE_STACK_TOP() - HLS_SIZE))
#define OTHER_HLS(id) ((hls_t*)((void *)HLS() + RISCV_PGSIZE * ((id) - read_const_csr(mhartid))))
#endif
#ifdef __cplusplus
}
#endif
#endif /*RISCV_MTRAP_H*/

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/*******************************************************************************
* @file mss_peripherals.c
* @author Microchip-FPGA Embedded Systems Solutions
* @brief PolarFire SoC MSS functions related to peripherals.
*
*/
/*=========================================================================*//**
*//*=========================================================================*/
#include <stdio.h>
#include <string.h>
#include "mpfs_hal/mss_hal.h"
const uint32_t LIBERO_SETTING_CONTEXT_EN[][2U] = {
{LIBERO_SETTING_CONTEXT_A_EN,
LIBERO_SETTING_CONTEXT_B_EN},
{LIBERO_SETTING_CONTEXT_A_EN_FIC,
LIBERO_SETTING_CONTEXT_B_EN_FIC},
};
/* offsets used in PERIPHERAL_SETUP array */
#define PERIPHERAL_INDEX_OFFSET 0U /* used for sanity check */
#define CONTEXT_EN_INDEX_OFFSET 1U
#define CONTEXT_MASK_INDEX_OFFSET 2U
#define CONTEXT_SUBCLK_INDEX_OFFSET 3U
const uint32_t PERIPHERAL_SETUP[][4U] = {
{MSS_PERIPH_MMUART0,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_MMUART0,SUBBLK_CLOCK_CR_MMUART0_MASK},
{MSS_PERIPH_MMUART1,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_MMUART1,SUBBLK_CLOCK_CR_MMUART1_MASK},
{MSS_PERIPH_MMUART2,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_MMUART2,SUBBLK_CLOCK_CR_MMUART2_MASK},
{MSS_PERIPH_MMUART3,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_MMUART3,SUBBLK_CLOCK_CR_MMUART3_MASK},
{MSS_PERIPH_MMUART4,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_MMUART4,SUBBLK_CLOCK_CR_MMUART4_MASK},
{MSS_PERIPH_WDOG0,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_WDOG0,SUBBLK_CLOCK_NA_MASK},
{MSS_PERIPH_WDOG1,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_WDOG1,SUBBLK_CLOCK_NA_MASK},
{MSS_PERIPH_WDOG2,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_WDOG2,SUBBLK_CLOCK_NA_MASK},
{MSS_PERIPH_WDOG3,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_WDOG3,SUBBLK_CLOCK_NA_MASK},
{MSS_PERIPH_WDOG4,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_WDOG4,SUBBLK_CLOCK_NA_MASK},
{MSS_PERIPH_SPI0,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_SPI0,SUBBLK_CLOCK_CR_SPI0_MASK},
{MSS_PERIPH_SPI1,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_SPI1,SUBBLK_CLOCK_CR_SPI1_MASK},
{MSS_PERIPH_I2C0,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_I2C0,SUBBLK_CLOCK_CR_I2C0_MASK},
{MSS_PERIPH_I2C1,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_I2C1,SUBBLK_CLOCK_CR_I2C1_MASK},
{MSS_PERIPH_CAN0,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_CAN0,SUBBLK_CLOCK_CR_CAN0_MASK},
{MSS_PERIPH_CAN1,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_CAN1,SUBBLK_CLOCK_CR_CAN1_MASK},
{MSS_PERIPH_MAC0,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_MAC0,SUBBLK_CLOCK_CR_MAC0_MASK},
{MSS_PERIPH_MAC1,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_MAC1,SUBBLK_CLOCK_CR_MAC1_MASK},
{MSS_PERIPH_TIMER,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_TIMER,SUBBLK_CLOCK_CR_TIMER_MASK},
{MSS_PERIPH_GPIO0,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_GPIO0,SUBBLK_CLOCK_CR_GPIO0_MASK},
{MSS_PERIPH_GPIO1,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_GPIO1,SUBBLK_CLOCK_CR_GPIO1_MASK},
{MSS_PERIPH_GPIO2,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_GPIO2,SUBBLK_CLOCK_CR_GPIO2_MASK},
{MSS_PERIPH_RTC,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_RTC,SUBBLK_CLOCK_CR_RTC_MASK},
{MSS_PERIPH_H2FINT,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_H2FINT, SUBBLK_CLOCK_NA_MASK},
{MSS_PERIPH_CRYPTO,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_CRYPTO,SUBBLK_CLOCK_CR_ATHENA_MASK},
{MSS_PERIPH_USB,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_USB,SUBBLK_CLOCK_CR_USB_MASK},
{MSS_PERIPH_QSPIXIP,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_QSPIXIP,SUBBLK_CLOCK_CR_QSPI_MASK},
{MSS_PERIPH_ATHENA,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_ATHENA,SUBBLK_CLOCK_CR_ATHENA_MASK},
{MSS_PERIPH_TRACE,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_MMC,SUBBLK_CLOCK_CR_MMC_MASK},
{MSS_PERIPH_MAILBOX_SC,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_MMC,SUBBLK_CLOCK_CR_MMC_MASK},
{MSS_PERIPH_EMMC,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_MMC,SUBBLK_CLOCK_CR_MMC_MASK},
{MSS_PERIPH_CFM,CONTEXT_EN_INDEX, CONTEXT_EN_MASK_CFM,SUBBLK_CLOCK_CR_CFM_MASK},
{MSS_PERIPH_FIC0,CONTEXT_EN_INDEX_FIC, CONTEXT_EN_MASK_FIC0,SUBBLK_CLOCK_CR_FIC0_MASK},
{MSS_PERIPH_FIC1,CONTEXT_EN_INDEX_FIC, CONTEXT_EN_MASK_FIC1,SUBBLK_CLOCK_CR_FIC1_MASK},
{MSS_PERIPH_FIC2,CONTEXT_EN_INDEX_FIC, CONTEXT_EN_MASK_FIC2,SUBBLK_CLOCK_CR_FIC2_MASK},
{MSS_PERIPH_FIC3,CONTEXT_EN_INDEX_FIC, CONTEXT_EN_MASK_FIC3,SUBBLK_CLOCK_CR_FIC3_MASK}
};
/**
* If contexts set-up, verify allowed access to peripheral
* @param option - Two option, , FIC enables set separately. CONTEXT_EN_INDEX_FIC or CONTEXT_EN_INDEX
* @param periph_context_mask See CONTEXT_EN_MASK_ defines for options
* @param hart The hart ID of origin of request.
* @return
*/
static inline uint8_t verify_context_enable(uint8_t option, uint32_t periph_context_mask , uint32_t hart)
{
uint8_t result = 1U;
#if ((LIBERO_SETTING_MEM_CONFIGS_ENABLED & PMP_ENABLED_MASK) == PMP_ENABLED_MASK)
if (hart != (uint8_t) 0U)
{
if (LIBERO_SETTING_CONTEXT_A_HART_EN & hart )
{
if (LIBERO_SETTING_CONTEXT_EN[option][0U] & periph_context_mask)
{
result = 0U;
}
}
if (LIBERO_SETTING_CONTEXT_B_HART_EN & hart )
{
if (LIBERO_SETTING_CONTEXT_EN[option][1U] & periph_context_mask)
{
result = 0U;
}
}
}
else
{
hart = 0U;
}
#else
(void)hart;
(void)periph_context_mask;
(void)option;
result = 0U;
#endif
return result;
}
/**
* Turn on/off mss peripheral as required
* @param peripheral_mask
* @param req_state
*/
static inline void peripheral_on_off(uint32_t peripheral_mask , PERIPH_RESET_STATE req_state)
{
if (req_state == PERIPHERAL_OFF)
{
/* Turn off clock */
SYSREG->SUBBLK_CLOCK_CR &= (uint32_t)~(peripheral_mask);
/* Hold in reset */
SYSREG->SOFT_RESET_CR |= (uint32_t)(peripheral_mask);
}
else
{
/* Turn on clock */
SYSREG->SUBBLK_CLOCK_CR |= (peripheral_mask);
/* Remove soft reset */
SYSREG->SOFT_RESET_CR &= (uint32_t)~(peripheral_mask);
}
}
/***************************************************************************//**
* See mss_peripherals.h for details of how to use this function.
*/
__attribute__((weak)) uint8_t mss_config_clk_rst(mss_peripherals peripheral, uint8_t hart, PERIPH_RESET_STATE req_state)
{
uint8_t result = 1U;
ASSERT(PERIPHERAL_SETUP[peripheral][PERIPHERAL_INDEX_OFFSET] == peripheral);
result = verify_context_enable(PERIPHERAL_SETUP[peripheral][CONTEXT_EN_INDEX_OFFSET], PERIPHERAL_SETUP[peripheral][CONTEXT_MASK_INDEX_OFFSET] , hart);
if (result == 0U)
{
peripheral_on_off(PERIPHERAL_SETUP[peripheral][CONTEXT_SUBCLK_INDEX_OFFSET] , req_state);
}
return result;
}

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/*******************************************************************************
* @file mss_peripherals.h
* @author Microchip-FPGA Embedded Systems Solutions
* @brief PolarFire SoC MSS fumnctions related to MSS peripherals.
*
*/
/*=========================================================================*//**
*//*=========================================================================*/
#ifndef MSS_PERIPHERALS_H
#define MSS_PERIPHERALS_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_CONTEXT_A_EN)
#define LIBERO_SETTING_CONTEXT_A_EN 0x00000000UL
#endif
#if !defined (LIBERO_SETTING_CONTEXT_B_EN)
#define LIBERO_SETTING_CONTEXT_B_EN 0x00000000UL
#endif
#if !defined (LIBERO_SETTING_CONTEXT_A_EN_FIC)
#define LIBERO_SETTING_CONTEXT_A_EN_FIC 0x0000000FUL
#endif
#if !defined (LIBERO_SETTING_CONTEXT_B_EN_FIC)
#define LIBERO_SETTING_CONTEXT_B_EN_FIC 0x0000000FUL
#endif
/***************************************************************************//**
*/
typedef enum PERIPH_RESET_STATE_
{
PERIPHERAL_ON = 0x00, /*!< 0 RST and clk ON */
PERIPHERAL_OFF = 0x01, /*!< 1 RST and clk OFF */
} PERIPH_RESET_STATE;
#define CONTEXT_EN_INDEX 0x00U
#define CONTEXT_EN_INDEX_FIC 0x01U
#define SUBBLK_CLOCK_NA_MASK 0x00U
typedef enum mss_peripherals_ {
MSS_PERIPH_MMUART0 = 0U,
MSS_PERIPH_MMUART1 = 1U,
MSS_PERIPH_MMUART2 = 2U,
MSS_PERIPH_MMUART3 = 3U,
MSS_PERIPH_MMUART4 = 4U,
MSS_PERIPH_WDOG0 = 5U,
MSS_PERIPH_WDOG1 = 6U,
MSS_PERIPH_WDOG2 = 7U,
MSS_PERIPH_WDOG3 = 8U,
MSS_PERIPH_WDOG4 = 9U,
MSS_PERIPH_SPI0 = 10U,
MSS_PERIPH_SPI1 = 11U,
MSS_PERIPH_I2C0 = 12U,
MSS_PERIPH_I2C1 = 13U,
MSS_PERIPH_CAN0 = 14U,
MSS_PERIPH_CAN1 = 15U,
MSS_PERIPH_MAC0 = 16U,
MSS_PERIPH_MAC1 = 17U,
MSS_PERIPH_TIMER = 18U,
MSS_PERIPH_GPIO0 = 19U,
MSS_PERIPH_GPIO1 = 20U,
MSS_PERIPH_GPIO2 = 21U,
MSS_PERIPH_RTC = 22U,
MSS_PERIPH_H2FINT = 23U,
MSS_PERIPH_CRYPTO = 24U,
MSS_PERIPH_USB = 25U,
MSS_PERIPH_QSPIXIP = 26U,
MSS_PERIPH_ATHENA = 27U,
MSS_PERIPH_TRACE = 28U,
MSS_PERIPH_MAILBOX_SC = 29U,
MSS_PERIPH_EMMC = 30U,
MSS_PERIPH_CFM = 31U,
MSS_PERIPH_FIC0 = 32U,
MSS_PERIPH_FIC1 = 33U,
MSS_PERIPH_FIC2 = 34U,
MSS_PERIPH_FIC3 = 35U
} mss_peripherals;
/***************************************************************************//**
This function is used to turn on or off a peripheral. If contexts have been
configured, these will be checked to see if peripheral should be controlled
from a particular context.
@param peripheral
See enum mss_peripherals for list of peripherals
@param hart
Origin hart of this request
@req_state
Turn peripheral on or off:
- PERIPHERAL_ON
- PERIPHERAL_OFF
Example:
@code
uint8_t err_status;
err_status = mss_config_clk_rst(MSS_PERIPH_MMUART0, (uint8_t) origin_hart_ID, PERIPHERAL_ON);
if(0U != err_status)
{
print_uart0("\n\r Context not allowed to access UART0 from hart:%d\n\nr", origin_hart_ID);
}
@endcode
*/
uint8_t mss_config_clk_rst(mss_peripherals peripheral, uint8_t hart, PERIPH_RESET_STATE req_state);
#ifdef __cplusplus
}
#endif
#endif /* MSS_PERIPHERALS_H */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/*******************************************************************************
*
* @file mss_plic.c
* @author Microchip-FPGA Embedded Systems Solutions
* @brief PolarFire SoC MSS PLIC and PRCI access data structures and functions.
*
* PLIC related data which cannot be placed in mss_plic.h
*
*/
#include "mpfs_hal/mss_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
const unsigned long plic_hart_lookup[5U] = {0U, 1U, 3U, 5U, 7U};
#ifdef __cplusplus
}
#endif

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/*******************************************************************************
* @file mss_pmp.c
* @author Microchip-FPGA Embedded Systems Solutions
* @brief PolarFire SoC MSS PMP configuration using MSS configurator values.
*
*/
/*=========================================================================*//**
*//*=========================================================================*/
#include <stdio.h>
#include <string.h>
#include "mpfs_hal/mss_hal.h"
/**
* \brief PMP configuration from Libero
*
*/
const uint64_t pmp_values[][18] = {
/* hart 0 */
{LIBERO_SETTING_HART0_CSR_PMPCFG0,
LIBERO_SETTING_HART0_CSR_PMPCFG2,
LIBERO_SETTING_HART0_CSR_PMPADDR0,
LIBERO_SETTING_HART0_CSR_PMPADDR1,
LIBERO_SETTING_HART0_CSR_PMPADDR2,
LIBERO_SETTING_HART0_CSR_PMPADDR3,
LIBERO_SETTING_HART0_CSR_PMPADDR4,
LIBERO_SETTING_HART0_CSR_PMPADDR5,
LIBERO_SETTING_HART0_CSR_PMPADDR6,
LIBERO_SETTING_HART0_CSR_PMPADDR7,
LIBERO_SETTING_HART0_CSR_PMPADDR8,
LIBERO_SETTING_HART0_CSR_PMPADDR9,
LIBERO_SETTING_HART0_CSR_PMPADDR10,
LIBERO_SETTING_HART0_CSR_PMPADDR11,
LIBERO_SETTING_HART0_CSR_PMPADDR12,
LIBERO_SETTING_HART0_CSR_PMPADDR13,
LIBERO_SETTING_HART0_CSR_PMPADDR14,
LIBERO_SETTING_HART0_CSR_PMPADDR15},
/* hart 1 */
{LIBERO_SETTING_HART1_CSR_PMPCFG0,
LIBERO_SETTING_HART1_CSR_PMPCFG2,
LIBERO_SETTING_HART1_CSR_PMPADDR0,
LIBERO_SETTING_HART1_CSR_PMPADDR1,
LIBERO_SETTING_HART1_CSR_PMPADDR2,
LIBERO_SETTING_HART1_CSR_PMPADDR3,
LIBERO_SETTING_HART1_CSR_PMPADDR4,
LIBERO_SETTING_HART1_CSR_PMPADDR5,
LIBERO_SETTING_HART1_CSR_PMPADDR6,
LIBERO_SETTING_HART1_CSR_PMPADDR7,
LIBERO_SETTING_HART1_CSR_PMPADDR8,
LIBERO_SETTING_HART1_CSR_PMPADDR9,
LIBERO_SETTING_HART1_CSR_PMPADDR10,
LIBERO_SETTING_HART1_CSR_PMPADDR11,
LIBERO_SETTING_HART1_CSR_PMPADDR12,
LIBERO_SETTING_HART1_CSR_PMPADDR13,
LIBERO_SETTING_HART1_CSR_PMPADDR14,
LIBERO_SETTING_HART1_CSR_PMPADDR15},
/* hart 2 */
{LIBERO_SETTING_HART2_CSR_PMPCFG0,
LIBERO_SETTING_HART2_CSR_PMPCFG2,
LIBERO_SETTING_HART2_CSR_PMPADDR0,
LIBERO_SETTING_HART2_CSR_PMPADDR1,
LIBERO_SETTING_HART2_CSR_PMPADDR2,
LIBERO_SETTING_HART2_CSR_PMPADDR3,
LIBERO_SETTING_HART2_CSR_PMPADDR4,
LIBERO_SETTING_HART2_CSR_PMPADDR5,
LIBERO_SETTING_HART2_CSR_PMPADDR6,
LIBERO_SETTING_HART2_CSR_PMPADDR7,
LIBERO_SETTING_HART2_CSR_PMPADDR8,
LIBERO_SETTING_HART2_CSR_PMPADDR9,
LIBERO_SETTING_HART2_CSR_PMPADDR10,
LIBERO_SETTING_HART2_CSR_PMPADDR11,
LIBERO_SETTING_HART2_CSR_PMPADDR12,
LIBERO_SETTING_HART2_CSR_PMPADDR13,
LIBERO_SETTING_HART2_CSR_PMPADDR14,
LIBERO_SETTING_HART2_CSR_PMPADDR15},
/* hart 3 */
{LIBERO_SETTING_HART3_CSR_PMPCFG0,
LIBERO_SETTING_HART3_CSR_PMPCFG2,
LIBERO_SETTING_HART3_CSR_PMPADDR0,
LIBERO_SETTING_HART3_CSR_PMPADDR1,
LIBERO_SETTING_HART3_CSR_PMPADDR2,
LIBERO_SETTING_HART3_CSR_PMPADDR3,
LIBERO_SETTING_HART3_CSR_PMPADDR4,
LIBERO_SETTING_HART3_CSR_PMPADDR5,
LIBERO_SETTING_HART3_CSR_PMPADDR6,
LIBERO_SETTING_HART3_CSR_PMPADDR7,
LIBERO_SETTING_HART3_CSR_PMPADDR8,
LIBERO_SETTING_HART3_CSR_PMPADDR9,
LIBERO_SETTING_HART3_CSR_PMPADDR10,
LIBERO_SETTING_HART3_CSR_PMPADDR11,
LIBERO_SETTING_HART3_CSR_PMPADDR12,
LIBERO_SETTING_HART3_CSR_PMPADDR13,
LIBERO_SETTING_HART3_CSR_PMPADDR14,
LIBERO_SETTING_HART3_CSR_PMPADDR15},
/* hart 4 */
{LIBERO_SETTING_HART4_CSR_PMPCFG0,
LIBERO_SETTING_HART4_CSR_PMPCFG2,
LIBERO_SETTING_HART4_CSR_PMPADDR0,
LIBERO_SETTING_HART4_CSR_PMPADDR1,
LIBERO_SETTING_HART4_CSR_PMPADDR2,
LIBERO_SETTING_HART4_CSR_PMPADDR3,
LIBERO_SETTING_HART4_CSR_PMPADDR4,
LIBERO_SETTING_HART4_CSR_PMPADDR5,
LIBERO_SETTING_HART4_CSR_PMPADDR6,
LIBERO_SETTING_HART4_CSR_PMPADDR7,
LIBERO_SETTING_HART4_CSR_PMPADDR8,
LIBERO_SETTING_HART4_CSR_PMPADDR9,
LIBERO_SETTING_HART4_CSR_PMPADDR10,
LIBERO_SETTING_HART4_CSR_PMPADDR11,
LIBERO_SETTING_HART4_CSR_PMPADDR12,
LIBERO_SETTING_HART4_CSR_PMPADDR13,
LIBERO_SETTING_HART4_CSR_PMPADDR14,
LIBERO_SETTING_HART4_CSR_PMPADDR15},
};
/**
* pmp_configure()
* Set PMP's up with configuration from Libero
* @param hart_id hart Id
* @return
*/
uint8_t pmp_configure(uint8_t hart_id) /* set-up with settings from Libero */
{
#if ((LIBERO_SETTING_MEM_CONFIGS_ENABLED & PMP_ENABLED_MASK) == PMP_ENABLED_MASK)
uint64_t pmp0cfg;
#endif
/* make sure enables are off */
write_csr(pmpcfg0, 0);
write_csr(pmpcfg2, 0);
/* set required addressing */
write_csr(pmpaddr0, pmp_values[hart_id][2]);
write_csr(pmpaddr1, pmp_values[hart_id][3]);
write_csr(pmpaddr2, pmp_values[hart_id][4]);
write_csr(pmpaddr3, pmp_values[hart_id][5]);
write_csr(pmpaddr4, pmp_values[hart_id][6]);
write_csr(pmpaddr5, pmp_values[hart_id][7]);
write_csr(pmpaddr6, pmp_values[hart_id][8]);
write_csr(pmpaddr7, pmp_values[hart_id][9]);
write_csr(pmpaddr8, pmp_values[hart_id][10]);
write_csr(pmpaddr9, pmp_values[hart_id][11]);
write_csr(pmpaddr10, pmp_values[hart_id][12]);
write_csr(pmpaddr11, pmp_values[hart_id][13]);
write_csr(pmpaddr12, pmp_values[hart_id][14]);
write_csr(pmpaddr13, pmp_values[hart_id][15]);
write_csr(pmpaddr14, pmp_values[hart_id][16]);
write_csr(pmpaddr15, pmp_values[hart_id][17]);
#if ((LIBERO_SETTING_MEM_CONFIGS_ENABLED & PMP_ENABLED_MASK) == PMP_ENABLED_MASK)
pmp0cfg = pmp_values[hart_id][0];
pmp_master_configs(hart_id, &pmp0cfg);
write_csr(pmpcfg0, pmp0cfg);
write_csr(pmpcfg2, pmp_values[hart_id][1]);
#endif
return(0);
}
/*-------------------------------------------------------------------------*//**
Please note the first four PMP's are set to zero by MSS Configurator v2021.1
These will need to be set by the HSS. The first three relate to HSS footprint
The PMP4 is used to open a hole for debug region.
| PMP | cfg | L | XWR | Detail |
|-----|-----------|-----|----------------------------------------------------|
| 0 | 0x18 | N | | 256KB | Closes access for s and U mode |
| 1 | 0x98 | Y | X R | 256KB | Opens up area for m-mode only |
| 2 | 0x98 | Y | XRW | 64KB | OpenSBI scratch per scratch |
| 3 | 0x98 | Y | XRW | 4KB | Open window for debug |
| .. | .. | .. | .. | .. | .. |
| 15 | 0x18 | Y | | - | Close everything not opened |
@param pmp0cfg return with config for first four PMP's
*/
__attribute__((weak)) void pmp_master_configs(uint8_t hart_id, uint64_t * pmp0cfg)
{
if ( hart_id == 0U )
{
*pmp0cfg = LIBERO_SETTING_HART0_CSR_PMPCFG0;
write_csr(pmpaddr0, pmp_values[hart_id][2]);
write_csr(pmpaddr1, pmp_values[hart_id][3]);
write_csr(pmpaddr2, pmp_values[hart_id][4]);
write_csr(pmpaddr3, pmp_values[hart_id][5]);
}
else
{
/*
* Example of closed memory map, must be created based on HSS footprint
*/
#define CLOSE_S_U_ACCESS_HSS_PMP0_LIM_EG0 0x2007FFFULL /* 256K LIM */
#define CLOSE_S_U_ACCESS_HSS_PMP0_LIM_EG1 0x200FFFFULL /* 512K LIM */
#define OPEN_M_ACCESS_HSS_PMP1_LIM_EG0 0x2007FFFULL /* 256K LIM */
#define OPEN_M_ACCESS_HSS_PMP1_LIM_EG1 0x200FFFFULL /* 512K LIM */
#define OPEN_M_ACCESS_HSS_PMP1_SCRATCH_EG 0x280FFFFULL /* 512K SCRATCHPAD */
#define OPEN_CONTEXT_ACCESS_LIM_PMP2_H1 0x2011FFFULL /* 64K LIM */
#define OPEN_CONTEXT_ACCESS_LIM_PMP2_H2 0x2015FFFULL /* 64K LIM */
#define OPEN_DEBUG_ACCESS_PMP3 0x1FFULL
#define HSS_CLOSED_CFG_MASK ~0xFFFFFFFFULL
#define HSS_CLOSED_CFG 0x9F9F9D18ULL
/*
* We will open 512K LIM and scratchpad in weak pmp_master_configs()
* for all harts.
*/
#define LIM_512K_FROM_BASE 0x200FFFFULL /* 512K LIM */
#define SCRATCH_512K_FROM_BASE 0x280FFFFULL /* 512K LIM */
*pmp0cfg &= HSS_CLOSED_CFG_MASK;
*pmp0cfg |= 0x9F009F9FULL; /* open 0,1 and 3 to allow open access */
write_csr(pmpaddr0, OPEN_M_ACCESS_HSS_PMP1_LIM_EG1);
write_csr(pmpaddr1, OPEN_M_ACCESS_HSS_PMP1_SCRATCH_EG);
write_csr(pmpaddr2, 0ULL);
write_csr(pmpaddr3, OPEN_DEBUG_ACCESS_PMP3);
}
/*
*
*/
#define LOCAL_PMP_SETTINGS
#ifdef LOCAL_PMP_SETTINGS
#endif
return;
}

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/*******************************************************************************
* @file mss_pmp.h
* @author Microchip-FPGA Embedded Systems Solutions
* @brief PolarFire SoC MSS PMP configuration using MSS configurator values.
*
*/
/*=========================================================================*//**
*//*=========================================================================*/
#ifndef MSS_PMP_H
#define MSS_PMP_H
#ifdef __cplusplus
extern "C" {
#endif
#if !defined (LIBERO_SETTING_MEM_CONFIGS_ENABLED)
#define LIBERO_SETTING_MEM_CONFIGS_ENABLED 0ULL
/* Enabled when bit set to 1 */
/* PMP [0:0] RW value= 0x0 */
/* MPU [1:0] RW value= 0x0 */
#endif
#define PMP_ENABLED_MASK 1UL
#define MPU_ENABLED_MASK 2UL
/*
* Bit offsets associated with LIBERO_SETTING_CONTEXT_A_HART_EN and
* LIBERO_SETTING_CONTEXT_B_HART_EN
*/
#define CONTEXT_EN_MASK_MMUART0 (1U<<0)
#define CONTEXT_EN_MASK_MMUART1 (1U<<1)
#define CONTEXT_EN_MASK_MMUART2 (1U<<2)
#define CONTEXT_EN_MASK_MMUART3 (1U<<3)
#define CONTEXT_EN_MASK_MMUART4 (1U<<4)
#define CONTEXT_EN_MASK_WDOG0 (1U<<5)
#define CONTEXT_EN_MASK_WDOG1 (1U<<6)
#define CONTEXT_EN_MASK_WDOG2 (1U<<7)
#define CONTEXT_EN_MASK_WDOG3 (1U<<8)
#define CONTEXT_EN_MASK_WDOG4 (1U<<9)
#define CONTEXT_EN_MASK_SPI0 (1U<<10)
#define CONTEXT_EN_MASK_SPI1 (1U<<11)
#define CONTEXT_EN_MASK_I2C0 (1U<<12)
#define CONTEXT_EN_MASK_I2C1 (1U<<13)
#define CONTEXT_EN_MASK_CAN0 (1U<<14)
#define CONTEXT_EN_MASK_CAN1 (1U<<15)
#define CONTEXT_EN_MASK_MAC0 (1U<<16)
#define CONTEXT_EN_MASK_MAC1 (1U<<17)
#define CONTEXT_EN_MASK_TIMER (1U<<18)
#define CONTEXT_EN_MASK_GPIO0 (1U<<19)
#define CONTEXT_EN_MASK_GPIO1 (1U<<20)
#define CONTEXT_EN_MASK_GPIO2 (1U<<21)
#define CONTEXT_EN_MASK_RTC (1U<<22)
#define CONTEXT_EN_MASK_H2FINT (1U<<23)
#define CONTEXT_EN_MASK_CRYPTO (1U<<24)
#define CONTEXT_EN_MASK_USB (1U<<25)
#define CONTEXT_EN_MASK_QSPIXIP (1U<<26)
#define CONTEXT_EN_MASK_ATHENA (1U<<27)
#define CONTEXT_EN_MASK_TRACE (1U<<28)
#define CONTEXT_EN_MASK_MAILBOX_SC (1U<<29)
#define CONTEXT_EN_MASK_MMC (1U<<30)
#define CONTEXT_EN_MASK_CFM (1U<<31)
/*
* Bit offsets associated with LIBERO_SETTING_CONTEXT_A_FIC_EN and
* LIBERO_SETTING_CONTEXT_B_FIC_EN
*/
#define CONTEXT_EN_MASK_FIC0 (1U<<0)
#define CONTEXT_EN_MASK_FIC1 (1U<<1)
#define CONTEXT_EN_MASK_FIC2 (1U<<2)
#define CONTEXT_EN_MASK_FIC3 (1U<<3)
uint8_t pmp_configure(uint8_t hart_id);
void pmp_master_configs(uint8_t hart_id, uint64_t * pmp0cfg);
#ifdef __cplusplus
}
#endif
#endif /* MSS_PMP_H */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/***************************************************************************
*
* @file mss_seg.h
* @author Microchip-FPGA Embedded Systems Solutions
* @brief segmentation block defines
*
* These blocks allow the DDR memory to be allocated to cached, non-cached
* regions and trace depending on the amount of DDR memory physically connected.
* Conceptually an address offset is added/subtracted from the DDR address
* provided by the Core Complex to point at a base address in the DDR memory.
*
* The AXI bus simply passes through the segmentation block, and the address
* is modified.
*
* There are two segmentation blocks, they are grouped into the same address
* ranges as the MPU blocks. Each one has seven 32-segmentation registers, but
* only two in SEG0 and five in SEG1 are actually implemented.
*
* DDRC blocker - blocks writes to DDR before it is set-up
* SEG0.CFG[7]
* Is cleared at reset. When written to '1' disables the blocker function
* Is allowing the L2 cache controller to access the DDRC.
* Is Once written to '1' the register cannot be written to 0, only an MSS reset
* Is will clear the register
*
*/
#ifndef MSS_SEG_H
#define MSS_SEG_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
union {
struct {
volatile int32_t offset : 15;
volatile int32_t rsrvd : 16;
volatile int32_t locked : 1;
} CFG;
uint32_t raw;
} u[8u];
uint32_t fill[64U-8U];
} seg_t;
#define SEG ((seg_t*) 0x20005d00)
#ifdef __cplusplus
}
#endif
#endif /*MSS_SEG_H*/

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/***************************************************************************
* @file mss_util.c
* @author Microchip-FPGA Embedded Systems Solutions
* @brief Utility functions
*
*/
#include <stddef.h>
#include <stdbool.h>
#include "mpfs_hal/mss_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------
*
*/
void enable_interrupts(void) {
__enable_irq();
}
/*------------------------------------------------------------------------------
*
*/
uint64_t disable_interrupts(void) {
uint64_t psr;
psr = read_csr(mstatus);
__disable_irq();
return(psr);
}
/*------------------------------------------------------------------------------
*
*/
void restore_interrupts(uint64_t saved_psr) {
write_csr(mstatus, saved_psr);
}
/*------------------------------------------------------------------------------
* Disable all interrupts.
*/
void __disable_irq(void)
{
clear_csr(mstatus, MSTATUS_MIE);
clear_csr(mstatus, MSTATUS_MPIE);
}
void __disable_all_irqs(void)
{
__disable_irq();
write_csr(mie, 0x00U);
write_csr(mip, 0x00);
}
/*------------------------------------------------------------------------------
* Enable all interrupts.
*/
void __enable_irq(void)
{
set_csr(mstatus, MSTATUS_MIE); /* mstatus Register- Machine Interrupt Enable */
}
/*------------------------------------------------------------------------------
* Enable particular local interrupt
*/
void __enable_local_irq(uint8_t local_interrupt)
{
if((local_interrupt > (int8_t)0) && (local_interrupt <= LOCAL_INT_MAX))
{
set_csr(mie, (0x1LLU << (int8_t)(local_interrupt + 16U))); /* mie Register- Machine Interrupt Enable Register */
}
}
/*------------------------------------------------------------------------------
* Disable particular local interrupt
*/
void __disable_local_irq(uint8_t local_interrupt)
{
if((local_interrupt > (int8_t)0) && (local_interrupt <= LOCAL_INT_MAX))
{
clear_csr(mie, (0x1LLU << (int8_t)(local_interrupt + 16U))); /* mie Register- Machine Interrupt Enable Register */
}
}
/**
* readmcycle(void)
* @return returns the mcycle count from hart CSR
*/
uint64_t readmcycle(void)
{
return (read_csr(mcycle));
}
void sleep_ms(uint64_t msecs)
{
uint64_t starttime = readmtime();
volatile uint64_t endtime = 0U;
while(endtime < (starttime+msecs)) {
endtime = readmtime();
}
}
/**
* sleep_cycles(uint64_t ncycles)
* @param number of cycles to sleep
*/
void sleep_cycles(uint64_t ncycles)
{
uint64_t starttime = readmcycle();
volatile uint64_t endtime = 0U;
while(endtime < (starttime + ncycles)) {
endtime = readmcycle();
}
}
/**
* get_program_counter(void)
* @return returns the program counter
*/
__attribute__((aligned(16))) uint64_t get_program_counter(void)
{
uint64_t prog_counter;
asm volatile ("auipc %0, 0" : "=r"(prog_counter));
return (prog_counter);
}
/**
* get_stack_pointer(void)
* @return Return the stack pointer
*/
uint64_t get_stack_pointer(void)
{
uint64_t stack_pointer;
asm volatile ("addi %0, sp, 0" : "=r"(stack_pointer));
return (stack_pointer);
}
/**
* Return the tp register
* The tp register holds the value of the Hart Common memory HLS once not in an
* interrupt. If the tp value is used in an interrupt, it is saved first and
* restored on exit. This conforms to OpenSBI implementation.
*
* @return returns the tp register value
*/
uint64_t get_tp_reg(void)
{
uint64_t tp_reg_val;
asm volatile ("addi %0, tp, 0" : "=r"(tp_reg_val));
return (tp_reg_val);
}
/**
* mpfs_sync_bool_compare_and_swap()
* this works on the E51 / U54s, and operates equivalently to the
* __sync_bool_compare_and_swap() intrinsic.
* @param ptr
* @param oldval
* @param newval
* @return
*/
bool mpfs_sync_bool_compare_and_swap(volatile long *ptr, long oldval, long newval)
{
static long lock = 0;
bool result = false;
if (!__sync_lock_test_and_set(&lock, 1)) { // amoswap.d.aq
if (*ptr == oldval) {
*ptr = newval;
}
__sync_lock_release(&lock); // fence iorw,ow; ampswap.d
result = true;
}
return result;
}
/**
* mpfs_sync_val_compare_and_swap()
* this works on the E51 / U54s, and operates equivalently to the
* __sync_val_compare_and_swap() intrinsic. It works by using a separate
* static lock, and then emulating the behaviour of the lr.w.aq instruction
* Required as lr/sr instructions are not supported on the E51 and are only
* supported on L1 cached back memory types. These limitations are not present
* with this function.
* @param ptr
* @param oldval
* @param newval
*/
long mpfs_sync_val_compare_and_swap(volatile long *ptr, long oldval, long newval)
{
long result = *ptr;
(void)mpfs_sync_bool_compare_and_swap(ptr, oldval, newval);
return result;
}
#ifdef PRINTF_DEBUG_SUPPORTED
void display_address_of_interest(uint64_t * address_of_interest, int nb_locations) {
uint64_t * p_addr_of_interest = address_of_interest;
int inc;
mpfs_printf(" Displaying address of interest: 0x%lx\n", p_addr_of_interest);
for (inc = 0U; inc < nb_locations; ++inc) {
mpfs_printf(" address of interest: 0x%lx: 0x%lx\n", p_addr_of_interest, *p_addr_of_interest);
p_addr_of_interest = p_addr_of_interest + 8;
}
}
#endif
#ifdef __cplusplus
}
#endif

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
* SPDX-License-Identifier: MIT
*
* MPFS HAL Embedded Software
*
*/
/***************************************************************************
* @file mss_util.h
* @author Microchip-FPGA Embedded Systems Solutions
* @brief MACROs defines and prototypes associated with utility functions
*
*/
#ifndef MSS_UTIL_H
#define MSS_UTIL_H
#include <stdint.h>
#include <stdbool.h>
#include "encoding.h"
#include "mss_hart_ints.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Useful macros
*/
#define WRITE_REG8(x, y) (*((volatile uint8_t *)(x)) = (y))
#define READ_REG8(x) (*((volatile uint8_t *)(x)))
#define WRITE_REG32(x, y) (*((volatile uint32_t *)(x)) = (y))
#define READ_REG32(x) (*((volatile uint32_t *)(x)))
#define WRITE_REG64(x, y) (*((volatile uint64_t *)(x)) = (y))
#define READ_REG64(x) (*((volatile uint64_t *)(x)))
/*
* return mcycle
*/
uint64_t readmcycle(void);
void sleep_ms(uint64_t msecs);
void sleep_cycles(uint64_t ncycles);
uint64_t get_stack_pointer(void);
uint64_t get_tp_reg(void);
uint64_t get_program_counter(void) __attribute__((aligned(16)));
#ifdef MPFS_PRINTF_DEBUG_SUPPORTED
void display_address_of_interest(uint64_t * address_of_interest, int nb_locations);
#endif
void exit_simulation(void);
void enable_interrupts(void);
uint64_t disable_interrupts(void);
void restore_interrupts(uint64_t saved_psr);
void __disable_irq(void);
void __disable_all_irqs(void);
void __enable_irq(void);
void __enable_local_irq(uint8_t local_interrupt);
void __disable_local_irq(uint8_t local_interrupt);
bool mpfs_sync_bool_compare_and_swap(volatile long *ptr, long oldval, long newval);
long mpfs_sync_val_compare_and_swap(volatile long *ptr, long oldval, long newval);
static inline void spinunlock(volatile long *lock)
{
*lock = 0;
}
static inline void spinlock(volatile long *lock)
{
while(!mpfs_sync_bool_compare_and_swap(lock, 0, 1))
{
/* add yield if OS */
}
*lock = 1;
}
#ifdef __cplusplus
}
#endif
#endif /* MSS_UTIL_H */

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
*/
#include <stdint.h>
#include <stdio.h>
#include <stdarg.h>
#include <stdbool.h>
#include <stdlib.h>
#include <string.h>
#include <stdint.h>
#include "mpfs_hal/mss_hal.h"
#include "mss_cfm.h"
/***************************************************************************//**
* See mss_cfm.h for description of this function.
*/
uint8_t MSS_CFM_control_start(void)
{
/* Writing a 1, to this causes measurement circuitry to start. */
CFM_REG->controlReg |= 1;
return (CFM_REG->controlReg & CFM_CONTROL_REG_START_MASK);
}
uint8_t MSS_CFM_control_stop(void)
{
/* Writing a 1, to this causes measurement circuitry to start. */
CFM_REG->controlReg |= (1 << CFM_CONTROL_REG_STOP_BITS_SHIFT);
return (CFM_REG->controlReg & CFM_CONTROL_REG_START_MASK);
}
cfm_error_id_t MSS_CLF_clk_configuration(
uint8_t clkSel,
uint8_t refsel0,
uint8_t refsel1,
uint8_t monSEL,
uint8_t monEN
)
{
/* Reset the register. */
CFM_REG->clkselReg = 0;
/* Some error checking on configuration values. */
if(clkSel > CFM_CLK_SEL_MASK)
return ERROR_INVALID_CLK_SELECTION_GROUP;
if(refsel0 > CFM_CLK_REFSEL0_MASK)
return ERROR_INVALID_REF_SEL0;
if(refsel1 > CFM_CLK_REFSEL1_MASK)
return ERROR_INVALID_REF_SEL1;
if(monSEL > CFM_CLK_MONSEL_MASK)
return ERROR_INVALID_CHANNEL_DRIVE_CLK_MONITOR;
CFM_REG->clkselReg |= (clkSel & CFM_CLK_SEL_MASK);
if(refsel0)
CFM_REG->clkselReg |= (uint32_t)(refsel0 << CFM_CLK_REFSEL0SHIFT);
if(refsel1)
CFM_REG->clkselReg |= (uint32_t)(refsel1 << CFM_CLK_REFSEL1SHIFT);
if(monSEL)
CFM_REG->clkselReg |= (uint32_t)(monSEL << CFM_CLK_MONSEL_SHIFT);
if(monEN)
CFM_REG->clkselReg |= (uint32_t)(monEN << CFM_CLK_MONEN_SHIFT);
return CFM_OK;
}
void MSS_CFM_runtime_register(uint32_t referenceCount)
{
/*Sets how many runtime reference clock cycles the frequency and time
* measurement shold be made for.. */
CFM_REG->runtimeReg = (referenceCount & CFM_RUNTIME_REG_MASK);
return;
}
void MSS_CFM_channel_mode(cfmChannelMode chMode)
{
uint32_t chConfiguration = 0;
chConfiguration |= (chMode.channel0 & CFM_CHANNEL_MODE_MASK) << CFM_CH0_SHIFT_MASK;
chConfiguration |= (chMode.channel1 & CFM_CHANNEL_MODE_MASK) << CFM_CH1_SHIFT_MASK;
chConfiguration |= (chMode.channel2 & CFM_CHANNEL_MODE_MASK) << CFM_CH2_SHIFT_MASK;
chConfiguration |= (chMode.channel3 & CFM_CHANNEL_MODE_MASK) << CFM_CH3_SHIFT_MASK;
chConfiguration |= (chMode.channel4 & CFM_CHANNEL_MODE_MASK) << CFM_CH4_SHIFT_MASK;
chConfiguration |= (chMode.channel5 & CFM_CHANNEL_MODE_MASK) << CFM_CH5_SHIFT_MASK;
chConfiguration |= (chMode.channel6 & CFM_CHANNEL_MODE_MASK) << CFM_CH6_SHIFT_MASK;
chConfiguration |= (chMode.channel7 & CFM_CHANNEL_MODE_MASK) << CFM_CH7_SHIFT_MASK;
CFM_REG->modelReg = chConfiguration;
return;
}
cfm_error_id_t MSS_CFM_get_count(cfm_count_id_t ch, uint32_t *count)
{
if(count == NULL)
return ERROR_NULL_VALUE;
*count = 0;
if(CFM_REG->controlReg & CFM_CONTROL_REG_BUSY_MASK)
return ERROR_INVALID_CFM_BUSY;
switch(ch)
{
case CFM_COUNT_0:
*count = CFM_REG->count0;
break;
case CFM_COUNT_1:
*count = CFM_REG->count1;
break;
case CFM_COUNT_2:
*count = CFM_REG->count2;
break;
case CFM_COUNT_3:
*count = CFM_REG->count3;
break;
case CFM_COUNT_4:
*count = CFM_REG->count4;
break;
case CFM_COUNT_5:
*count = CFM_REG->count5;
break;
case CFM_COUNT_6:
*count = CFM_REG->count6;
break;
case CFM_COUNT_7:
*count = CFM_REG->count7;
break;
default:
return 11;
}
return CFM_OK;
}

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/*******************************************************************************
* Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
*
*/
/*=========================================================================*//**
@mainpage PolarFire MSS Frequency Meter Bare Metal Driver.
The MSS Clock Frequency Meter (CFM) block is used to support test of the
DLL's within the MSS. All functional clocks are connected to the CFM block.
The frequency meter can be configured to measure time or frequency, time
allowing items such as PLL lock times to be tested and frequency to test
oscillator frequencies.
Upto 8 circuit counters are implemented.
@section intro_sec Introduction
*//*=========================================================================*/
#ifndef __COREPLEX_PLATFORM_CFM_H_
#define __COREPLEX_PLATFORM_CFM_H_
#ifdef __cplusplus
extern "C" {
#endif
/* CFM Register base address. */
#define CFM_REG_BASE 0x20006000
/***************************************************************************//**
The __cfm_count_id_t enumeration is used to identify the channel used.
*/
typedef enum __cfm_count_id
{
CFM_COUNT_0 = 0,
CFM_COUNT_1,
CFM_COUNT_2,
CFM_COUNT_3,
CFM_COUNT_4,
CFM_COUNT_5,
CFM_COUNT_6,
CFM_COUNT_7,
cfm_lastCH,
} cfm_count_id_t;
/***************************************************************************//**
The cfm_channel_mode enumeration is used to specify the channel mode.
*/
typedef enum __cfm_channel_mode
{
CFM_CH_DISABLED = 0,
CFM_CH_FREQUENCY_MODE,
CFM_CH_RESERVER,
CFM_CH_TIMER_MODE,
CFM_CH_lastmd
} cfm_channel_mode;
typedef enum __cfm_error_id_t
{
CFM_OK = 0,
ERROR_INVALID_CLK_SELECTION_GROUP,
ERROR_INVALID_REF_SEL0,
ERROR_INVALID_REF_SEL1,
ERROR_INVALID_CHANNEL_DRIVE_CLK_MONITOR,
ERROR_INVALID_CFM_BUSY,
ERROR_NULL_VALUE,
ERROR_CFMLAST_ID
} cfm_error_id_t;
typedef struct _cfmRegs
{
__IO uint32_t controlReg; /* CFM Control Register */
__IO uint32_t clkselReg; /* Clock Selection Register */
__IO uint32_t runtimeReg; /* Reference Count Value */
__IO uint32_t modelReg; /* Sets the measurement mode */
__I uint32_t count0; /* Count x value */
__I uint32_t count1;
__I uint32_t count2;
__I uint32_t count3;
__I uint32_t count4;
__I uint32_t count5;
__I uint32_t count6;
__I uint32_t count7;
__I uint32_t reserved[4]; /*Reserved registers, padding structure */
}CFM;
#define CFM_REG ((CFM *)CFM_REG_BASE)
typedef struct _cfmChannelMode
{
uint8_t channel0; /* Channel x mode */
uint8_t channel1; /* Channel x mode */
uint8_t channel2; /* Channel x mode */
uint8_t channel3; /* Channel x mode */
uint8_t channel4; /* Channel x mode */
uint8_t channel5; /* Channel x mode */
uint8_t channel6; /* Channel x mode */
uint8_t channel7; /* Channel x mode */
}cfmChannelMode;
#define CFM_CONTROL_REG_BUSY_MASK 0x01U
#define CFM_CONTROL_REG_START_MASK 0x01U
#define CFM_CONTROL_REG_STOP_BITS_SHIFT 0x01U
#define CFM_CLK_SEL_MASK 0x07U
#define CFM_CLK_REFSEL0_MASK 0x01U
#define CFM_CLK_REFSEL0SHIFT 0x04U
#define CFM_CLK_REFSEL1_MASK 0x01U
#define CFM_CLK_REFSEL1SHIFT 0x05U
#define CFM_CLK_MONSEL_MASK 0x07U
#define CFM_CLK_MONSEL_SHIFT 0x08U
#define CFM_CLK_MONEN_MASK 0x01
#define CFM_CLK_MONEN_SHIFT 11U
#define CFM_RUNTIME_REG_MASK 0xFFFFFFU
#define CFM_CHANNEL_MODE_MASK 0x3U
#define CFM_CH0_SHIFT_MASK 0x00U
#define CFM_CH1_SHIFT_MASK 0x02U
#define CFM_CH2_SHIFT_MASK 0x04U
#define CFM_CH3_SHIFT_MASK 0x06U
#define CFM_CH4_SHIFT_MASK 0x08U
#define CFM_CH5_SHIFT_MASK 0x0AU
#define CFM_CH6_SHIFT_MASK 0x0CU
#define CFM_CH7_SHIFT_MASK 0x0EU
/*****************************************************************************
* CFM Function Prototypes
*******************************************************************************
*/
/*-------------------------------------------------------------------------*//**
The MSS_CFM_control_start() function causes the measurement circuitry
to start. This state of 'busy' will clear which measurement is complete.
@param None
@return
Busy state
Example:
The following call will start the CFM
@code
MSS_CFM_control_start( );
@endcode
*/
uint8_t MSS_CFM_control_start(void);
/*-------------------------------------------------------------------------*//**
The MSS_CFM_control_stop() function causes the measurement circuitry
to stop.
@param None
@return uint8_t
Returns the busy flag.
Example:
The following call will stop the CFM
@code
MSS_CFM_control_stop( );
@endcode
*/
uint8_t MSS_CFM_control_stop(void);
/*-------------------------------------------------------------------------*//**
The MSS_CLF_clk_configuration() function is used to configure the clock
selection register.
@param clkSel
Selects which group of clock inputs are selected by the channels, control
the input multiplexer.
@param refsel0
Selects the reference input, 0=clkref1 / 1=clkref2
@param refsel1
When in timer mode allows ATPG (corners) / clkref3 clock input to clock
the channel counters. This clock input is expected to be sourced from an
on-chip PLL to support at-speed testing. This allows the timer to clocked
off a much higher clock frequency that the reference counter that is limited
to 100Mhz.
@param monSEL
Selects which channel drives the clock monitor output 0-7.
@param monEN
Enables the clock monitor output.
@return
cfm_error_id_t
Example:
The following call will configure clk 0, using clkref1, channel zero drives
the clock monitor and enable the clock monitor output.
@code
MSS_GPIO_config( 0, 0, 0, 0, 1 );
@endcode
*/
cfm_error_id_t MSS_CLF_clk_configuration(
uint8_t clkSel,
uint8_t refsel0,
uint8_t refsel1,
uint8_t monSEL,
uint8_t monEN
);
/*-------------------------------------------------------------------------*//**
The MSS_CFM_runtime_register() function is used to set how many reference
clock cycles the frequency and time measurement should be made.
The register does NOT change during oepration
@param refcount
The reference count value.
*/
void MSS_CFM_runtime_register(
uint32_t referenceCount
);
/*-------------------------------------------------------------------------*//**
The MSS_CFM_channel_mode() function is used to set the measurement mode for
the specified channel.
2'b00: Disabled
2'b01: Frequency Mode
2'b11: Timer Mode
2'b10: Reserved
@param cfmChannelMode
Configuration structure for each channel
@return
None
*/
void MSS_CFM_channel_mode(cfmChannelMode chMode);
/*-------------------------------------------------------------------------*//**
The MSS_CFM_get_count() function is used to get the count value.
Block must not be busy.
@param ch
The channel ID to return the count for.
@param count
The count for the channel register.
@return
cfm_error_id_t
Example:
The following call will return the value in count register. channel 0
@code
MSS_CFM_get_count();
@endcode
*/
cfm_error_id_t MSS_CFM_get_count(cfm_count_id_t ch, uint32_t *count);
#ifdef __cplusplus
}
#endif
#endif /* __COREPLEX_PLATFORM_CFM_H_ */

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