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Prepare for V9.0.0 release.
+ Set flash wait states on MSP432 demos. + Remove use of obsolete IO library in PIC32 demos. + Remove obsolete item left on stack of first task to run in the Cortex-M0 ports. + Correct IA32 GCC vPortExitCritical() implementation when configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY.
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34 changed files with 2764 additions and 2463 deletions
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@ -186,8 +186,10 @@ void vPortStartFirstTask( void )
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" isb \n"
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" pop {r0-r5} \n" /* Pop the registers that are saved automatically. */
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" mov lr, r5 \n" /* lr is now in r5. */
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" pop {r3} \n" /* Return address is now in r3. */
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" pop {r2} \n" /* Pop and discard XPSR. */
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" cpsie i \n" /* The first task has its context and interrupts can be enabled. */
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" pop {pc} \n" /* Finally, pop the PC to jump to the user defined task code. */
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" bx r3 \n" /* Finally, jump to the user defined task code. */
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" \n"
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" .align 4 \n"
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"pxCurrentTCBConst2: .word pxCurrentTCB "
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@ -504,16 +504,16 @@ void vPortExitCritical( void )
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#else
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{
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portAPIC_TASK_PRIORITY = 0;
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/* If a yield was pended from within the critical section then
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perform the yield now. */
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if( ulPortYieldPending != pdFALSE )
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{
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ulPortYieldPending = pdFALSE;
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__asm volatile( portYIELD_INTERRUPT );
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}
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}
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#endif
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/* If a yield was pended from within the critical section then
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perform the yield now. */
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if( ulPortYieldPending != pdFALSE )
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{
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ulPortYieldPending = pdFALSE;
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__asm volatile( portYIELD_INTERRUPT );
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}
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}
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}
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}
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@ -152,8 +152,10 @@ vPortStartFirstTask
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isb
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pop {r0-r5} /* Pop the registers that are saved automatically. */
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mov lr, r5 /* lr is now in r5. */
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pop {r3} /* The return address is now in r3. */
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pop {r2} /* Pop and discard the XPSR. */
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cpsie i /* The first task has its context and interrupts can be enabled. */
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pop {pc} /* Finally, pop the PC to jump to the user defined task code. */
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bx r3 /* Jump to the user defined task code. */
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/*-----------------------------------------------------------*/
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@ -184,8 +184,10 @@ __asm void prvPortStartFirstTask( void )
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isb
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pop {r0-r5} /* Pop the registers that are saved automatically. */
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mov lr, r5 /* lr is now in r5. */
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pop {r3} /* The return address is now in r3. */
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pop {r2} /* Pop and discard the XPSR. */
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cpsie i /* The first task has its context and interrupts can be enabled. */
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pop {pc} /* Finally, pop the PC to jump to the user defined task code. */
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bx r3 /* Finally, jump to the user defined task code. */
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ALIGN
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}
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