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Add support for Vector context save support on RISC-V (#1260)

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port: riscv: Add vector context save support
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Jonathan Cubides 2025-03-27 10:52:22 +01:00 • committed by GitHub
parent b9aa064591
commit 0030d609a4
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3 changed files with 144 additions and 5 deletions
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9
portable/GCC/RISC-V/portASM.S
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@ -192,6 +192,7 @@ definitions. */
* x5
* portTASK_RETURN_ADDRESS
* [FPU registers (when enabled/available) go here]
* [VPU registers (when enabled/available) go here]
* [chip specific registers go here]
* mstatus
* pxCode
@ -233,6 +234,14 @@ chip_specific_stack_frame: /* First add any chip specific registers
or t0, t0, t1
#endif
#if( configENABLE_VPU == 1 )
/* Mark the VPU as clean in the mstatus value. */
li t1, ~MSTATUS_VS_MASK
and t0, t0, t1
li t1, MSTATUS_VS_CLEAN
or t0, t0, t1
#endif
addi a0, a0, -portWORD_SIZE
store_x t0, 0(a0) /* mstatus onto the stack. */