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Remove unused files from STM32L discovery board demo directory structure and build.

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This commit is contained in:
Richard Barry 2013-12-10 17:16:45 +00:00
parent 751103d848
commit 0028cc48c1
48 changed files with 330 additions and 21393 deletions
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60
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/RTOSDemo.ewp
View file

@ -991,15 +991,9 @@
<file>
<name>$PROJ_DIR$\ST_Code\Libraries\STM32L1xx_StdPeriph_Driver\src\misc.c</name>
</file>
<file>
<name>$PROJ_DIR$\ST_Code\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_adc.c</name>
</file>
<file>
<name>$PROJ_DIR$\ST_Code\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_exti.c</name>
</file>
<file>
<name>$PROJ_DIR$\ST_Code\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_flash.c</name>
</file>
<file>
<name>$PROJ_DIR$\ST_Code\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_gpio.c</name>
</file>
@ -1022,48 +1016,6 @@
<name>$PROJ_DIR$\ST_Code\Libraries\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_tim.c</name>
</file>
</group>
<group>
<name>TouchSensingDriver</name>
<excluded>
<configuration>Debug</configuration>
</excluded>
<file>
<name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl.c</name>
</file>
<file>
<name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_acq.c</name>
</file>
<file>
<name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_acq_stm32l1xx_sw.c</name>
</file>
<file>
<name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_dxs.c</name>
</file>
<file>
<name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_ecs.c</name>
</file>
<file>
<name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_filter.c</name>
</file>
<file>
<name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_globals.c</name>
</file>
<file>
<name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_linrot.c</name>
</file>
<file>
<name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_object.c</name>
</file>
<file>
<name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_time.c</name>
</file>
<file>
<name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_time_stm32l1xx.c</name>
</file>
<file>
<name>$PROJ_DIR$\ST_Code\Libraries\STMTouch_Driver\src\tsl_touchkey.c</name>
</file>
</group>
</group>
<group>
<name>Standard Demo Tasks</name>
@ -1101,18 +1053,9 @@
<name>$PROJ_DIR$\System\system_stm32l1xx.c</name>
</file>
</group>
<file>
<name>$PROJ_DIR$\discover_functions.c</name>
</file>
<file>
<name>$PROJ_DIR$\include\FreeRTOSConfig.h</name>
</file>
<file>
<name>$PROJ_DIR$\icc_measure.c</name>
</file>
<file>
<name>$PROJ_DIR$\icc_measure_Ram.c</name>
</file>
<file>
<name>$PROJ_DIR$\main.c</name>
</file>
@ -1128,9 +1071,6 @@
<file>
<name>$PROJ_DIR$\STM32L_low_power_tick_management.c</name>
</file>
<file>
<name>$PROJ_DIR$\tsl_user.c</name>
</file>
</project>

650
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_adc.h
View file

@ -1,650 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_adc.h
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_ADC_H
#define __STM32L1xx_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @addtogroup ADC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief ADC Init structure definition
*/
typedef struct
{
uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion.
This parameter can be a value of @ref ADC_Resolution */
FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in
Scan (multichannel) or Single (one channel) mode.
This parameter can be set to ENABLE or DISABLE */
FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
Continuous or Single mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the
trigger of a regular group. This parameter can be a value
of @ref ADC_external_trigger_edge_for_regular_channels_conversion */
uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
to digital conversion of regular channels. This parameter
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
This parameter can be a value of @ref ADC_data_align */
uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done
using the sequencer for regular channel group.
This parameter must range from 1 to 27. */
}ADC_InitTypeDef;
typedef struct
{
uint32_t ADC_Prescaler; /*!< Selects the ADC prescaler.
This parameter can be a value
of @ref ADC_Prescaler */
}ADC_CommonInitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup ADC_Exported_Constants
* @{
*/
#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1)
#define IS_ADC_DMA_PERIPH(PERIPH) ((PERIPH) == ADC1)
/** @defgroup ADC_Power_down_during_Idle_and_or_Delay_phase
* @{
*/
#define ADC_PowerDown_Delay ((uint32_t)0x00010000)
#define ADC_PowerDown_Idle ((uint32_t)0x00020000)
#define ADC_PowerDown_Idle_Delay ((uint32_t)0x00030000)
#define IS_ADC_POWER_DOWN(DWON) (((DWON) == ADC_PowerDown_Delay) || \
((DWON) == ADC_PowerDown_Idle) || \
((DWON) == ADC_PowerDown_Idle_Delay))
/**
* @}
*/
/** @defgroup ADC_Prescaler
* @{
*/
#define ADC_Prescaler_Div1 ((uint32_t)0x00000000)
#define ADC_Prescaler_Div2 ((uint32_t)0x00010000)
#define ADC_Prescaler_Div4 ((uint32_t)0x00020000)
#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div1) || \
((PRESCALER) == ADC_Prescaler_Div2) || \
((PRESCALER) == ADC_Prescaler_Div4))
/**
* @}
*/
/** @defgroup ADC_Resolution
* @{
*/
#define ADC_Resolution_12b ((uint32_t)0x00000000)
#define ADC_Resolution_10b ((uint32_t)0x01000000)
#define ADC_Resolution_8b ((uint32_t)0x02000000)
#define ADC_Resolution_6b ((uint32_t)0x03000000)
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
((RESOLUTION) == ADC_Resolution_10b) || \
((RESOLUTION) == ADC_Resolution_8b) || \
((RESOLUTION) == ADC_Resolution_6b))
/**
* @}
*/
/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
* @{
*/
#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)
#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)
#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
/**
* @}
*/
/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
* @{
*/
/* TIM2 */
#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x02000000)
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)
#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)
/* TIM3 */
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)
#define ADC_ExternalTrigConv_T3_CC3 ((uint32_t)0x08000000)
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x04000000)
/* TIM4 */
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x05000000)
#define ADC_ExternalTrigConv_T4_TRGO ((uint32_t)0x09000000)
/* TIM6 */
#define ADC_ExternalTrigConv_T6_TRGO ((uint32_t)0x0A000000)
/* TIM9 */
#define ADC_ExternalTrigConv_T9_CC2 ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T9_TRGO ((uint32_t)0x01000000)
/* EXTI */
#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T9_CC2) || \
((REGTRIG) == ADC_ExternalTrigConv_T9_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T3_CC3) || \
((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T6_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
/**
* @}
*/
/** @defgroup ADC_data_align
* @{
*/
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
((ALIGN) == ADC_DataAlign_Left))
/**
* @}
*/
/** @defgroup ADC_channels
* @{
*/
/* ADC Bank A Channels -------------------------------------------------------*/
#define ADC_Channel_0 ((uint8_t)0x00)
#define ADC_Channel_1 ((uint8_t)0x01)
#define ADC_Channel_2 ((uint8_t)0x02)
#define ADC_Channel_3 ((uint8_t)0x03)
#define ADC_Channel_6 ((uint8_t)0x06)
#define ADC_Channel_7 ((uint8_t)0x07)
#define ADC_Channel_8 ((uint8_t)0x08)
#define ADC_Channel_9 ((uint8_t)0x09)
#define ADC_Channel_10 ((uint8_t)0x0A)
#define ADC_Channel_11 ((uint8_t)0x0B)
#define ADC_Channel_12 ((uint8_t)0x0C)
/* ADC Bank B Channels -------------------------------------------------------*/
#define ADC_Channel_0b ADC_Channel_0
#define ADC_Channel_1b ADC_Channel_1
#define ADC_Channel_2b ADC_Channel_2
#define ADC_Channel_3b ADC_Channel_3
#define ADC_Channel_6b ADC_Channel_6
#define ADC_Channel_7b ADC_Channel_7
#define ADC_Channel_8b ADC_Channel_8
#define ADC_Channel_9b ADC_Channel_9
#define ADC_Channel_10b ADC_Channel_10
#define ADC_Channel_11b ADC_Channel_11
#define ADC_Channel_12b ADC_Channel_12
/* ADC Common Channels (ADC Bank A and B) ------------------------------------*/
#define ADC_Channel_4 ((uint8_t)0x04)
#define ADC_Channel_5 ((uint8_t)0x05)
#define ADC_Channel_13 ((uint8_t)0x0D)
#define ADC_Channel_14 ((uint8_t)0x0E)
#define ADC_Channel_15 ((uint8_t)0x0F)
#define ADC_Channel_16 ((uint8_t)0x10)
#define ADC_Channel_17 ((uint8_t)0x11)
#define ADC_Channel_18 ((uint8_t)0x12)
#define ADC_Channel_19 ((uint8_t)0x13)
#define ADC_Channel_20 ((uint8_t)0x14)
#define ADC_Channel_21 ((uint8_t)0x15)
#define ADC_Channel_22 ((uint8_t)0x16)
#define ADC_Channel_23 ((uint8_t)0x17)
#define ADC_Channel_24 ((uint8_t)0x18)
#define ADC_Channel_25 ((uint8_t)0x19)
#define ADC_Channel_27 ((uint8_t)0x1B)
#define ADC_Channel_28 ((uint8_t)0x1C)
#define ADC_Channel_29 ((uint8_t)0x1D)
#define ADC_Channel_30 ((uint8_t)0x1E)
#define ADC_Channel_31 ((uint8_t)0x1F)
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17) || \
((CHANNEL) == ADC_Channel_18) || ((CHANNEL) == ADC_Channel_19) || \
((CHANNEL) == ADC_Channel_20) || ((CHANNEL) == ADC_Channel_21) || \
((CHANNEL) == ADC_Channel_22) || ((CHANNEL) == ADC_Channel_23) || \
((CHANNEL) == ADC_Channel_24) || ((CHANNEL) == ADC_Channel_25) || \
((CHANNEL) == ADC_Channel_27) || ((CHANNEL) == ADC_Channel_28) || \
((CHANNEL) == ADC_Channel_29) || ((CHANNEL) == ADC_Channel_30) || \
((CHANNEL) == ADC_Channel_31))
/**
* @}
*/
/** @defgroup ADC_sampling_times
* @{
*/
#define ADC_SampleTime_4Cycles ((uint8_t)0x00)
#define ADC_SampleTime_9Cycles ((uint8_t)0x01)
#define ADC_SampleTime_16Cycles ((uint8_t)0x02)
#define ADC_SampleTime_24Cycles ((uint8_t)0x03)
#define ADC_SampleTime_48Cycles ((uint8_t)0x04)
#define ADC_SampleTime_96Cycles ((uint8_t)0x05)
#define ADC_SampleTime_192Cycles ((uint8_t)0x06)
#define ADC_SampleTime_384Cycles ((uint8_t)0x07)
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_4Cycles) || \
((TIME) == ADC_SampleTime_9Cycles) || \
((TIME) == ADC_SampleTime_16Cycles) || \
((TIME) == ADC_SampleTime_24Cycles) || \
((TIME) == ADC_SampleTime_48Cycles) || \
((TIME) == ADC_SampleTime_96Cycles) || \
((TIME) == ADC_SampleTime_192Cycles) || \
((TIME) == ADC_SampleTime_384Cycles))
/**
* @}
*/
/** @defgroup ADC_Delay_length
* @{
*/
#define ADC_DelayLength_None ((uint8_t)0x00)
#define ADC_DelayLength_Freeze ((uint8_t)0x10)
#define ADC_DelayLength_7Cycles ((uint8_t)0x20)
#define ADC_DelayLength_15Cycles ((uint8_t)0x30)
#define ADC_DelayLength_31Cycles ((uint8_t)0x40)
#define ADC_DelayLength_63Cycles ((uint8_t)0x50)
#define ADC_DelayLength_127Cycles ((uint8_t)0x60)
#define ADC_DelayLength_255Cycles ((uint8_t)0x70)
#define IS_ADC_DELAY_LENGTH(LENGTH) (((LENGTH) == ADC_DelayLength_None) || \
((LENGTH) == ADC_DelayLength_Freeze) || \
((LENGTH) == ADC_DelayLength_7Cycles) || \
((LENGTH) == ADC_DelayLength_15Cycles) || \
((LENGTH) == ADC_DelayLength_31Cycles) || \
((LENGTH) == ADC_DelayLength_63Cycles) || \
((LENGTH) == ADC_DelayLength_127Cycles) || \
((LENGTH) == ADC_DelayLength_255Cycles))
/**
* @}
*/
/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion
* @{
*/
#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)
#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)
#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)
#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
/**
* @}
*/
/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
* @{
*/
/* TIM2 */
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00020000)
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00030000)
/* TIM3 */
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00040000)
/* TIM4 */
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00050000)
#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)
#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)
#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)
/* TIM7 */
#define ADC_ExternalTrigInjecConv_T7_TRGO ((uint32_t)0x000A0000)
/* TIM9 */
#define ADC_ExternalTrigInjecConv_T9_CC1 ((uint32_t)0x00000000)
#define ADC_ExternalTrigInjecConv_T9_TRGO ((uint32_t)0x00010000)
/* TIM10 */
#define ADC_ExternalTrigInjecConv_T10_CC1 ((uint32_t)0x00090000)
/* EXTI */
#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T9_CC1) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T9_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T10_CC1) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_T7_TRGO) || \
((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
/**
* @}
*/
/** @defgroup ADC_injected_channel_selection
* @{
*/
#define ADC_InjectedChannel_1 ((uint8_t)0x18)
#define ADC_InjectedChannel_2 ((uint8_t)0x1C)
#define ADC_InjectedChannel_3 ((uint8_t)0x20)
#define ADC_InjectedChannel_4 ((uint8_t)0x24)
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
((CHANNEL) == ADC_InjectedChannel_2) || \
((CHANNEL) == ADC_InjectedChannel_3) || \
((CHANNEL) == ADC_InjectedChannel_4))
/**
* @}
*/
/** @defgroup ADC_analog_watchdog_selection
* @{
*/
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_None))
/**
* @}
*/
/** @defgroup ADC_interrupts_definition
* @{
*/
#define ADC_IT_AWD ((uint16_t)0x0106)
#define ADC_IT_EOC ((uint16_t)0x0205)
#define ADC_IT_JEOC ((uint16_t)0x0407)
#define ADC_IT_OVR ((uint16_t)0x201A)
#define IS_ADC_IT(IT) (((IT) == ADC_IT_AWD) || ((IT) == ADC_IT_EOC) || \
((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
/**
* @}
*/
/** @defgroup ADC_flags_definition
* @{
*/
#define ADC_FLAG_AWD ((uint16_t)0x0001)
#define ADC_FLAG_EOC ((uint16_t)0x0002)
#define ADC_FLAG_JEOC ((uint16_t)0x0004)
#define ADC_FLAG_JSTRT ((uint16_t)0x0008)
#define ADC_FLAG_STRT ((uint16_t)0x0010)
#define ADC_FLAG_OVR ((uint16_t)0x0020)
#define ADC_FLAG_ADONS ((uint16_t)0x0040)
#define ADC_FLAG_RCNR ((uint16_t)0x0100)
#define ADC_FLAG_JCNR ((uint16_t)0x0200)
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFC0) == 0x00) && ((FLAG) != 0x00))
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
((FLAG) == ADC_FLAG_STRT) || ((FLAG)== ADC_FLAG_OVR) || \
((FLAG) == ADC_FLAG_ADONS) || ((FLAG)== ADC_FLAG_RCNR) || \
((FLAG) == ADC_FLAG_JCNR))
/**
* @}
*/
/** @defgroup ADC_thresholds
* @{
*/
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
/**
* @}
*/
/** @defgroup ADC_injected_offset
* @{
*/
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
/**
* @}
*/
/** @defgroup ADC_injected_length
* @{
*/
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
/**
* @}
*/
/** @defgroup ADC_injected_rank
* @{
*/
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
/**
* @}
*/
/** @defgroup ADC_regular_length
* @{
*/
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 28))
/**
* @}
*/
/** @defgroup ADC_regular_rank
* @{
*/
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1) && ((RANK) <= 28))
/**
* @}
*/
/** @defgroup ADC_regular_discontinuous_mode_number
* @{
*/
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
/**
* @}
*/
/** @defgroup ADC_Bank_Selection
* @{
*/
#define ADC_Bank_A ((uint8_t)0x00)
#define ADC_Bank_B ((uint8_t)0x01)
#define IS_ADC_BANK(BANK) (((BANK) == ADC_Bank_A) || ((BANK) == ADC_Bank_B))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the ADC configuration to the default reset state *****/
void ADC_DeInit(ADC_TypeDef* ADCx);
/* Initialization and Configuration functions *********************************/
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_BankSelection(ADC_TypeDef* ADCx, uint8_t ADC_Bank);
/* Power saving functions *****************************************************/
void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState);
void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength);
/* Analog Watchdog configuration functions ************************************/
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
/* Temperature Sensor & Vrefint (Voltage Reference internal) management function */
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
/* Regular Channels Configuration functions ***********************************/
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
/* Regular Channels DMA Configuration functions *******************************/
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
/* Injected channels Configuration functions **********************************/
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
/* Interrupts and flags management functions **********************************/
void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32L1xx_ADC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

236
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_aes.h
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@ -1,236 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_aes.h
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file contains all the functions prototypes for the AES firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_AES_H
#define __STM32L1xx_AES_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @addtogroup AES
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief AES Init structure definition
*/
typedef struct
{
uint32_t AES_Operation; /*!< Specifies the AES mode of operation.
This parameter can be a value of @ref AES_possible_Operation_modes */
uint32_t AES_Chaining; /*!< Specifies the AES Chaining modes: ECB, CBC or CTR.
This parameter can be a value of @ref AES_possible_chaining_modes */
uint32_t AES_DataType; /*!< Specifies the AES data swapping: 32-bit, 16-bit, 8-bit or 1-bit.
This parameter can be a value of @ref AES_Data_Types */
}AES_InitTypeDef;
/**
* @brief AES Key(s) structure definition
*/
typedef struct
{
uint32_t AES_Key0; /*!< Key[31:0] */
uint32_t AES_Key1; /*!< Key[63:32] */
uint32_t AES_Key2; /*!< Key[95:64] */
uint32_t AES_Key3; /*!< Key[127:96] */
}AES_KeyInitTypeDef;
/**
* @brief AES Initialization Vectors (IV) structure definition
*/
typedef struct
{
uint32_t AES_IV0; /*!< Init Vector IV[31:0] */
uint32_t AES_IV1; /*!< Init Vector IV[63:32] */
uint32_t AES_IV2; /*!< Init Vector IV[95:64] */
uint32_t AES_IV3; /*!< Init Vector IV[127:96] */
}AES_IVInitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup AES_Exported_Constants
* @{
*/
/** @defgroup AES_possible_Operation_modes
* @{
*/
#define AES_Operation_Encryp ((uint32_t)0x00000000) /*!< AES in Encryption mode */
#define AES_Operation_KeyDeriv AES_CR_MODE_0 /*!< AES in Key Derivation mode */
#define AES_Operation_Decryp AES_CR_MODE_1 /*!< AES in Decryption mode */
#define AES_Operation_KeyDerivAndDecryp AES_CR_MODE /*!< AES in Key Derivation and Decryption mode */
#define IS_AES_MODE(OPERATION) (((OPERATION) == AES_Operation_Encryp) || \
((OPERATION) == AES_Operation_KeyDeriv) || \
((OPERATION) == AES_Operation_Decryp) || \
((OPERATION) == AES_Operation_KeyDerivAndDecryp))
/**
* @}
*/
/** @defgroup AES_possible_chaining_modes
* @{
*/
#define AES_Chaining_ECB ((uint32_t)0x00000000) /*!< AES in ECB chaining mode */
#define AES_Chaining_CBC AES_CR_CHMOD_0 /*!< AES in CBC chaining mode */
#define AES_Chaining_CTR AES_CR_CHMOD_1 /*!< AES in CTR chaining mode */
#define IS_AES_CHAINING(CHAINING) (((CHAINING) == AES_Chaining_ECB) || \
((CHAINING) == AES_Chaining_CBC) || \
((CHAINING) == AES_Chaining_CTR))
/**
* @}
*/
/** @defgroup AES_Data_Types
* @{
*/
#define AES_DataType_32b ((uint32_t)0x00000000) /*!< 32-bit data. No swapping */
#define AES_DataType_16b AES_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
#define AES_DataType_8b AES_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
#define AES_DataType_1b AES_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
#define IS_AES_DATATYPE(DATATYPE) (((DATATYPE) == AES_DataType_32b) || \
((DATATYPE) == AES_DataType_16b)|| \
((DATATYPE) == AES_DataType_8b) || \
((DATATYPE) == AES_DataType_1b))
/**
* @}
*/
/** @defgroup AES_Flags
* @{
*/
#define AES_FLAG_CCF AES_SR_CCF /*!< Computation Complete Flag */
#define AES_FLAG_RDERR AES_SR_RDERR /*!< Read Error Flag */
#define AES_FLAG_WRERR AES_SR_WRERR /*!< Write Error Flag */
#define IS_AES_FLAG(FLAG) (((FLAG) == AES_FLAG_CCF) || \
((FLAG) == AES_FLAG_RDERR) || \
((FLAG) == AES_FLAG_WRERR))
/**
* @}
*/
/** @defgroup AES_Interrupts
* @{
*/
#define AES_IT_CC AES_CR_CCIE /*!< Computation Complete interrupt */
#define AES_IT_ERR AES_CR_ERRIE /*!< Error interrupt */
#define IS_AES_IT(IT) ((((IT) & (uint32_t)0xFFFFF9FF) == 0x00) && ((IT) != 0x00))
#define IS_AES_GET_IT(IT) (((IT) == AES_IT_CC) || ((IT) == AES_IT_ERR))
/**
* @}
*/
/** @defgroup AES_DMA_Transfer_modes
* @{
*/
#define AES_DMATransfer_In AES_CR_DMAINEN /*!< DMA requests enabled for input transfer phase */
#define AES_DMATransfer_Out AES_CR_DMAOUTEN /*!< DMA requests enabled for input transfer phase */
#define AES_DMATransfer_InOut (AES_CR_DMAINEN | AES_CR_DMAOUTEN) /*!< DMA requests enabled for both input and output phases */
#define IS_AES_DMA_TRANSFER(TRANSFER) (((TRANSFER) == AES_DMATransfer_In) || \
((TRANSFER) == AES_DMATransfer_Out) || \
((TRANSFER) == AES_DMATransfer_InOut))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Initialization and configuration functions *********************************/
void AES_DeInit(void);
void AES_Init(AES_InitTypeDef* AES_InitStruct);
void AES_KeyInit(AES_KeyInitTypeDef* AES_KeyInitStruct);
void AES_IVInit(AES_IVInitTypeDef* AES_IVInitStruct);
void AES_Cmd(FunctionalState NewState);
/* Structures initialization functions ****************************************/
void AES_StructInit(AES_InitTypeDef* AES_InitStruct);
void AES_KeyStructInit(AES_KeyInitTypeDef* AES_KeyInitStruct);
void AES_IVStructInit(AES_IVInitTypeDef* AES_IVInitStruct);
/* AES Read and Write functions **********************************************/
void AES_WriteSubData(uint32_t Data);
uint32_t AES_ReadSubData(void);
void AES_ReadKey(AES_KeyInitTypeDef* AES_KeyInitStruct);
void AES_ReadIV(AES_IVInitTypeDef* AES_IVInitStruct);
/* DMA transfers management function ******************************************/
void AES_DMAConfig(uint32_t AES_DMATransfer, FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void AES_ITConfig(uint32_t AES_IT, FunctionalState NewState);
FlagStatus AES_GetFlagStatus(uint32_t AES_FLAG);
void AES_ClearFlag(uint32_t AES_FLAG);
ITStatus AES_GetITStatus(uint32_t AES_IT);
void AES_ClearITPendingBit(uint32_t AES_IT);
/* High Level AES functions **************************************************/
ErrorStatus AES_ECB_Encrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output);
ErrorStatus AES_ECB_Decrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output);
ErrorStatus AES_CBC_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
ErrorStatus AES_CBC_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
ErrorStatus AES_CTR_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
ErrorStatus AES_CTR_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
#ifdef __cplusplus
}
#endif
#endif /*__STM32L1xx_AES_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

187
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_comp.h
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@ -1,187 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_comp.h
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file contains all the functions prototypes for the COMP firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_COMP_H
#define __STM32L1xx_COMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @addtogroup COMP
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief COMP Init structure definition
*/
typedef struct
{
uint32_t COMP_Speed; /*!< Defines the speed of comparator 2.
This parameter can be a value of @ref COMP_Speed */
uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator 2.
This parameter can be a value of @ref COMP_InvertingInput */
uint32_t COMP_OutputSelect; /*!< Selects the output redirection of the comparator 2.
This parameter can be a value of @ref COMP_OutputSelect */
}COMP_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup COMP_Exported_Constants
* @{
*/
#define COMP_OutputLevel_High ((uint32_t)0x00000001)
#define COMP_OutputLevel_Low ((uint32_t)0x00000000)
/** @defgroup COMP_Selection
* @{
*/
#define COMP_Selection_COMP1 ((uint32_t)0x00000001)
#define COMP_Selection_COMP2 ((uint32_t)0x00000002)
#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
((PERIPH) == COMP_Selection_COMP2))
/**
* @}
*/
/** @defgroup COMP_InvertingInput
* @{
*/
#define COMP_InvertingInput_None ((uint32_t)0x00000000) /* COMP2 is disabled when this parameter is selected */
#define COMP_InvertingInput_IO ((uint32_t)0x00040000)
#define COMP_InvertingInput_VREFINT ((uint32_t)0x00080000)
#define COMP_InvertingInput_3_4VREFINT ((uint32_t)0x000C0000)
#define COMP_InvertingInput_1_2VREFINT ((uint32_t)0x00100000)
#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00140000)
#define COMP_InvertingInput_DAC1 ((uint32_t)0x00180000)
#define COMP_InvertingInput_DAC2 ((uint32_t)0x001C0000)
#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_None) || \
((INPUT) == COMP_InvertingInput_IO) || \
((INPUT) == COMP_InvertingInput_VREFINT) || \
((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
((INPUT) == COMP_InvertingInput_DAC1) || \
((INPUT) == COMP_InvertingInput_DAC2))
/**
* @}
*/
/** @defgroup COMP_OutputSelect
* @{
*/
#define COMP_OutputSelect_TIM2IC4 ((uint32_t)0x00000000)
#define COMP_OutputSelect_TIM2OCREFCLR ((uint32_t)0x00200000)
#define COMP_OutputSelect_TIM3IC4 ((uint32_t)0x00400000)
#define COMP_OutputSelect_TIM3OCREFCLR ((uint32_t)0x00600000)
#define COMP_OutputSelect_TIM4IC4 ((uint32_t)0x00800000)
#define COMP_OutputSelect_TIM4OCREFCLR ((uint32_t)0x00A00000)
#define COMP_OutputSelect_TIM10IC1 ((uint32_t)0x00C00000)
#define COMP_OutputSelect_None ((uint32_t)0x00E00000)
#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OutputSelect_TIM2IC4) || \
((OUTPUT) == COMP_OutputSelect_TIM2OCREFCLR) || \
((OUTPUT) == COMP_OutputSelect_TIM3IC4) || \
((OUTPUT) == COMP_OutputSelect_TIM3OCREFCLR) || \
((OUTPUT) == COMP_OutputSelect_TIM4IC4) || \
((OUTPUT) == COMP_OutputSelect_TIM4OCREFCLR) || \
((OUTPUT) == COMP_OutputSelect_TIM10IC1) || \
((OUTPUT) == COMP_OutputSelect_None))
/**
* @}
*/
/** @defgroup COMP_Speed
* @{
*/
#define COMP_Speed_Slow ((uint32_t)0x00000000)
#define COMP_Speed_Fast ((uint32_t)0x00001000)
#define IS_COMP_SPEED(SPEED) (((SPEED) == COMP_Speed_Slow) || \
((SPEED) == COMP_Speed_Fast))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the COMP configuration to the default reset state ****/
void COMP_DeInit(void);
/* Initialization and Configuration functions *********************************/
void COMP_Init(COMP_InitTypeDef* COMP_InitStruct);
void COMP_Cmd(FunctionalState NewState);
uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection);
void COMP_SW1SwitchConfig(FunctionalState NewState);
/* Window mode control function ***********************************************/
void COMP_WindowCmd(FunctionalState NewState);
/* Internal Reference Voltage (VREFINT) output function ***********************/
void COMP_VrefintOutputCmd(FunctionalState NewState);
#ifdef __cplusplus
}
#endif
#endif /*__STM32L1xx_COMP_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

83
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_crc.h
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@ -1,83 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_crc.h
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file contains all the functions prototypes for the CRC firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_CRC_H
#define __STM32L1xx_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @addtogroup CRC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRC_Exported_Constants
* @{
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void CRC_ResetDR(void);
uint32_t CRC_CalcCRC(uint32_t Data);
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
uint32_t CRC_GetCRC(void);
void CRC_SetIDRegister(uint8_t IDValue);
uint8_t CRC_GetIDRegister(void);
#ifdef __cplusplus
}
#endif
#endif /* __STM32L1xx_CRC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

305
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_dac.h
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@ -1,305 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_dac.h
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file contains all the functions prototypes for the DAC firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_DAC_H
#define __STM32L1xx_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @addtogroup DAC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief DAC Init structure definition
*/
typedef struct
{
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection */
uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
are generated, or whether no wave is generated.
This parameter can be a value of @ref DAC_wave_generation */
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
the maximum amplitude triangle generation for the DAC channel.
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
}DAC_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup DAC_Exported_Constants
* @{
*/
/** @defgroup DAC_trigger_selection
* @{
*/
#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T9_TRGO ((uint32_t)0x0000001C) /*!< TIM9 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
((TRIGGER) == DAC_Trigger_T7_TRGO) || \
((TRIGGER) == DAC_Trigger_T9_TRGO) || \
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
((TRIGGER) == DAC_Trigger_Software))
/**
* @}
*/
/** @defgroup DAC_wave_generation
* @{
*/
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
((WAVE) == DAC_WaveGeneration_Noise) || \
((WAVE) == DAC_WaveGeneration_Triangle))
/**
* @}
*/
/** @defgroup DAC_lfsrunmask_triangleamplitude
* @{
*/
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
((VALUE) == DAC_TriangleAmplitude_1) || \
((VALUE) == DAC_TriangleAmplitude_3) || \
((VALUE) == DAC_TriangleAmplitude_7) || \
((VALUE) == DAC_TriangleAmplitude_15) || \
((VALUE) == DAC_TriangleAmplitude_31) || \
((VALUE) == DAC_TriangleAmplitude_63) || \
((VALUE) == DAC_TriangleAmplitude_127) || \
((VALUE) == DAC_TriangleAmplitude_255) || \
((VALUE) == DAC_TriangleAmplitude_511) || \
((VALUE) == DAC_TriangleAmplitude_1023) || \
((VALUE) == DAC_TriangleAmplitude_2047) || \
((VALUE) == DAC_TriangleAmplitude_4095))
/**
* @}
*/
/** @defgroup DAC_output_buffer
* @{
*/
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
((STATE) == DAC_OutputBuffer_Disable))
/**
* @}
*/
/** @defgroup DAC_Channel_selection
* @{
*/
#define DAC_Channel_1 ((uint32_t)0x00000000)
#define DAC_Channel_2 ((uint32_t)0x00000010)
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
((CHANNEL) == DAC_Channel_2))
/**
* @}
*/
/** @defgroup DAC_data_alignment
* @{
*/
#define DAC_Align_12b_R ((uint32_t)0x00000000)
#define DAC_Align_12b_L ((uint32_t)0x00000004)
#define DAC_Align_8b_R ((uint32_t)0x00000008)
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
((ALIGN) == DAC_Align_12b_L) || \
((ALIGN) == DAC_Align_8b_R))
/**
* @}
*/
/** @defgroup DAC_wave_generation
* @{
*/
#define DAC_Wave_Noise ((uint32_t)0x00000040)
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
((WAVE) == DAC_Wave_Triangle))
/**
* @}
*/
/** @defgroup DAC_data
* @{
*/
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
/**
* @}
*/
/** @defgroup DAC_interrupts_definition
* @{
*/
#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
/**
* @}
*/
/** @defgroup DAC_flags_definition
* @{
*/
#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the DAC configuration to the default reset state *****/
void DAC_DeInit(void);
/* DAC channels configuration: trigger, output buffer, data format functions */
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
/* DMA management functions ***************************************************/
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32L1xx_DAC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

105
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_dbgmcu.h
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@ -1,105 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_dbgmcu.h
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file contains all the functions prototypes for the DBGMCU
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_DBGMCU_H
#define __STM32L1xx_DBGMCU_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @addtogroup DBGMCU
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DBGMCU_Exported_Constants
* @{
*/
#define DBGMCU_SLEEP ((uint32_t)0x00000001)
#define DBGMCU_STOP ((uint32_t)0x00000002)
#define DBGMCU_STANDBY ((uint32_t)0x00000004)
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)
#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)
#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)
#define DBGMCU_TIM5_STOP ((uint32_t)0x00000008)
#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)
#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)
#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)
#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFF9FE3C0) == 0x00) && ((PERIPH) != 0x00))
#define DBGMCU_TIM9_STOP ((uint32_t)0x00000004)
#define DBGMCU_TIM10_STOP ((uint32_t)0x00000008)
#define DBGMCU_TIM11_STOP ((uint32_t)0x00000010)
#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE3) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
uint32_t DBGMCU_GetREVID(void);
uint32_t DBGMCU_GetDEVID(void);
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
#ifdef __cplusplus
}
#endif
#endif /* __STM32L1xx_DBGMCU_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

435
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_dma.h
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@ -1,435 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_dma.h
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file contains all the functions prototypes for the DMA firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_DMA_H
#define __STM32L1xx_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief DMA Init structure definition
*/
typedef struct
{
uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
This parameter can be a value of @ref DMA_data_transfer_direction */
uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
The data unit is equal to the configuration set in DMA_PeripheralDataSize
or DMA_MemoryDataSize members depending in the transfer direction. */
uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
This parameter can be a value of @ref DMA_memory_incremented_mode */
uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_peripheral_data_size */
uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
This parameter can be a value of @ref DMA_memory_data_size */
uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_circular_normal_mode
@note: The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Channel */
uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_priority_level */
uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
This parameter can be a value of @ref DMA_memory_to_memory */
}DMA_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA_Exported_Constants
* @{
*/
#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
((PERIPH) == DMA1_Channel2) || \
((PERIPH) == DMA1_Channel3) || \
((PERIPH) == DMA1_Channel4) || \
((PERIPH) == DMA1_Channel5) || \
((PERIPH) == DMA1_Channel6) || \
((PERIPH) == DMA1_Channel7) || \
((PERIPH) == DMA2_Channel1) || \
((PERIPH) == DMA2_Channel2) || \
((PERIPH) == DMA2_Channel3) || \
((PERIPH) == DMA2_Channel4) || \
((PERIPH) == DMA2_Channel5))
/** @defgroup DMA_data_transfer_direction
* @{
*/
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
((DIR) == DMA_DIR_PeripheralSRC))
/**
* @}
*/
/** @defgroup DMA_peripheral_incremented_mode
* @{
*/
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
((STATE) == DMA_PeripheralInc_Disable))
/**
* @}
*/
/** @defgroup DMA_memory_incremented_mode
* @{
*/
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
((STATE) == DMA_MemoryInc_Disable))
/**
* @}
*/
/** @defgroup DMA_peripheral_data_size
* @{
*/
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
((SIZE) == DMA_PeripheralDataSize_Word))
/**
* @}
*/
/** @defgroup DMA_memory_data_size
* @{
*/
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
((SIZE) == DMA_MemoryDataSize_Word))
/**
* @}
*/
/** @defgroup DMA_circular_normal_mode
* @{
*/
#define DMA_Mode_Circular ((uint32_t)0x00000020)
#define DMA_Mode_Normal ((uint32_t)0x00000000)
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
/**
* @}
*/
/** @defgroup DMA_priority_level
* @{
*/
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
#define DMA_Priority_High ((uint32_t)0x00002000)
#define DMA_Priority_Medium ((uint32_t)0x00001000)
#define DMA_Priority_Low ((uint32_t)0x00000000)
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
((PRIORITY) == DMA_Priority_High) || \
((PRIORITY) == DMA_Priority_Medium) || \
((PRIORITY) == DMA_Priority_Low))
/**
* @}
*/
/** @defgroup DMA_memory_to_memory
* @{
*/
#define DMA_M2M_Enable ((uint32_t)0x00004000)
#define DMA_M2M_Disable ((uint32_t)0x00000000)
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
/**
* @}
*/
/** @defgroup DMA_interrupts_definition
* @{
*/
#define DMA_IT_TC ((uint32_t)0x00000002)
#define DMA_IT_HT ((uint32_t)0x00000004)
#define DMA_IT_TE ((uint32_t)0x00000008)
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
#define DMA2_IT_TE1 ((uint32_t)0x10000008)
#define DMA2_IT_GL2 ((uint32_t)0x10000010)
#define DMA2_IT_TC2 ((uint32_t)0x10000020)
#define DMA2_IT_HT2 ((uint32_t)0x10000040)
#define DMA2_IT_TE2 ((uint32_t)0x10000080)
#define DMA2_IT_GL3 ((uint32_t)0x10000100)
#define DMA2_IT_TC3 ((uint32_t)0x10000200)
#define DMA2_IT_HT3 ((uint32_t)0x10000400)
#define DMA2_IT_TE3 ((uint32_t)0x10000800)
#define DMA2_IT_GL4 ((uint32_t)0x10001000)
#define DMA2_IT_TC4 ((uint32_t)0x10002000)
#define DMA2_IT_HT4 ((uint32_t)0x10004000)
#define DMA2_IT_TE4 ((uint32_t)0x10008000)
#define DMA2_IT_GL5 ((uint32_t)0x10010000)
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
/**
* @}
*/
/** @defgroup DMA_flags_definition
* @{
*/
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
/**
* @}
*/
/** @defgroup DMA_Buffer_Size
* @{
*/
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the DMA configuration to the default reset state *****/
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
/* Initialization and Configuration functions *********************************/
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
/* Data Counter functions *****************************************************/
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
/* Interrupts and flags management functions **********************************/
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
void DMA_ClearFlag(uint32_t DMAy_FLAG);
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32L1xx_DMA_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

464
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_flash.h
View file

@ -1,464 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_flash.h
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file contains all the functions prototypes for the FLASH
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_FLASH_H
#define __STM32L1xx_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief FLASH Status
*/
typedef enum
{
FLASH_BUSY = 1,
FLASH_ERROR_WRP,
FLASH_ERROR_PROGRAM,
FLASH_COMPLETE,
FLASH_TIMEOUT
}FLASH_Status;
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Constants
* @{
*/
/** @defgroup FLASH_Latency
* @{
*/
#define FLASH_Latency_0 ((uint8_t)0x00) /*!< FLASH Zero Latency cycle */
#define FLASH_Latency_1 ((uint8_t)0x01) /*!< FLASH One Latency cycle */
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
((LATENCY) == FLASH_Latency_1))
/**
* @}
*/
/** @defgroup FLASH_Interrupts
* @{
*/
#define FLASH_IT_EOP FLASH_PECR_EOPIE /*!< End of programming interrupt source */
#define FLASH_IT_ERR FLASH_PECR_ERRIE /*!< Error interrupt source */
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFCFFFF) == 0x00000000) && (((IT) != 0x00000000)))
/**
* @}
*/
/** @defgroup FLASH_Address
* @{
*/
#define IS_FLASH_DATA_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08080000) && ((ADDRESS) <= 0x08082FFF))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0805FFFF))
/**
* @}
*/
/** @defgroup Option_Bytes_Write_Protection
* @{
*/
#define OB_WRP_Pages0to15 ((uint32_t)0x00000001) /* Write protection of Sector0 */
#define OB_WRP_Pages16to31 ((uint32_t)0x00000002) /* Write protection of Sector1 */
#define OB_WRP_Pages32to47 ((uint32_t)0x00000004) /* Write protection of Sector2 */
#define OB_WRP_Pages48to63 ((uint32_t)0x00000008) /* Write protection of Sector3 */
#define OB_WRP_Pages64to79 ((uint32_t)0x00000010) /* Write protection of Sector4 */
#define OB_WRP_Pages80to95 ((uint32_t)0x00000020) /* Write protection of Sector5 */
#define OB_WRP_Pages96to111 ((uint32_t)0x00000040) /* Write protection of Sector6 */
#define OB_WRP_Pages112to127 ((uint32_t)0x00000080) /* Write protection of Sector7 */
#define OB_WRP_Pages128to143 ((uint32_t)0x00000100) /* Write protection of Sector8 */
#define OB_WRP_Pages144to159 ((uint32_t)0x00000200) /* Write protection of Sector9 */
#define OB_WRP_Pages160to175 ((uint32_t)0x00000400) /* Write protection of Sector10 */
#define OB_WRP_Pages176to191 ((uint32_t)0x00000800) /* Write protection of Sector11 */
#define OB_WRP_Pages192to207 ((uint32_t)0x00001000) /* Write protection of Sector12 */
#define OB_WRP_Pages208to223 ((uint32_t)0x00002000) /* Write protection of Sector13 */
#define OB_WRP_Pages224to239 ((uint32_t)0x00004000) /* Write protection of Sector14 */
#define OB_WRP_Pages240to255 ((uint32_t)0x00008000) /* Write protection of Sector15 */
#define OB_WRP_Pages256to271 ((uint32_t)0x00010000) /* Write protection of Sector16 */
#define OB_WRP_Pages272to287 ((uint32_t)0x00020000) /* Write protection of Sector17 */
#define OB_WRP_Pages288to303 ((uint32_t)0x00040000) /* Write protection of Sector18 */
#define OB_WRP_Pages304to319 ((uint32_t)0x00080000) /* Write protection of Sector19 */
#define OB_WRP_Pages320to335 ((uint32_t)0x00100000) /* Write protection of Sector20 */
#define OB_WRP_Pages336to351 ((uint32_t)0x00200000) /* Write protection of Sector21 */
#define OB_WRP_Pages352to367 ((uint32_t)0x00400000) /* Write protection of Sector22 */
#define OB_WRP_Pages368to383 ((uint32_t)0x00800000) /* Write protection of Sector23 */
#define OB_WRP_Pages384to399 ((uint32_t)0x01000000) /* Write protection of Sector24 */
#define OB_WRP_Pages400to415 ((uint32_t)0x02000000) /* Write protection of Sector25 */
#define OB_WRP_Pages416to431 ((uint32_t)0x04000000) /* Write protection of Sector26 */
#define OB_WRP_Pages432to447 ((uint32_t)0x08000000) /* Write protection of Sector27 */
#define OB_WRP_Pages448to463 ((uint32_t)0x10000000) /* Write protection of Sector28 */
#define OB_WRP_Pages464to479 ((uint32_t)0x20000000) /* Write protection of Sector29 */
#define OB_WRP_Pages480to495 ((uint32_t)0x40000000) /* Write protection of Sector30 */
#define OB_WRP_Pages496to511 ((uint32_t)0x80000000) /* Write protection of Sector31 */
#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
#define OB_WRP1_Pages512to527 ((uint32_t)0x00000001) /* Write protection of Sector32 */
#define OB_WRP1_Pages528to543 ((uint32_t)0x00000002) /* Write protection of Sector33 */
#define OB_WRP1_Pages544to559 ((uint32_t)0x00000004) /* Write protection of Sector34 */
#define OB_WRP1_Pages560to575 ((uint32_t)0x00000008) /* Write protection of Sector35 */
#define OB_WRP1_Pages576to591 ((uint32_t)0x00000010) /* Write protection of Sector36 */
#define OB_WRP1_Pages592to607 ((uint32_t)0x00000020) /* Write protection of Sector37 */
#define OB_WRP1_Pages608to623 ((uint32_t)0x00000040) /* Write protection of Sector38 */
#define OB_WRP1_Pages624to639 ((uint32_t)0x00000080) /* Write protection of Sector39 */
#define OB_WRP1_Pages640to655 ((uint32_t)0x00000100) /* Write protection of Sector40 */
#define OB_WRP1_Pages656to671 ((uint32_t)0x00000200) /* Write protection of Sector41 */
#define OB_WRP1_Pages672to687 ((uint32_t)0x00000400) /* Write protection of Sector42 */
#define OB_WRP1_Pages688to703 ((uint32_t)0x00000800) /* Write protection of Sector43 */
#define OB_WRP1_Pages704to719 ((uint32_t)0x00001000) /* Write protection of Sector44 */
#define OB_WRP1_Pages720to735 ((uint32_t)0x00002000) /* Write protection of Sector45 */
#define OB_WRP1_Pages736to751 ((uint32_t)0x00004000) /* Write protection of Sector46 */
#define OB_WRP1_Pages752to767 ((uint32_t)0x00008000) /* Write protection of Sector47 */
#define OB_WRP1_Pages768to783 ((uint32_t)0x00010000) /* Write protection of Sector48 */
#define OB_WRP1_Pages784to799 ((uint32_t)0x00020000) /* Write protection of Sector49 */
#define OB_WRP1_Pages800to815 ((uint32_t)0x00040000) /* Write protection of Sector50 */
#define OB_WRP1_Pages816to831 ((uint32_t)0x00080000) /* Write protection of Sector51 */
#define OB_WRP1_Pages832to847 ((uint32_t)0x00100000) /* Write protection of Sector52 */
#define OB_WRP1_Pages848to863 ((uint32_t)0x00200000) /* Write protection of Sector53 */
#define OB_WRP1_Pages864to879 ((uint32_t)0x00400000) /* Write protection of Sector54 */
#define OB_WRP1_Pages880to895 ((uint32_t)0x00800000) /* Write protection of Sector55 */
#define OB_WRP1_Pages896to911 ((uint32_t)0x01000000) /* Write protection of Sector56 */
#define OB_WRP1_Pages912to927 ((uint32_t)0x02000000) /* Write protection of Sector57 */
#define OB_WRP1_Pages928to943 ((uint32_t)0x04000000) /* Write protection of Sector58 */
#define OB_WRP1_Pages944to959 ((uint32_t)0x08000000) /* Write protection of Sector59 */
#define OB_WRP1_Pages960to975 ((uint32_t)0x10000000) /* Write protection of Sector60 */
#define OB_WRP1_Pages976to991 ((uint32_t)0x20000000) /* Write protection of Sector61 */
#define OB_WRP1_Pages992to1007 ((uint32_t)0x40000000) /* Write protection of Sector62 */
#define OB_WRP1_Pages1008to1023 ((uint32_t)0x80000000) /* Write protection of Sector63 */
#define OB_WRP1_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
#define OB_WRP2_Pages1024to1039 ((uint32_t)0x00000001) /* Write protection of Sector64 */
#define OB_WRP2_Pages1040to1055 ((uint32_t)0x00000002) /* Write protection of Sector65 */
#define OB_WRP2_Pages1056to1071 ((uint32_t)0x00000004) /* Write protection of Sector66 */
#define OB_WRP2_Pages1072to1087 ((uint32_t)0x00000008) /* Write protection of Sector67 */
#define OB_WRP2_Pages1088to1103 ((uint32_t)0x00000010) /* Write protection of Sector68 */
#define OB_WRP2_Pages1104to1119 ((uint32_t)0x00000020) /* Write protection of Sector69 */
#define OB_WRP2_Pages1120to1135 ((uint32_t)0x00000040) /* Write protection of Sector70 */
#define OB_WRP2_Pages1136to1151 ((uint32_t)0x00000080) /* Write protection of Sector71 */
#define OB_WRP2_Pages1152to1167 ((uint32_t)0x00000100) /* Write protection of Sector72 */
#define OB_WRP2_Pages1168to1183 ((uint32_t)0x00000200) /* Write protection of Sector73 */
#define OB_WRP2_Pages1184to1199 ((uint32_t)0x00000400) /* Write protection of Sector74 */
#define OB_WRP2_Pages1200to1215 ((uint32_t)0x00000800) /* Write protection of Sector75 */
#define OB_WRP2_Pages1216to1231 ((uint32_t)0x00001000) /* Write protection of Sector76 */
#define OB_WRP2_Pages1232to1247 ((uint32_t)0x00002000) /* Write protection of Sector77 */
#define OB_WRP2_Pages1248to1263 ((uint32_t)0x00004000) /* Write protection of Sector78 */
#define OB_WRP2_Pages1264to1279 ((uint32_t)0x00008000) /* Write protection of Sector79 */
#define OB_WRP2_Pages1280to1295 ((uint32_t)0x00010000) /* Write protection of Sector80 */
#define OB_WRP2_Pages1296to1311 ((uint32_t)0x00020000) /* Write protection of Sector81 */
#define OB_WRP2_Pages1312to1327 ((uint32_t)0x00040000) /* Write protection of Sector82 */
#define OB_WRP2_Pages1328to1343 ((uint32_t)0x00080000) /* Write protection of Sector83 */
#define OB_WRP2_Pages1344to1359 ((uint32_t)0x00100000) /* Write protection of Sector84 */
#define OB_WRP2_Pages1360to1375 ((uint32_t)0x00200000) /* Write protection of Sector85 */
#define OB_WRP2_Pages1376to1391 ((uint32_t)0x00400000) /* Write protection of Sector86 */
#define OB_WRP2_Pages1392to1407 ((uint32_t)0x00800000) /* Write protection of Sector87 */
#define OB_WRP2_Pages1408to1423 ((uint32_t)0x01000000) /* Write protection of Sector88 */
#define OB_WRP2_Pages1424to1439 ((uint32_t)0x02000000) /* Write protection of Sector89 */
#define OB_WRP2_Pages1440to1455 ((uint32_t)0x04000000) /* Write protection of Sector90 */
#define OB_WRP2_Pages1456to1471 ((uint32_t)0x08000000) /* Write protection of Sector91 */
#define OB_WRP2_Pages1472to1487 ((uint32_t)0x10000000) /* Write protection of Sector92 */
#define OB_WRP2_Pages1488to1503 ((uint32_t)0x20000000) /* Write protection of Sector93 */
#define OB_WRP2_Pages1504to1519 ((uint32_t)0x40000000) /* Write protection of Sector94 */
#define OB_WRP2_Pages1520to1535 ((uint32_t)0x80000000) /* Write protection of Sector95 */
#define OB_WRP2_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
/**
* @}
*/
/** @defgroup Option_Bytes_Read_Protection
* @{
*/
/**
* @brief Read Protection Level
*/
#define OB_RDP_Level_0 ((uint8_t)0xAA)
#define OB_RDP_Level_1 ((uint8_t)0xBB)
/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
it's no more possible to go back to level 1 or 0 */
#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
((LEVEL) == OB_RDP_Level_1))/*||\
((LEVEL) == OB_RDP_Level_2))*/
/**
* @}
*/
/** @defgroup Option_Bytes_IWatchdog
* @{
*/
#define OB_IWDG_SW ((uint8_t)0x10) /*!< Software WDG selected */
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware WDG selected */
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
/**
* @}
*/
/** @defgroup Option_Bytes_nRST_STOP
* @{
*/
#define OB_STOP_NoRST ((uint8_t)0x20) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
/**
* @}
*/
/** @defgroup Option_Bytes_nRST_STDBY
* @{
*/
#define OB_STDBY_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
/**
* @}
*/
/** @defgroup Option_Bytes_BOOT
* @{
*/
#define OB_BOOT_BANK2 ((uint8_t)0x00) /*!< At startup, if boot pins are set in boot from user Flash position
and this parameter is selected the device will boot from Bank 2
or Bank 1, depending on the activation of the bank */
#define OB_BOOT_BANK1 ((uint8_t)0x80) /*!< At startup, if boot pins are set in boot from user Flash position
and this parameter is selected the device will boot from Bank1(Default) */
#define IS_OB_BOOT_BANK(BANK) (((BANK) == OB_BOOT_BANK2) || ((BANK) == OB_BOOT_BANK1))
/**
* @}
*/
/** @defgroup Option_Bytes_BOR_Level
* @{
*/
#define OB_BOR_OFF ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD
power supply reaches the PDR(Power Down Reset) threshold (1.5V) */
#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */
#define OB_BOR_LEVEL2 ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */
#define OB_BOR_LEVEL3 ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */
#define OB_BOR_LEVEL4 ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */
#define OB_BOR_LEVEL5 ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */
#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_OFF) || \
((LEVEL) == OB_BOR_LEVEL1) || \
((LEVEL) == OB_BOR_LEVEL2) || \
((LEVEL) == OB_BOR_LEVEL3) || \
((LEVEL) == OB_BOR_LEVEL4) || \
((LEVEL) == OB_BOR_LEVEL5))
/**
* @}
*/
/** @defgroup FLASH_Flags
* @{
*/
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
#define FLASH_FLAG_ENDHV FLASH_SR_ENHV /*!< FLASH End of High Voltage flag */
#define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */
#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */
#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */
#define FLASH_FLAG_OPTVERRUSR FLASH_SR_OPTVERRUSR /*!< FLASH Option User Validity error flag */
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE0FD) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
((FLAG) == FLASH_FLAG_ENDHV) || ((FLAG) == FLASH_FLAG_READY ) || \
((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR ) || \
((FLAG) == FLASH_FLAG_SIZERR) || ((FLAG) == FLASH_FLAG_OPTVERR) || \
((FLAG) == FLASH_FLAG_OPTVERRUSR))
/**
* @}
*/
/** @defgroup FLASH_Keys
* @{
*/
#define FLASH_PDKEY1 ((uint32_t)0x04152637) /*!< Flash power down key1 */
#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1
to unlock the RUN_PD bit in FLASH_ACR */
#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEF) /*!< Flash program erase key1 */
#define FLASH_PEKEY2 ((uint32_t)0x02030405) /*!< Flash program erase key: used with FLASH_PEKEY2
to unlock the write access to the FLASH_PECR register and
data EEPROM */
#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBF) /*!< Flash program memory key1 */
#define FLASH_PRGKEY2 ((uint32_t)0x13141516) /*!< Flash program memory key2: used with FLASH_PRGKEY2
to unlock the program memory */
#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8) /*!< Flash option key1 */
#define FLASH_OPTKEY2 ((uint32_t)0x24252627) /*!< Flash option key2: used with FLASH_OPTKEY1 to
unlock the write access to the option byte block */
/**
* @}
*/
/** @defgroup Timeout_definition
* @{
*/
#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x8000)
/**
* @}
*/
/** @defgroup CMSIS_Legacy
* @{
*/
#if defined ( __ICCARM__ )
#define InterruptType_ACTLR_DISMCYCINT_Msk IntType_ACTLR_DISMCYCINT_Msk
#endif
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/**
* @brief FLASH memory functions that can be executed from FLASH.
*/
/* FLASH Interface configuration functions ************************************/
void FLASH_SetLatency(uint32_t FLASH_Latency);
void FLASH_PrefetchBufferCmd(FunctionalState NewState);
void FLASH_ReadAccess64Cmd(FunctionalState NewState);
void FLASH_SLEEPPowerDownCmd(FunctionalState NewState);
/* FLASH Memory Programming functions *****************************************/
void FLASH_Unlock(void);
void FLASH_Lock(void);
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data);
/* DATA EEPROM Programming functions ******************************************/
void DATA_EEPROM_Unlock(void);
void DATA_EEPROM_Lock(void);
void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState);
FLASH_Status DATA_EEPROM_EraseByte(uint32_t Address);
FLASH_Status DATA_EEPROM_EraseHalfWord(uint32_t Address);
FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address);
FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);
FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);
FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);
FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);
FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);
FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);
/* Option Bytes Programming functions *****************************************/
void FLASH_OB_Unlock(void);
void FLASH_OB_Lock(void);
void FLASH_OB_Launch(void);
FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState);
FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState);
FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR);
FLASH_Status FLASH_OB_BootConfig(uint8_t OB_BOOT);
uint8_t FLASH_OB_GetUser(void);
uint32_t FLASH_OB_GetWRP(void);
uint32_t FLASH_OB_GetWRP1(void);
uint32_t FLASH_OB_GetWRP2(void);
FlagStatus FLASH_OB_GetRDP(void);
uint8_t FLASH_OB_GetBOR(void);
/* Interrupts and flags management functions **********************************/
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
FLASH_Status FLASH_GetStatus(void);
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
/**
* @brief FLASH memory functions that should be executed from internal SRAM.
* These functions are defined inside the "stm32l1xx_flash_ramfunc.c"
* file.
*/
__RAM_FUNC FLASH_RUNPowerDownCmd(FunctionalState NewState);
__RAM_FUNC FLASH_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2);
__RAM_FUNC FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer);
__RAM_FUNC FLASH_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2);
__RAM_FUNC DATA_EEPROM_EraseDoubleWord(uint32_t Address);
__RAM_FUNC DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data);
#ifdef __cplusplus
}
#endif
#endif /* __STM32L1xx_FLASH_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_fsmc.h
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@ -1,438 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_fsmc.h
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file contains all the functions prototypes for the FSMC firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_FSMC_H
#define __STM32L1xx_FSMC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @addtogroup FSMC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief Timing parameters For NOR/SRAM Banks
*/
typedef struct
{
uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address setup time.
This parameter can be a value between 0 and 0xF.
@note It is not used with synchronous NOR Flash memories. */
uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address hold time.
This parameter can be a value between 0 and 0xF.
@note It is not used with synchronous NOR Flash memories.*/
uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between 0 and 0xFF.
@note It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
the duration of the bus turnaround.
This parameter can be a value between 0 and 0xF.
@note It is only used for multiplexed NOR Flash memories. */
uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
This parameter can be a value between 1 and 0xF.
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
to the memory before getting the first data.
The parameter value depends on the memory type as shown below:
- It must be set to 0 in case of a CRAM
- It is don't care in asynchronous NOR, SRAM or ROM accesses
- It may assume a value between 0 and 0xF in NOR Flash memories
with synchronous burst mode enable */
uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
This parameter can be a value of @ref FSMC_Access_Mode */
}FSMC_NORSRAMTimingInitTypeDef;
/**
* @brief FSMC NOR/SRAM Init structure definition
*/
typedef struct
{
uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
This parameter can be a value of @ref FSMC_NORSRAM_Bank */
uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the databus or not.
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory bank.
This parameter can be a value of @ref FSMC_Memory_Type */
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be a value of @ref FSMC_Data_Width */
uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
This parameter can be a value of @ref FSMC_AsynchronousWait */
uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
memory, valid only when accessing Flash memories in burst mode.
This parameter can be a value of @ref FSMC_Wrap_Mode */
uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
valid only when accessing memories in burst mode.
This parameter can be a value of @ref FSMC_Wait_Timing */
uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
This parameter can be a value of @ref FSMC_Write_Operation */
uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
signal, valid for Flash memory access in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal */
uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
This parameter can be a value of @ref FSMC_Extended_Mode */
uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
This parameter can be a value of @ref FSMC_Write_Burst */
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
}FSMC_NORSRAMInitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup FSMC_Exported_Constants
* @{
*/
/** @defgroup FSMC_NORSRAM_Bank
* @{
*/
#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
((BANK) == FSMC_Bank1_NORSRAM2) || \
((BANK) == FSMC_Bank1_NORSRAM3) || \
((BANK) == FSMC_Bank1_NORSRAM4))
/**
* @}
*/
/** @defgroup NOR_SRAM_Controller
* @{
*/
/** @defgroup FSMC_Data_Address_Bus_Multiplexing
* @{
*/
#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
((MUX) == FSMC_DataAddressMux_Enable))
/**
* @}
*/
/** @defgroup FSMC_Memory_Type
* @{
*/
#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
((MEMORY) == FSMC_MemoryType_PSRAM)|| \
((MEMORY) == FSMC_MemoryType_NOR))
/**
* @}
*/
/** @defgroup FSMC_Data_Width
* @{
*/
#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
((WIDTH) == FSMC_MemoryDataWidth_16b))
/**
* @}
*/
/** @defgroup FSMC_Burst_Access_Mode
* @{
*/
#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
((STATE) == FSMC_BurstAccessMode_Enable))
/**
* @}
*/
/** @defgroup FSMC_AsynchronousWait
* @{
*/
#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
((STATE) == FSMC_AsynchronousWait_Enable))
/**
* @}
*/
/** @defgroup FSMC_Wait_Signal_Polarity
* @{
*/
#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
((POLARITY) == FSMC_WaitSignalPolarity_High))
/**
* @}
*/
/** @defgroup FSMC_Wrap_Mode
* @{
*/
#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
((MODE) == FSMC_WrapMode_Enable))
/**
* @}
*/
/** @defgroup FSMC_Wait_Timing
* @{
*/
#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
/**
* @}
*/
/** @defgroup FSMC_Write_Operation
* @{
*/
#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
((OPERATION) == FSMC_WriteOperation_Enable))
/**
* @}
*/
/** @defgroup FSMC_Wait_Signal
* @{
*/
#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
((SIGNAL) == FSMC_WaitSignal_Enable))
/**
* @}
*/
/** @defgroup FSMC_Extended_Mode
* @{
*/
#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
((MODE) == FSMC_ExtendedMode_Enable))
/**
* @}
*/
/** @defgroup FSMC_Write_Burst
* @{
*/
#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
((BURST) == FSMC_WriteBurst_Enable))
/**
* @}
*/
/** @defgroup FSMC_Address_Setup_Time
* @{
*/
#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
/**
* @}
*/
/** @defgroup FSMC_Address_Hold_Time
* @{
*/
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
/**
* @}
*/
/** @defgroup FSMC_Data_Setup_Time
* @{
*/
#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
/**
* @}
*/
/** @defgroup FSMC_Bus_Turn_around_Duration
* @{
*/
#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
/**
* @}
*/
/** @defgroup FSMC_CLK_Division
* @{
*/
#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
/**
* @}
*/
/** @defgroup FSMC_Data_Latency
* @{
*/
#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
/**
* @}
*/
/** @defgroup FSMC_Access_Mode
* @{
*/
#define FSMC_AccessMode_A ((uint32_t)0x00000000)
#define FSMC_AccessMode_B ((uint32_t)0x10000000)
#define FSMC_AccessMode_C ((uint32_t)0x20000000)
#define FSMC_AccessMode_D ((uint32_t)0x30000000)
#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
((MODE) == FSMC_AccessMode_B) || \
((MODE) == FSMC_AccessMode_C) || \
((MODE) == FSMC_AccessMode_D))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* NOR/SRAM Controller functions **********************************************/
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
#ifdef __cplusplus
}
#endif
#endif /*__STM32L1xx_FSMC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_i2c.h
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@ -1,703 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_i2c.h
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file contains all the functions prototypes for the I2C firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_I2C_H
#define __STM32L1xx_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief I2C Init structure definition
*/
typedef struct
{
uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
This parameter must be set to a value lower than 400kHz */
uint16_t I2C_Mode; /*!< Specifies the I2C mode.
This parameter can be a value of @ref I2C_mode */
uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
This parameter can be a value of @ref I2C_acknowledgement */
uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
This parameter can be a value of @ref I2C_acknowledged_address */
}I2C_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_Exported_Constants
* @{
*/
#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
((PERIPH) == I2C2))
/** @defgroup I2C_mode
* @{
*/
#define I2C_Mode_I2C ((uint16_t)0x0000)
#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
((MODE) == I2C_Mode_SMBusDevice) || \
((MODE) == I2C_Mode_SMBusHost))
/**
* @}
*/
/** @defgroup I2C_duty_cycle_in_fast_mode
* @{
*/
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
((CYCLE) == I2C_DutyCycle_2))
/**
* @}
*/
/** @defgroup I2C_acknowledgement
* @{
*/
#define I2C_Ack_Enable ((uint16_t)0x0400)
#define I2C_Ack_Disable ((uint16_t)0x0000)
#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
((STATE) == I2C_Ack_Disable))
/**
* @}
*/
/** @defgroup I2C_transfer_direction
* @{
*/
#define I2C_Direction_Transmitter ((uint8_t)0x00)
#define I2C_Direction_Receiver ((uint8_t)0x01)
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
((DIRECTION) == I2C_Direction_Receiver))
/**
* @}
*/
/** @defgroup I2C_acknowledged_address
* @{
*/
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
((ADDRESS) == I2C_AcknowledgedAddress_10bit))
/**
* @}
*/
/** @defgroup I2C_registers
* @{
*/
#define I2C_Register_CR1 ((uint8_t)0x00)
#define I2C_Register_CR2 ((uint8_t)0x04)
#define I2C_Register_OAR1 ((uint8_t)0x08)
#define I2C_Register_OAR2 ((uint8_t)0x0C)
#define I2C_Register_DR ((uint8_t)0x10)
#define I2C_Register_SR1 ((uint8_t)0x14)
#define I2C_Register_SR2 ((uint8_t)0x18)
#define I2C_Register_CCR ((uint8_t)0x1C)
#define I2C_Register_TRISE ((uint8_t)0x20)
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
((REGISTER) == I2C_Register_CR2) || \
((REGISTER) == I2C_Register_OAR1) || \
((REGISTER) == I2C_Register_OAR2) || \
((REGISTER) == I2C_Register_DR) || \
((REGISTER) == I2C_Register_SR1) || \
((REGISTER) == I2C_Register_SR2) || \
((REGISTER) == I2C_Register_CCR) || \
((REGISTER) == I2C_Register_TRISE))
/**
* @}
*/
/** @defgroup I2C_SMBus_alert_pin_level
* @{
*/
#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
((ALERT) == I2C_SMBusAlert_High))
/**
* @}
*/
/** @defgroup I2C_PEC_position
* @{
*/
#define I2C_PECPosition_Next ((uint16_t)0x0800)
#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
((POSITION) == I2C_PECPosition_Current))
/**
* @}
*/
/** @defgroup I2C_NACK_position
* @{
*/
#define I2C_NACKPosition_Next ((uint16_t)0x0800)
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
((POSITION) == I2C_NACKPosition_Current))
/**
* @}
*/
/** @defgroup I2C_interrupts_definition
* @{
*/
#define I2C_IT_BUF ((uint16_t)0x0400)
#define I2C_IT_EVT ((uint16_t)0x0200)
#define I2C_IT_ERR ((uint16_t)0x0100)
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
/**
* @}
*/
/** @defgroup I2C_interrupts_definition
* @{
*/
#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
#define I2C_IT_PECERR ((uint32_t)0x01001000)
#define I2C_IT_OVR ((uint32_t)0x01000800)
#define I2C_IT_AF ((uint32_t)0x01000400)
#define I2C_IT_ARLO ((uint32_t)0x01000200)
#define I2C_IT_BERR ((uint32_t)0x01000100)
#define I2C_IT_TXE ((uint32_t)0x06000080)
#define I2C_IT_RXNE ((uint32_t)0x06000040)
#define I2C_IT_STOPF ((uint32_t)0x02000010)
#define I2C_IT_ADD10 ((uint32_t)0x02000008)
#define I2C_IT_BTF ((uint32_t)0x02000004)
#define I2C_IT_ADDR ((uint32_t)0x02000002)
#define I2C_IT_SB ((uint32_t)0x02000001)
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
/**
* @}
*/
/** @defgroup I2C_flags_definition
* @{
*/
/**
* @brief SR2 register flags
*/
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
#define I2C_FLAG_TRA ((uint32_t)0x00040000)
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
#define I2C_FLAG_MSL ((uint32_t)0x00010000)
/**
* @brief SR1 register flags
*/
#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
#define I2C_FLAG_OVR ((uint32_t)0x10000800)
#define I2C_FLAG_AF ((uint32_t)0x10000400)
#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
#define I2C_FLAG_BERR ((uint32_t)0x10000100)
#define I2C_FLAG_TXE ((uint32_t)0x10000080)
#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
#define I2C_FLAG_BTF ((uint32_t)0x10000004)
#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
#define I2C_FLAG_SB ((uint32_t)0x10000001)
#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
((FLAG) == I2C_FLAG_SB))
/**
* @}
*/
/** @defgroup I2C_Events
* @{
*/
/**
===============================================================================
I2C Master Events (Events grouped in order of communication)
===============================================================================
*/
/**
* @brief Communication start
*
* After sending the START condition (I2C_GenerateSTART() function) the master
* has to wait for this event. It means that the Start condition has been correctly
* released on the I2C bus (the bus is free, no other devices is communicating).
*
*/
/* --EV5 */
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
/**
* @brief Address Acknowledge
*
* After checking on EV5 (start condition correctly released on the bus), the
* master sends the address of the slave(s) with which it will communicate
* (I2C_Send7bitAddress() function, it also determines the direction of the communication:
* Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
* his address. If an acknowledge is sent on the bus, one of the following events will
* be set:
*
* 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
* event is set.
*
* 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
* is set
*
* 3) In case of 10-Bit addressing mode, the master (just after generating the START
* and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
* function). Then master should wait on EV9. It means that the 10-bit addressing
* header has been correctly sent on the bus. Then master should send the second part of
* the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
* should wait for event EV6.
*
*/
/* --EV6 */
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
/* --EV9 */
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
/**
* @brief Communication events
*
* If a communication is established (START condition generated and slave address
* acknowledged) then the master has to check on one of the following events for
* communication procedures:
*
* 1) Master Receiver mode: The master has to wait on the event EV7 then to read
* the data received from the slave (I2C_ReceiveData() function).
*
* 2) Master Transmitter mode: The master has to send data (I2C_SendData()
* function) then to wait on event EV8 or EV8_2.
* These two events are similar:
* - EV8 means that the data has been written in the data register and is
* being shifted out.
* - EV8_2 means that the data has been physically shifted out and output
* on the bus.
* In most cases, using EV8 is sufficient for the application.
* Using EV8_2 leads to a slower communication but ensure more reliable test.
* EV8_2 is also more suitable than EV8 for testing on the last data transmission
* (before Stop condition generation).
*
* @note In case the user software does not guarantee that this event EV7 is
* managed before the current byte end of transfer, then user may check on EV7
* and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
* In this case the communication may be slower.
*
*/
/* Master RECEIVER mode -----------------------------*/
/* --EV7 */
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
/* Master TRANSMITTER mode --------------------------*/
/* --EV8 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
/* --EV8_2 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
/**
===============================================================================
I2C Slave Events (Events grouped in order of communication)
===============================================================================
*/
/**
* @brief Communication start events
*
* Wait on one of these events at the start of the communication. It means that
* the I2C peripheral detected a Start condition on the bus (generated by master
* device) followed by the peripheral address. The peripheral generates an ACK
* condition on the bus (if the acknowledge feature is enabled through function
* I2C_AcknowledgeConfig()) and the events listed above are set :
*
* 1) In normal case (only one address managed by the slave), when the address
* sent by the master matches the own address of the peripheral (configured by
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
* (where XXX could be TRANSMITTER or RECEIVER).
*
* 2) In case the address sent by the master matches the second address of the
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
* (where XXX could be TRANSMITTER or RECEIVER) are set.
*
* 3) In case the address sent by the master is General Call (address 0x00) and
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
*
*/
/* --EV1 (all the events below are variants of EV1) */
/* 1) Case of One Single Address managed by the slave */
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
/* 2) Case of Dual address managed by the slave */
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
/* 3) Case of General Call enabled for the slave */
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
/**
* @brief Communication events
*
* Wait on one of these events when EV1 has already been checked and:
*
* - Slave RECEIVER mode:
* - EV2: When the application is expecting a data byte to be received.
* - EV4: When the application is expecting the end of the communication: master
* sends a stop condition and data transmission is stopped.
*
* - Slave Transmitter mode:
* - EV3: When a byte has been transmitted by the slave and the application is expecting
* the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
* used when the user software doesn't guarantee the EV3 is managed before the
* current byte end of transfer.
* - EV3_2: When the master sends a NACK in order to tell slave that data transmission
* shall end (before sending the STOP condition). In this case slave has to stop sending
* data bytes and expect a Stop condition on the bus.
*
* @note In case the user software does not guarantee that the event EV2 is
* managed before the current byte end of transfer, then user may check on EV2
* and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
* In this case the communication may be slower.
*
*/
/* Slave RECEIVER mode --------------------------*/
/* --EV2 */
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
/* --EV4 */
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
/* Slave TRANSMITTER mode -----------------------*/
/* --EV3 */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
/* --EV3_2 */
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
/*
===============================================================================
End of Events Description
===============================================================================
*/
#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
/**
* @}
*/
/** @defgroup I2C_own_address1
* @{
*/
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
/**
* @}
*/
/** @defgroup I2C_clock_speed
* @{
*/
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the I2C configuration to the default reset state *****/
void I2C_DeInit(I2C_TypeDef* I2Cx);
/* Initialization and Configuration functions *********************************/
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
/* Data transfers functions ***************************************************/
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
/* PEC management functions ***************************************************/
void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
/* DMA transfers management functions *****************************************/
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
/* Interrupts, events and flags management functions **************************/
uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
/*
===============================================================================
I2C State Monitoring Functions
===============================================================================
This I2C driver provides three different ways for I2C state monitoring
depending on the application requirements and constraints:
1. Basic state monitoring (Using I2C_CheckEvent() function)
-----------------------------------------------------------
It compares the status registers (SR1 and SR2) content to a given event
(can be the combination of one or more flags).
It returns SUCCESS if the current status includes the given flags
and returns ERROR if one or more flags are missing in the current status.
- When to use
- This function is suitable for most applications as well as for startup
activity since the events are fully described in the product reference
manual (RM0038).
- It is also suitable for users who need to define their own events.
- Limitations
- If an error occurs (ie. error flags are set besides to the monitored
flags), the I2C_CheckEvent() function may return SUCCESS despite
the communication hold or corrupted real state.
In this case, it is advised to use error interrupts to monitor
the error events and handle them in the interrupt IRQ handler.
Note
For error management, it is advised to use the following functions:
- I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
Where x is the peripheral instance (I2C1, I2C2 ...)
- I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
I2Cx_ER_IRQHandler() function in order to determine which error occurred.
- I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
and/or I2C_GenerateStop() in order to clear the error flag and source
and return to correct communciation status.
2. Advanced state monitoring (Using the function I2C_GetLastEvent())
--------------------------------------------------------------------
Using the function I2C_GetLastEvent() which returns the image of both status
registers in a single word (uint32_t) (Status Register 2 value is shifted left
by 16 bits and concatenated to Status Register 1).
- When to use
- This function is suitable for the same applications above but it
allows to overcome the mentioned limitation of I2C_GetFlagStatus()
function.
- The returned value could be compared to events already defined in
the library (stm32l1xx_i2c.h) or to custom values defined by user.
This function is suitable when multiple flags are monitored at the
same time.
- At the opposite of I2C_CheckEvent() function, this function allows
user to choose when an event is accepted (when all events flags are
set and no other flags are set or just when the needed flags are set
like I2C_CheckEvent() function.
- Limitations
- User may need to define his own events.
- Same remark concerning the error management is applicable for this
function if user decides to check only regular communication flags
(and ignores error flags).
3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
-----------------------------------------------------------------------
Using the function I2C_GetFlagStatus() which simply returns the status of
one single flag (ie. I2C_FLAG_RXNE ...).
- When to use
- This function could be used for specific applications or in debug
phase.
- It is suitable when only one flag checking is needed (most I2C
events are monitored through multiple flags).
- Limitations:
- When calling this function, the Status register is accessed.
Some flags are cleared when the status register is accessed.
So checking the status of one Flag, may clear other ones.
- Function may need to be called twice or more in order to monitor
one single event.
For detailed description of Events, please refer to section I2C_Events in
stm32l1xx_i2c.h file.
*/
/*
===============================================================================
1. Basic state monitoring
===============================================================================
*/
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
/*
===============================================================================
2. Advanced state monitoring
===============================================================================
*/
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
/*
===============================================================================
3. Flag-based state monitoring
===============================================================================
*/
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32L1xx_I2C_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

134
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_iwdg.h
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@ -1,134 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_iwdg.h
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file contains all the functions prototypes for the IWDG
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_IWDG_H
#define __STM32L1xx_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @addtogroup IWDG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IWDG_Exported_Constants
* @{
*/
/** @defgroup IWDG_WriteAccess
* @{
*/
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
((ACCESS) == IWDG_WriteAccess_Disable))
/**
* @}
*/
/** @defgroup IWDG_prescaler
* @{
*/
#define IWDG_Prescaler_4 ((uint8_t)0x00)
#define IWDG_Prescaler_8 ((uint8_t)0x01)
#define IWDG_Prescaler_16 ((uint8_t)0x02)
#define IWDG_Prescaler_32 ((uint8_t)0x03)
#define IWDG_Prescaler_64 ((uint8_t)0x04)
#define IWDG_Prescaler_128 ((uint8_t)0x05)
#define IWDG_Prescaler_256 ((uint8_t)0x06)
#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
((PRESCALER) == IWDG_Prescaler_8) || \
((PRESCALER) == IWDG_Prescaler_16) || \
((PRESCALER) == IWDG_Prescaler_32) || \
((PRESCALER) == IWDG_Prescaler_64) || \
((PRESCALER) == IWDG_Prescaler_128)|| \
((PRESCALER) == IWDG_Prescaler_256))
/**
* @}
*/
/** @defgroup IWDG_Flag
* @{
*/
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Prescaler and Counter configuration functions ******************************/
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
void IWDG_SetReload(uint16_t Reload);
void IWDG_ReloadCounter(void);
/* IWDG activation function ***************************************************/
void IWDG_Enable(void);
/* Flag management function ***************************************************/
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
#ifdef __cplusplus
}
#endif
#endif /* __STM32L1xx_IWDG_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

187
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_opamp.h
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@ -1,187 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_opamp.h
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file contains all the functions prototypes for the operational
* amplifiers (opamp) firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_OPAMP_H
#define __STM32L1xx_OPAMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @addtogroup OPAMP
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup OPAMP_Exported_Constants
* @{
*/
/** @defgroup OPAMP_Selection
* @{
*/
#define OPAMP_Selection_OPAMP1 OPAMP_CSR_OPA1PD
#define OPAMP_Selection_OPAMP2 OPAMP_CSR_OPA2PD
#define OPAMP_Selection_OPAMP3 OPAMP_CSR_OPA3PD
#define IS_OPAMP_ALL_PERIPH(PERIPH) (((PERIPH) == OPAMP_Selection_OPAMP1) || \
((PERIPH) == OPAMP_Selection_OPAMP2) || \
((PERIPH) == OPAMP_Selection_OPAMP3))
/**
* @}
*/
/** @defgroup OPAMP_Switches
* @{
*/
/* OPAMP1 Switches */
#define OPAMP_OPAMP1Switch3 OPAMP_CSR_S3SEL1 /*!< OPAMP1 Switch 3 */
#define OPAMP_OPAMP1Switch4 OPAMP_CSR_S4SEL1 /*!< OPAMP1 Switch 4 */
#define OPAMP_OPAMP1Switch5 OPAMP_CSR_S5SEL1 /*!< OPAMP1 Switch 5 */
#define OPAMP_OPAMP1Switch6 OPAMP_CSR_S6SEL1 /*!< OPAMP1 Switch 6 */
#define OPAMP_OPAMP1SwitchANA OPAMP_CSR_ANAWSEL1 /*!< OPAMP1 Switch ANA */
/* OPAMP2 Switches */
#define OPAMP_OPAMP2Switch3 OPAMP_CSR_S3SEL2 /*!< OPAMP2 Switch 3 */
#define OPAMP_OPAMP2Switch4 OPAMP_CSR_S4SEL2 /*!< OPAMP2 Switch 4 */
#define OPAMP_OPAMP2Switch5 OPAMP_CSR_S5SEL2 /*!< OPAMP2 Switch 5 */
#define OPAMP_OPAMP2Switch6 OPAMP_CSR_S6SEL2 /*!< OPAMP2 Switch 6 */
#define OPAMP_OPAMP2Switch7 OPAMP_CSR_S7SEL2 /*!< OPAMP2 Switch 7 */
#define OPAMP_OPAMP2SwitchANA OPAMP_CSR_ANAWSEL2 /*!< OPAMP2 Switch ANA */
/* OPAMP3 Switches */
#define OPAMP_OPAMP3Switch3 OPAMP_CSR_S3SEL3 /*!< OPAMP3 Switch 3 */
#define OPAMP_OPAMP3Switch4 OPAMP_CSR_S4SEL3 /*!< OPAMP3 Switch 4 */
#define OPAMP_OPAMP3Switch5 OPAMP_CSR_S5SEL3 /*!< OPAMP3 Switch 5 */
#define OPAMP_OPAMP3Switch6 OPAMP_CSR_S6SEL3 /*!< OPAMP3 Switch 6 */
#define OPAMP_OPAMP3SwitchANA OPAMP_CSR_ANAWSEL3 /*!< OPAMP3 Switch ANA */
#define IS_OPAMP_SWITCH(SWITCH) ((((SWITCH) & (uint32_t)0xF0E1E1E1) == 0x00) && ((SWITCH) != 0x00))
/**
* @}
*/
/** @defgroup OPAMP_Trimming
* @{
*/
#define OPAMP_Trimming_Factory ((uint32_t)0x00000000) /*!< Factory trimming */
#define OPAMP_Trimming_User OPAMP_OTR_OT_USER /*!< User trimming */
#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_Trimming_Factory) || \
((TRIMMING) == OPAMP_Trimming_User))
/**
* @}
*/
/** @defgroup OPAMP_Input
* @{
*/
#define OPAMP_Input_NMOS OPAMP_CSR_OPA1CAL_H /*!< NMOS input */
#define OPAMP_Input_PMOS OPAMP_CSR_OPA1CAL_L /*!< PMOS input */
#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_Input_NMOS) || \
((INPUT) == OPAMP_Input_PMOS))
/**
* @}
*/
/** @defgroup OPAMP_TrimValue
* @{
*/
#define IS_OPAMP_TRIMMINGVALUE(VALUE) ((VALUE) <= 0x0000001F) /*!< Trimming value */
/**
* @}
*/
/** @defgroup OPAMP_PowerRange
* @{
*/
#define OPAMP_PowerRange_Low ((uint32_t)0x00000000) /*!< Low power range is selected (VDDA is lower than 2.4V) */
#define OPAMP_PowerRange_High OPAMP_CSR_AOP_RANGE /*!< High power range is selected (VDDA is higher than 2.4V) */
#define IS_OPAMP_RANGE(RANGE) (((RANGE) == OPAMP_PowerRange_Low) || \
((RANGE) == OPAMP_PowerRange_High))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Initialization and Configuration functions *********************************/
void OPAMP_DeInit(void);
void OPAMP_SwitchCmd(uint32_t OPAMP_OPAMPxSwitchy, FunctionalState NewState);
void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState);
void OPAMP_LowPowerCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
void OPAMP_PowerRangeSelect(uint32_t OPAMP_PowerRange);
/* Calibration functions ******************************************************/
void OPAMP_OffsetTrimmingModeSelect(uint32_t OPAMP_Trimming);
void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);
void OPAMP_OffsetTrimLowPowerConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);
FlagStatus OPAMP_GetFlagStatus(uint32_t OPAMP_Selection);
#ifdef __cplusplus
}
#endif
#endif /*__STM32L1xx_OPAMP_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

535
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_sdio.h
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@ -1,535 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_sdio.h
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file contains all the functions prototypes for the SDIO firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_SDIO_H
#define __STM32L1xx_SDIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @addtogroup SDIO
* @{
*/
/* Exported types ------------------------------------------------------------*/
typedef struct
{
uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref SDIO_Clock_Edge */
uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
enabled or disabled.
This parameter can be a value of @ref SDIO_Clock_Bypass */
uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
disabled when the bus is idle.
This parameter can be a value of @ref SDIO_Clock_Power_Save */
uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.
This parameter can be a value of @ref SDIO_Bus_Wide */
uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
This parameter can be a value between 0x00 and 0xFF. */
} SDIO_InitTypeDef;
typedef struct
{
uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent
to a card as part of a command message. If a command
contains an argument, it must be loaded into this register
before writing the command to the command register */
uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
This parameter can be a value of @ref SDIO_Response_Type */
uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
is enabled or disabled.
This parameter can be a value of @ref SDIO_CPSM_State */
} SDIO_CmdInitTypeDef;
typedef struct
{
uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */
uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.
This parameter can be a value of @ref SDIO_Data_Block_Size */
uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer
is a read or write.
This parameter can be a value of @ref SDIO_Transfer_Direction */
uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
This parameter can be a value of @ref SDIO_Transfer_Type */
uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
is enabled or disabled.
This parameter can be a value of @ref SDIO_DPSM_State */
} SDIO_DataInitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup SDIO_Exported_Constants
* @{
*/
/** @defgroup SDIO_Clock_Edge
* @{
*/
#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
((EDGE) == SDIO_ClockEdge_Falling))
/**
* @}
*/
/** @defgroup SDIO_Clock_Bypass
* @{
*/
#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
((BYPASS) == SDIO_ClockBypass_Enable))
/**
* @}
*/
/** @defgroup SDIO_Clock_Power_Save
* @{
*/
#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
((SAVE) == SDIO_ClockPowerSave_Enable))
/**
* @}
*/
/** @defgroup SDIO_Bus_Wide
* @{
*/
#define SDIO_BusWide_1b ((uint32_t)0x00000000)
#define SDIO_BusWide_4b ((uint32_t)0x00000800)
#define SDIO_BusWide_8b ((uint32_t)0x00001000)
#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
((WIDE) == SDIO_BusWide_8b))
/**
* @}
*/
/** @defgroup SDIO_Hardware_Flow_Control
* @{
*/
#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
((CONTROL) == SDIO_HardwareFlowControl_Enable))
/**
* @}
*/
/** @defgroup SDIO_Power_State
* @{
*/
#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
#define SDIO_PowerState_ON ((uint32_t)0x00000003)
#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
/**
* @}
*/
/** @defgroup SDIO_Interrupt_soucres
* @{
*/
#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
#define SDIO_IT_TXACT ((uint32_t)0x00001000)
#define SDIO_IT_RXACT ((uint32_t)0x00002000)
#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup SDIO_Command_Index
* @{
*/
#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
/**
* @}
*/
/** @defgroup SDIO_Response_Type
* @{
*/
#define SDIO_Response_No ((uint32_t)0x00000000)
#define SDIO_Response_Short ((uint32_t)0x00000040)
#define SDIO_Response_Long ((uint32_t)0x000000C0)
#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
((RESPONSE) == SDIO_Response_Short) || \
((RESPONSE) == SDIO_Response_Long))
/**
* @}
*/
/** @defgroup SDIO_Wait_Interrupt_State
* @{
*/
#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
((WAIT) == SDIO_Wait_Pend))
/**
* @}
*/
/** @defgroup SDIO_CPSM_State
* @{
*/
#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
/**
* @}
*/
/** @defgroup SDIO_Response_Registers
* @{
*/
#define SDIO_RESP1 ((uint32_t)0x00000000)
#define SDIO_RESP2 ((uint32_t)0x00000004)
#define SDIO_RESP3 ((uint32_t)0x00000008)
#define SDIO_RESP4 ((uint32_t)0x0000000C)
#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
/**
* @}
*/
/** @defgroup SDIO_Data_Length
* @{
*/
#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
/**
* @}
*/
/** @defgroup SDIO_Data_Block_Size
* @{
*/
#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
((SIZE) == SDIO_DataBlockSize_2b) || \
((SIZE) == SDIO_DataBlockSize_4b) || \
((SIZE) == SDIO_DataBlockSize_8b) || \
((SIZE) == SDIO_DataBlockSize_16b) || \
((SIZE) == SDIO_DataBlockSize_32b) || \
((SIZE) == SDIO_DataBlockSize_64b) || \
((SIZE) == SDIO_DataBlockSize_128b) || \
((SIZE) == SDIO_DataBlockSize_256b) || \
((SIZE) == SDIO_DataBlockSize_512b) || \
((SIZE) == SDIO_DataBlockSize_1024b) || \
((SIZE) == SDIO_DataBlockSize_2048b) || \
((SIZE) == SDIO_DataBlockSize_4096b) || \
((SIZE) == SDIO_DataBlockSize_8192b) || \
((SIZE) == SDIO_DataBlockSize_16384b))
/**
* @}
*/
/** @defgroup SDIO_Transfer_Direction
* @{
*/
#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
((DIR) == SDIO_TransferDir_ToSDIO))
/**
* @}
*/
/** @defgroup SDIO_Transfer_Type
* @{
*/
#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
((MODE) == SDIO_TransferMode_Block))
/**
* @}
*/
/** @defgroup SDIO_DPSM_State
* @{
*/
#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
/**
* @}
*/
/** @defgroup SDIO_Flags
* @{
*/
#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
((FLAG) == SDIO_FLAG_DCRCFAIL) || \
((FLAG) == SDIO_FLAG_CTIMEOUT) || \
((FLAG) == SDIO_FLAG_DTIMEOUT) || \
((FLAG) == SDIO_FLAG_TXUNDERR) || \
((FLAG) == SDIO_FLAG_RXOVERR) || \
((FLAG) == SDIO_FLAG_CMDREND) || \
((FLAG) == SDIO_FLAG_CMDSENT) || \
((FLAG) == SDIO_FLAG_DATAEND) || \
((FLAG) == SDIO_FLAG_STBITERR) || \
((FLAG) == SDIO_FLAG_DBCKEND) || \
((FLAG) == SDIO_FLAG_CMDACT) || \
((FLAG) == SDIO_FLAG_TXACT) || \
((FLAG) == SDIO_FLAG_RXACT) || \
((FLAG) == SDIO_FLAG_TXFIFOHE) || \
((FLAG) == SDIO_FLAG_RXFIFOHF) || \
((FLAG) == SDIO_FLAG_TXFIFOF) || \
((FLAG) == SDIO_FLAG_RXFIFOF) || \
((FLAG) == SDIO_FLAG_TXFIFOE) || \
((FLAG) == SDIO_FLAG_RXFIFOE) || \
((FLAG) == SDIO_FLAG_TXDAVL) || \
((FLAG) == SDIO_FLAG_RXDAVL) || \
((FLAG) == SDIO_FLAG_SDIOIT) || \
((FLAG) == SDIO_FLAG_CEATAEND))
#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
((IT) == SDIO_IT_DCRCFAIL) || \
((IT) == SDIO_IT_CTIMEOUT) || \
((IT) == SDIO_IT_DTIMEOUT) || \
((IT) == SDIO_IT_TXUNDERR) || \
((IT) == SDIO_IT_RXOVERR) || \
((IT) == SDIO_IT_CMDREND) || \
((IT) == SDIO_IT_CMDSENT) || \
((IT) == SDIO_IT_DATAEND) || \
((IT) == SDIO_IT_STBITERR) || \
((IT) == SDIO_IT_DBCKEND) || \
((IT) == SDIO_IT_CMDACT) || \
((IT) == SDIO_IT_TXACT) || \
((IT) == SDIO_IT_RXACT) || \
((IT) == SDIO_IT_TXFIFOHE) || \
((IT) == SDIO_IT_RXFIFOHF) || \
((IT) == SDIO_IT_TXFIFOF) || \
((IT) == SDIO_IT_RXFIFOF) || \
((IT) == SDIO_IT_TXFIFOE) || \
((IT) == SDIO_IT_RXFIFOE) || \
((IT) == SDIO_IT_TXDAVL) || \
((IT) == SDIO_IT_RXDAVL) || \
((IT) == SDIO_IT_SDIOIT) || \
((IT) == SDIO_IT_CEATAEND))
#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup SDIO_Read_Wait_Mode
* @{
*/
#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
((MODE) == SDIO_ReadWaitMode_DATA2))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the SDIO configuration to the default reset state ****/
void SDIO_DeInit(void);
/* Initialization and Configuration functions *********************************/
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
void SDIO_ClockCmd(FunctionalState NewState);
void SDIO_SetPowerState(uint32_t SDIO_PowerState);
uint32_t SDIO_GetPowerState(void);
/* DMA transfers management functions *****************************************/
void SDIO_DMACmd(FunctionalState NewState);
/* Command path state machine (CPSM) management functions *********************/
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
uint8_t SDIO_GetCommandResponse(void);
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
/* Data path state machine (DPSM) management functions ************************/
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
uint32_t SDIO_GetDataCounter(void);
uint32_t SDIO_ReadData(void);
void SDIO_WriteData(uint32_t Data);
uint32_t SDIO_GetFIFOCount(void);
/* SDIO IO Cards mode management functions ************************************/
void SDIO_StartSDIOReadWait(FunctionalState NewState);
void SDIO_StopSDIOReadWait(FunctionalState NewState);
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
void SDIO_SetSDIOOperation(FunctionalState NewState);
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
/* CE-ATA mode management functions *******************************************/
void SDIO_CommandCompletionCmd(FunctionalState NewState);
void SDIO_CEATAITCmd(FunctionalState NewState);
void SDIO_SendCEATACmd(FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
void SDIO_ClearFlag(uint32_t SDIO_FLAG);
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32L1xx_SDIO_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

524
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_spi.h
View file

@ -1,524 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_spi.h
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file contains all the functions prototypes for the SPI
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_SPI_H
#define __STM32L1xx_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @addtogroup SPI
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief SPI Init structure definition
*/
typedef struct
{
uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be a value of @ref SPI_data_direction */
uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
This parameter can be a value of @ref SPI_mode */
uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
This parameter can be a value of @ref SPI_data_size */
uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */
uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_Clock_Phase */
uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */
uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
}SPI_InitTypeDef;
/**
* @brief I2S Init structure definition
*/
typedef struct
{
uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
This parameter can be a value of @ref SPI_I2S_Mode */
uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
This parameter can be a value of @ref SPI_I2S_Standard */
uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
This parameter can be a value of @ref SPI_I2S_Data_Format */
uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref SPI_I2S_MCLK_Output */
uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref SPI_I2S_Audio_Frequency */
uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
This parameter can be a value of @ref SPI_I2S_Clock_Polarity */
}I2S_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup SPI_Exported_Constants
* @{
*/
#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
((PERIPH) == SPI2) || \
((PERIPH) == SPI3))
#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
((PERIPH) == SPI3))
/** @defgroup SPI_data_direction
* @{
*/
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
((MODE) == SPI_Direction_2Lines_RxOnly) || \
((MODE) == SPI_Direction_1Line_Rx) || \
((MODE) == SPI_Direction_1Line_Tx))
/**
* @}
*/
/** @defgroup SPI_mode
* @{
*/
#define SPI_Mode_Master ((uint16_t)0x0104)
#define SPI_Mode_Slave ((uint16_t)0x0000)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
((MODE) == SPI_Mode_Slave))
/**
* @}
*/
/** @defgroup SPI_data_size
* @{
*/
#define SPI_DataSize_16b ((uint16_t)0x0800)
#define SPI_DataSize_8b ((uint16_t)0x0000)
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
((DATASIZE) == SPI_DataSize_8b))
/**
* @}
*/
/** @defgroup SPI_Clock_Polarity
* @{
*/
#define SPI_CPOL_Low ((uint16_t)0x0000)
#define SPI_CPOL_High ((uint16_t)0x0002)
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
((CPOL) == SPI_CPOL_High))
/**
* @}
*/
/** @defgroup SPI_Clock_Phase
* @{
*/
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
((CPHA) == SPI_CPHA_2Edge))
/**
* @}
*/
/** @defgroup SPI_Slave_Select_management
* @{
*/
#define SPI_NSS_Soft ((uint16_t)0x0200)
#define SPI_NSS_Hard ((uint16_t)0x0000)
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
((NSS) == SPI_NSS_Hard))
/**
* @}
*/
/** @defgroup SPI_BaudRate_Prescaler
* @{
*/
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
((PRESCALER) == SPI_BaudRatePrescaler_4) || \
((PRESCALER) == SPI_BaudRatePrescaler_8) || \
((PRESCALER) == SPI_BaudRatePrescaler_16) || \
((PRESCALER) == SPI_BaudRatePrescaler_32) || \
((PRESCALER) == SPI_BaudRatePrescaler_64) || \
((PRESCALER) == SPI_BaudRatePrescaler_128) || \
((PRESCALER) == SPI_BaudRatePrescaler_256))
/**
* @}
*/
/** @defgroup SPI_MSB_LSB_transmission
* @{
*/
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
((BIT) == SPI_FirstBit_LSB))
/**
* @}
*/
/** @defgroup SPI_I2S_Mode
* @{
*/
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
((MODE) == I2S_Mode_SlaveRx) || \
((MODE) == I2S_Mode_MasterTx)|| \
((MODE) == I2S_Mode_MasterRx))
/**
* @}
*/
/** @defgroup SPI_I2S_Standard
* @{
*/
#define I2S_Standard_Phillips ((uint16_t)0x0000)
#define I2S_Standard_MSB ((uint16_t)0x0010)
#define I2S_Standard_LSB ((uint16_t)0x0020)
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
((STANDARD) == I2S_Standard_MSB) || \
((STANDARD) == I2S_Standard_LSB) || \
((STANDARD) == I2S_Standard_PCMShort) || \
((STANDARD) == I2S_Standard_PCMLong))
/**
* @}
*/
/** @defgroup SPI_I2S_Data_Format
* @{
*/
#define I2S_DataFormat_16b ((uint16_t)0x0000)
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
#define I2S_DataFormat_24b ((uint16_t)0x0003)
#define I2S_DataFormat_32b ((uint16_t)0x0005)
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
((FORMAT) == I2S_DataFormat_16bextended) || \
((FORMAT) == I2S_DataFormat_24b) || \
((FORMAT) == I2S_DataFormat_32b))
/**
* @}
*/
/** @defgroup SPI_I2S_MCLK_Output
* @{
*/
#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
((OUTPUT) == I2S_MCLKOutput_Disable))
/**
* @}
*/
/** @defgroup SPI_I2S_Audio_Frequency
* @{
*/
#define I2S_AudioFreq_192k ((uint32_t)192000)
#define I2S_AudioFreq_96k ((uint32_t)96000)
#define I2S_AudioFreq_48k ((uint32_t)48000)
#define I2S_AudioFreq_44k ((uint32_t)44100)
#define I2S_AudioFreq_32k ((uint32_t)32000)
#define I2S_AudioFreq_22k ((uint32_t)22050)
#define I2S_AudioFreq_16k ((uint32_t)16000)
#define I2S_AudioFreq_11k ((uint32_t)11025)
#define I2S_AudioFreq_8k ((uint32_t)8000)
#define I2S_AudioFreq_Default ((uint32_t)2)
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
((FREQ) <= I2S_AudioFreq_192k)) || \
((FREQ) == I2S_AudioFreq_Default))
/**
* @}
*/
/** @defgroup SPI_I2S_Clock_Polarity
* @{
*/
#define I2S_CPOL_Low ((uint16_t)0x0000)
#define I2S_CPOL_High ((uint16_t)0x0008)
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
((CPOL) == I2S_CPOL_High))
/**
* @}
*/
/** @defgroup SPI_I2S_DMA_transfer_requests
* @{
*/
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
/**
* @}
*/
/** @defgroup SPI_NSS_internal_software_management
* @{
*/
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
((INTERNAL) == SPI_NSSInternalSoft_Reset))
/**
* @}
*/
/** @defgroup SPI_CRC_Transmit_Receive
* @{
*/
#define SPI_CRC_Tx ((uint8_t)0x00)
#define SPI_CRC_Rx ((uint8_t)0x01)
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
/**
* @}
*/
/** @defgroup SPI_direction_transmit_receive
* @{
*/
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
#define SPI_Direction_Tx ((uint16_t)0x4000)
#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
((DIRECTION) == SPI_Direction_Tx))
/**
* @}
*/
/** @defgroup SPI_I2S_interrupts_definition
* @{
*/
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
#define I2S_IT_UDR ((uint8_t)0x53)
#define SPI_I2S_IT_FRE ((uint8_t)0x58)
#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
((IT) == SPI_I2S_IT_RXNE) || \
((IT) == SPI_I2S_IT_ERR))
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
#define SPI_IT_MODF ((uint8_t)0x55)
#define SPI_IT_CRCERR ((uint8_t)0x54)
#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \
((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\
((IT) == SPI_I2S_IT_FRE))
/**
* @}
*/
/** @defgroup SPI_I2S_flags_definition
* @{
*/
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
#define I2S_FLAG_UDR ((uint16_t)0x0008)
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
#define SPI_FLAG_MODF ((uint16_t)0x0020)
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
#define SPI_I2S_FLAG_FRE ((uint16_t)0x0100)
#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
((FLAG) == SPI_I2S_FLAG_FRE))
/**
* @}
*/
/** @defgroup SPI_CRC_polynomial
* @{
*/
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
/**
* @}
*/
/** @defgroup SPI_I2S_Legacy
* @{
*/
#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx
#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx
#define SPI_IT_TXE SPI_I2S_IT_TXE
#define SPI_IT_RXNE SPI_I2S_IT_RXNE
#define SPI_IT_ERR SPI_I2S_IT_ERR
#define SPI_IT_OVR SPI_I2S_IT_OVR
#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE
#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE
#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR
#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY
#define SPI_DeInit SPI_I2S_DeInit
#define SPI_ITConfig SPI_I2S_ITConfig
#define SPI_DMACmd SPI_I2S_DMACmd
#define SPI_SendData SPI_I2S_SendData
#define SPI_ReceiveData SPI_I2S_ReceiveData
#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus
#define SPI_ClearFlag SPI_I2S_ClearFlag
#define SPI_GetITStatus SPI_I2S_GetITStatus
#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the SPI configuration to the default reset state *****/
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
/* Initialization and Configuration functions *********************************/
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
/* Data transfers functions ***************************************************/
void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
/* Hardware CRC Calculation functions *****************************************/
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
/* DMA transfers management functions *****************************************/
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
#ifdef __cplusplus
}
#endif
#endif /*__STM32L1xx_SPI_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_usart.h
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@ -1,427 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_usart.h
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file contains all the functions prototypes for the USART
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_USART_H
#define __STM32L1xx_USART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @addtogroup USART
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief USART Init Structure definition
*/
typedef struct
{
uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate)))
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_Word_Length */
uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_Stop_Bits */
uint16_t USART_Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode */
uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
or disabled.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
} USART_InitTypeDef;
/**
* @brief USART Clock Init Structure definition
*/
typedef struct
{
uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
This parameter can be a value of @ref USART_Clock */
uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock.
This parameter can be a value of @ref USART_Clock_Polarity */
uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_Clock_Phase */
uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit */
} USART_ClockInitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup USART_Exported_Constants
* @{
*/
#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
((PERIPH) == USART2) || \
((PERIPH) == USART3) || \
((PERIPH) == UART4) || \
((PERIPH) == UART5))
#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
((PERIPH) == USART2) || \
((PERIPH) == USART3))
/** @defgroup USART_Word_Length
* @{
*/
#define USART_WordLength_8b ((uint16_t)0x0000)
#define USART_WordLength_9b ((uint16_t)0x1000)
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
((LENGTH) == USART_WordLength_9b))
/**
* @}
*/
/** @defgroup USART_Stop_Bits
* @{
*/
#define USART_StopBits_1 ((uint16_t)0x0000)
#define USART_StopBits_0_5 ((uint16_t)0x1000)
#define USART_StopBits_2 ((uint16_t)0x2000)
#define USART_StopBits_1_5 ((uint16_t)0x3000)
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
((STOPBITS) == USART_StopBits_0_5) || \
((STOPBITS) == USART_StopBits_2) || \
((STOPBITS) == USART_StopBits_1_5))
/**
* @}
*/
/** @defgroup USART_Parity
* @{
*/
#define USART_Parity_No ((uint16_t)0x0000)
#define USART_Parity_Even ((uint16_t)0x0400)
#define USART_Parity_Odd ((uint16_t)0x0600)
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
((PARITY) == USART_Parity_Even) || \
((PARITY) == USART_Parity_Odd))
/**
* @}
*/
/** @defgroup USART_Mode
* @{
*/
#define USART_Mode_Rx ((uint16_t)0x0004)
#define USART_Mode_Tx ((uint16_t)0x0008)
#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
/**
* @}
*/
/** @defgroup USART_Hardware_Flow_Control
* @{
*/
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
(((CONTROL) == USART_HardwareFlowControl_None) || \
((CONTROL) == USART_HardwareFlowControl_RTS) || \
((CONTROL) == USART_HardwareFlowControl_CTS) || \
((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
/**
* @}
*/
/** @defgroup USART_Clock
* @{
*/
#define USART_Clock_Disable ((uint16_t)0x0000)
#define USART_Clock_Enable ((uint16_t)0x0800)
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
((CLOCK) == USART_Clock_Enable))
/**
* @}
*/
/** @defgroup USART_Clock_Polarity
* @{
*/
#define USART_CPOL_Low ((uint16_t)0x0000)
#define USART_CPOL_High ((uint16_t)0x0400)
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
/**
* @}
*/
/** @defgroup USART_Clock_Phase
* @{
*/
#define USART_CPHA_1Edge ((uint16_t)0x0000)
#define USART_CPHA_2Edge ((uint16_t)0x0200)
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
/**
* @}
*/
/** @defgroup USART_Last_Bit
* @{
*/
#define USART_LastBit_Disable ((uint16_t)0x0000)
#define USART_LastBit_Enable ((uint16_t)0x0100)
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
((LASTBIT) == USART_LastBit_Enable))
/**
* @}
*/
/** @defgroup USART_Interrupt_definition
* @{
*/
#define USART_IT_PE ((uint16_t)0x0028)
#define USART_IT_TXE ((uint16_t)0x0727)
#define USART_IT_TC ((uint16_t)0x0626)
#define USART_IT_RXNE ((uint16_t)0x0525)
#define USART_IT_IDLE ((uint16_t)0x0424)
#define USART_IT_LBD ((uint16_t)0x0846)
#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */
#define USART_IT_CTS ((uint16_t)0x096A)
#define USART_IT_ERR ((uint16_t)0x0060)
#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */
#define USART_IT_NE ((uint16_t)0x0260)
#define USART_IT_FE ((uint16_t)0x0160)
/** @defgroup USART_Legacy
* @{
*/
#define USART_IT_ORE USART_IT_ORE_ER
/**
* @}
*/
#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE_RX) || \
((IT) == USART_IT_ORE_ER) || ((IT) == USART_IT_NE) || \
((IT) == USART_IT_FE))
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
/**
* @}
*/
/** @defgroup USART_DMA_Requests
* @{
*/
#define USART_DMAReq_Tx ((uint16_t)0x0080)
#define USART_DMAReq_Rx ((uint16_t)0x0040)
#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
/**
* @}
*/
/** @defgroup USART_WakeUp_methods
* @{
*/
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
((WAKEUP) == USART_WakeUp_AddressMark))
/**
* @}
*/
/** @defgroup USART_LIN_Break_Detection_Length
* @{
*/
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
((LENGTH) == USART_LINBreakDetectLength_11b))
/**
* @}
*/
/** @defgroup USART_IrDA_Low_Power
* @{
*/
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
#define USART_IrDAMode_Normal ((uint16_t)0x0000)
#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
((MODE) == USART_IrDAMode_Normal))
/**
* @}
*/
/** @defgroup USART_Flags
* @{
*/
#define USART_FLAG_CTS ((uint16_t)0x0200)
#define USART_FLAG_LBD ((uint16_t)0x0100)
#define USART_FLAG_TXE ((uint16_t)0x0080)
#define USART_FLAG_TC ((uint16_t)0x0040)
#define USART_FLAG_RXNE ((uint16_t)0x0020)
#define USART_FLAG_IDLE ((uint16_t)0x0010)
#define USART_FLAG_ORE ((uint16_t)0x0008)
#define USART_FLAG_NE ((uint16_t)0x0004)
#define USART_FLAG_FE ((uint16_t)0x0002)
#define USART_FLAG_PE ((uint16_t)0x0001)
#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x003D0901))
#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the USART configuration to the default reset state ***/
void USART_DeInit(USART_TypeDef* USARTx);
/* Initialization and Configuration functions *********************************/
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
/* Data transfers functions ***************************************************/
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
/* Multi-Processor Communication functions ************************************/
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
/* LIN mode functions *********************************************************/
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SendBreak(USART_TypeDef* USARTx);
/* Half-duplex mode function **************************************************/
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
/* Smartcard mode functions ***************************************************/
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
/* IrDA mode functions ********************************************************/
void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
/* DMA transfers management functions *****************************************/
void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
#ifdef __cplusplus
}
#endif
#endif /* __STM32L1xx_USART_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_wwdg.h
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/**
******************************************************************************
* @file stm32l1xx_wwdg.h
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file contains all the functions prototypes for the WWDG
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_WWDG_H
#define __STM32L1xx_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @addtogroup WWDG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup WWDG_Exported_Constants
* @{
*/
/** @defgroup WWDG_Prescaler
* @{
*/
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
((PRESCALER) == WWDG_Prescaler_2) || \
((PRESCALER) == WWDG_Prescaler_4) || \
((PRESCALER) == WWDG_Prescaler_8))
#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the WWDG configuration to the default reset state ****/
void WWDG_DeInit(void);
/* Prescaler, Refresh window and Counter configuration functions **************/
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
void WWDG_SetWindowValue(uint8_t WindowValue);
void WWDG_EnableIT(void);
void WWDG_SetCounter(uint8_t Counter);
/* WWDG activation functions **************************************************/
void WWDG_Enable(uint8_t Counter);
/* Interrupts and flags management functions **********************************/
FlagStatus WWDG_GetFlagStatus(void);
void WWDG_ClearFlag(void);
#ifdef __cplusplus
}
#endif
#endif /* __STM32L1xx_WWDG_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_adc.c
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FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_aes.c
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/**
******************************************************************************
* @file stm32l1xx_aes.c
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the AES peripheral:
* + Configuration
* + Read/Write operations
* + DMA transfers management
* + Interrupts and flags management
*
* @verbatim
===============================================================================
##### AES Peripheral features #####
===============================================================================
....[..]
(#) The Advanced Encryption Standard hardware accelerator (AES) can be used
to both encipher and decipher data using AES algorithm.
(#) The AES supports 4 operation modes:
(++) Encryption: It consumes 214 clock cycle when processing one 128-bit block
(++) Decryption: It consumes 214 clock cycle when processing one 128-bit block
(++) Key derivation for decryption: It consumes 80 clock cycle when processing one 128-bit block
(++) Key Derivation and decryption: It consumes 288 clock cycle when processing one 128-bit blobk
(#) Moreover 3 chaining modes are supported:
(++) Electronic codebook (ECB): Each plain text is encrypted/decrypted separately
(++) Cipher block chaining (CBC): Each block is XORed with the previous block
(++) Counter mode (CTR): A 128-bit counter is encrypted and then XORed with the
plain text to give the cipher text
(#) The AES peripheral supports data swapping: 1-bit, 8-bit, 16-bit and 32-bit.
(#) The AES peripheral supports write/read error handling with interrupt capability.
(#) Automatic data flow control with support of direct memory access (DMA) using
2 channels, one for incoming data (DMA2 Channel5), and one for outcoming data
(DMA2 Channel3).
##### How to use this driver #####
===============================================================================
[..]
(#) AES AHB clock must be enabled to get write access to AES registers
using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_AES, ENABLE).
(#) Initialize the key using AES_KeyInit().
(#) Configure the AES operation mode using AES_Init().
(#) If required, enable interrupt source using AES_ITConfig() and
enable the AES interrupt vector using NVIC_Init().
(#) If required, when using the DMA mode.
(##) Configure the DMA using DMA_Init().
(##) Enable DMA requests using AES_DMAConfig().
(#) Enable the AES peripheral using AES_Cmd().
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_aes.h"
#include "stm32l1xx_rcc.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @defgroup AES
* @brief AES driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define CR_CLEAR_MASK ((uint32_t)0xFFFFFF81)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup AES_Private_Functions
* @{
*/
/** @defgroup AES_Group1 Initialization and configuration
* @brief Initialization and configuration.
*
@verbatim
===============================================================================
##### Initialization and configuration #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes AES peripheral registers to their default reset values.
* @param None
* @retval None
*/
void AES_DeInit(void)
{
/* Enable AES reset state */
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_AES, ENABLE);
/* Release AES from reset state */
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_AES, DISABLE);
}
/**
* @brief Initializes the AES peripheral according to the specified parameters
* in the AES_InitStruct:
* - AES_Operation: specifies the operation mode (encryption, decryption...).
* - AES_Chaining: specifies the chaining mode (ECB, CBC or CTR).
* - AES_DataType: specifies the data swapping type: 32-bit, 16-bit, 8-bit or 1-bit.
* @note If AES is already enabled, use AES_Cmd(DISABLE) before setting the new
* configuration (When AES is enabled, setting configuration is forbidden).
* @param AES_InitStruct: pointer to an AES_InitTypeDef structure that contains
* the configuration information for AES peripheral.
* @retval None
*/
void AES_Init(AES_InitTypeDef* AES_InitStruct)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_AES_MODE(AES_InitStruct->AES_Operation));
assert_param(IS_AES_CHAINING(AES_InitStruct->AES_Chaining));
assert_param(IS_AES_DATATYPE(AES_InitStruct->AES_DataType));
/* Get AES CR register value */
tmpreg = AES->CR;
/* Clear DATATYPE[1:0], MODE[1:0] and CHMOD[1:0] bits */
tmpreg &= (uint32_t)CR_CLEAR_MASK;
tmpreg |= (AES_InitStruct->AES_Operation | AES_InitStruct->AES_Chaining | AES_InitStruct->AES_DataType);
AES->CR = (uint32_t) tmpreg;
}
/**
* @brief Initializes the AES Keys according to the specified parameters in the AES_KeyInitStruct.
* @param AES_KeyInitStruct: pointer to an AES_KeyInitTypeDef structure that
* contains the configuration information for the specified AES Keys.
* @note This function must be called while the AES is disabled.
* @note In encryption, key derivation and key derivation + decryption modes,
* AES_KeyInitStruct must contain the encryption key.
* In decryption mode, AES_KeyInitStruct must contain the decryption key.
* @retval None
*/
void AES_KeyInit(AES_KeyInitTypeDef* AES_KeyInitStruct)
{
AES->KEYR0 = AES_KeyInitStruct->AES_Key0;
AES->KEYR1 = AES_KeyInitStruct->AES_Key1;
AES->KEYR2 = AES_KeyInitStruct->AES_Key2;
AES->KEYR3 = AES_KeyInitStruct->AES_Key3;
}
/**
* @brief Initializes the AES Initialization Vector IV according to
* the specified parameters in the AES_IVInitStruct.
* @param AES_KeyInitStruct: pointer to an AES_IVInitTypeDef structure that
* contains the configuration information for the specified AES IV.
* @note When ECB chaining mode is selected, Initialization Vector IV has no
* meaning.
* When CTR chaining mode is selected, AES_IV0 contains the CTR value.
* AES_IV1, AES_IV2 and AES_IV3 contains nonce value.
* @retval None
*/
void AES_IVInit(AES_IVInitTypeDef* AES_IVInitStruct)
{
AES->IVR0 = AES_IVInitStruct->AES_IV0;
AES->IVR1 = AES_IVInitStruct->AES_IV1;
AES->IVR2 = AES_IVInitStruct->AES_IV2;
AES->IVR3 = AES_IVInitStruct->AES_IV3;
}
/**
* @brief Enable or disable the AES peripheral.
* @param NewState: new state of the AES peripheral.
* This parameter can be: ENABLE or DISABLE.
* @note The key must be written while AES is disabled.
* @retval None
*/
void AES_Cmd(FunctionalState NewState)
{
/* Check the parameter */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the AES peripheral */
AES->CR |= (uint32_t) AES_CR_EN; /**< AES Enable */
}
else
{
/* Disable the AES peripheral */
AES->CR &= (uint32_t)(~AES_CR_EN); /**< AES Disable */
}
}
/**
* @}
*/
/** @defgroup AES_Group2 Structures initialization functions
* @brief Structures initialization.
*
@verbatim
===============================================================================
##### Structures initialization functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Fills each AES_InitStruct member with its default value.
* @param AES_InitStruct: pointer to an AES_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void AES_StructInit(AES_InitTypeDef* AES_InitStruct)
{
AES_InitStruct->AES_Operation = AES_Operation_Encryp;
AES_InitStruct->AES_Chaining = AES_Chaining_ECB;
AES_InitStruct->AES_DataType = AES_DataType_32b;
}
/**
* @brief Fills each AES_KeyInitStruct member with its default value.
* @param AES_KeyInitStruct: pointer to an AES_KeyInitStruct structure which
* will be initialized.
* @retval None
*/
void AES_KeyStructInit(AES_KeyInitTypeDef* AES_KeyInitStruct)
{
AES_KeyInitStruct->AES_Key0 = 0x00000000;
AES_KeyInitStruct->AES_Key1 = 0x00000000;
AES_KeyInitStruct->AES_Key2 = 0x00000000;
AES_KeyInitStruct->AES_Key3 = 0x00000000;
}
/**
* @brief Fills each AES_IVInitStruct member with its default value.
* @param AES_IVInitStruct: pointer to an AES_IVInitTypeDef structure which
* will be initialized.
* @retval None
*/
void AES_IVStructInit(AES_IVInitTypeDef* AES_IVInitStruct)
{
AES_IVInitStruct->AES_IV0 = 0x00000000;
AES_IVInitStruct->AES_IV1 = 0x00000000;
AES_IVInitStruct->AES_IV2 = 0x00000000;
AES_IVInitStruct->AES_IV3 = 0x00000000;
}
/**
* @}
*/
/** @defgroup AES_Group3 AES Read and Write
* @brief AES Read and Write.
*
@verbatim
===============================================================================
##### AES Read and Write functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Write data in DINR register to be processed by AES peripheral.
* @note To process 128-bit data (4 * 32-bit), this function must be called
* four times to write the 128-bit data in the 32-bit register DINR.
* @note When an unexpected write to DOUTR register is detected, WRERR flag is
* set.
* @param Data: The data to be processed.
* @retval None
*/
void AES_WriteSubData(uint32_t Data)
{
/* Write Data */
AES->DINR = Data;
}
/**
* @brief Returns the data in DOUTR register processed by AES peripheral.
* @note This function must be called four times to get the 128-bit data.
* @note When an unexpected read of DINR register is detected, RDERR flag is
* set.
* @retval The processed data.
*/
uint32_t AES_ReadSubData(void)
{
/* Read Data */
return AES->DOUTR;
}
/**
* @brief Read the Key value.
* @param AES_KeyInitStruct: pointer to an AES_KeyInitTypeDef structure which
* will contain the key.
* @note When the key derivation mode is selected, AES must be disabled
* (AES_Cmd(DISABLE)) before reading the decryption key.
* Reading the key while the AES is enabled will return unpredictable
* value.
* @retval None
*/
void AES_ReadKey(AES_KeyInitTypeDef* AES_KeyInitStruct)
{
AES_KeyInitStruct->AES_Key0 = AES->KEYR0;
AES_KeyInitStruct->AES_Key1 = AES->KEYR1;
AES_KeyInitStruct->AES_Key2 = AES->KEYR2;
AES_KeyInitStruct->AES_Key3 = AES->KEYR3;
}
/**
* @brief Read the Initialization Vector IV value.
* @param AES_IVInitStruct: pointer to an AES_IVInitTypeDef structure which
* will contain the Initialization Vector IV.
* @note When the AES is enabled Reading the Initialization Vector IV value
* will return 0. The AES must be disabled using AES_Cmd(DISABLE)
* to get the right value.
* @note When ECB chaining mode is selected, Initialization Vector IV has no
* meaning.
* When CTR chaining mode is selected, AES_IV0 contains 32-bit Counter value.
* AES_IV1, AES_IV2 and AES_IV3 contains nonce value.
* @retval None
*/
void AES_ReadIV(AES_IVInitTypeDef* AES_IVInitStruct)
{
AES_IVInitStruct->AES_IV0 = AES->IVR0;
AES_IVInitStruct->AES_IV1 = AES->IVR1;
AES_IVInitStruct->AES_IV2 = AES->IVR2;
AES_IVInitStruct->AES_IV3 = AES->IVR3;
}
/**
* @}
*/
/** @defgroup AES_Group4 DMA transfers management functions
* @brief DMA transfers management function.
*
@verbatim
===============================================================================
##### DMA transfers management functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Configures the AES DMA interface.
* @param AES_DMATransfer: Specifies the AES DMA transfer.
* This parameter can be one of the following values:
* @arg AES_DMATransfer_In: When selected, DMA manages the data input phase.
* @arg AES_DMATransfer_Out: When selected, DMA manages the data output phase.
* @arg AES_DMATransfer_InOut: When selected, DMA manages both the data input/output phases.
* @param NewState Indicates the new state of the AES DMA interface.
* This parameter can be: ENABLE or DISABLE.
* @note The DMA has no action in key derivation mode.
* @retval None
*/
void AES_DMAConfig(uint32_t AES_DMATransfer, FunctionalState NewState)
{
/* Check the parameter */
assert_param(IS_AES_DMA_TRANSFER(AES_DMATransfer));
if (NewState != DISABLE)
{
/* Enable the DMA transfer */
AES->CR |= (uint32_t) AES_DMATransfer;
}
else
{
/* Disable the DMA transfer */
AES->CR &= (uint32_t)(~AES_DMATransfer);
}
}
/**
* @}
*/
/** @defgroup AES_Group5 Interrupts and flags management functions
* @brief Interrupts and flags management functions.
*
@verbatim
===============================================================================
##### Interrupts and flags management functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified AES interrupt.
* @param AES_IT: Specifies the AES interrupt source to enable/disable.
* This parameter can be any combinations of the following values:
* @arg AES_IT_CC: Computation Complete Interrupt. If enabled, once CCF
* flag is set an interrupt is generated.
* @arg AES_IT_ERR: Error Interrupt. If enabled, once a read error
* flags (RDERR) or write error flag (WRERR) is set,
* an interrupt is generated.
* @param NewState: The new state of the AES interrupt source.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void AES_ITConfig(uint32_t AES_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_AES_IT(AES_IT));
if (NewState != DISABLE)
{
AES->CR |= (uint32_t) AES_IT; /**< AES_IT Enable */
}
else
{
AES->CR &= (uint32_t)(~AES_IT); /**< AES_IT Disable */
}
}
/**
* @brief Checks whether the specified AES flag is set or not.
* @param AES_FLAG specifies the flag to check.
* This parameter can be one of the following values:
* @arg AES_FLAG_CCF: Computation Complete Flag is set by hardware when
* he computation phase is completed.
* @arg AES_FLAG_RDERR: Read Error Flag is set when an unexpected read
* operation of DOUTR register is detected.
* @arg AES_FLAG_WRERR: Write Error Flag is set when an unexpected write
* operation in DINR is detected.
* @retval FlagStatus (SET or RESET)
*/
FlagStatus AES_GetFlagStatus(uint32_t AES_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check parameters */
assert_param(IS_AES_FLAG(AES_FLAG));
if ((AES->SR & AES_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the AES_FLAG status */
return bitstatus;
}
/**
* @brief Clears the AES flags.
* @param AES_FLAG: specifies the flag to clear.
* This parameter can be:
* @arg AES_FLAG_CCF: Computation Complete Flag is cleared by setting CCFC
* bit in CR register.
* @arg AES_FLAG_RDERR: Read Error is cleared by setting ERRC bit in
* CR register.
* @arg AES_FLAG_WRERR: Write Error is cleared by setting ERRC bit in
* CR register.
* @retval None
*/
void AES_ClearFlag(uint32_t AES_FLAG)
{
/* Check the parameters */
assert_param(IS_AES_FLAG(AES_FLAG));
/* Check if AES_FLAG is AES_FLAG_CCF */
if (AES_FLAG == AES_FLAG_CCF)
{
/* Clear CCF flag by setting CCFC bit */
AES->CR |= (uint32_t) AES_CR_CCFC;
}
else /* AES_FLAG is AES_FLAG_RDERR or AES_FLAG_WRERR */
{
/* Clear RDERR and WRERR flags by setting ERRC bit */
AES->CR |= (uint32_t) AES_CR_ERRC;
}
}
/**
* @brief Checks whether the specified AES interrupt has occurred or not.
* @param AES_IT: Specifies the AES interrupt pending bit to check.
* This parameter can be:
* @arg AES_IT_CC: Computation Complete Interrupt.
* @arg AES_IT_ERR: Error Interrupt.
* @retval ITStatus The new state of AES_IT (SET or RESET).
*/
ITStatus AES_GetITStatus(uint32_t AES_IT)
{
ITStatus itstatus = RESET;
uint32_t cciebitstatus = RESET, ccfbitstatus = RESET;
/* Check parameters */
assert_param(IS_AES_GET_IT(AES_IT));
cciebitstatus = AES->CR & AES_CR_CCIE;
ccfbitstatus = AES->SR & AES_SR_CCF;
/* Check if AES_IT is AES_IT_CC */
if (AES_IT == AES_IT_CC)
{
/* Check the status of the specified AES interrupt */
if (((cciebitstatus) != (uint32_t)RESET) && ((ccfbitstatus) != (uint32_t)RESET))
{
/* Interrupt occurred */
itstatus = SET;
}
else
{
/* Interrupt didn't occur */
itstatus = RESET;
}
}
else /* AES_IT is AES_IT_ERR */
{
/* Check the status of the specified AES interrupt */
if ((AES->CR & AES_CR_ERRIE) != RESET)
{
/* Check if WRERR or RDERR flags are set */
if ((AES->SR & (uint32_t)(AES_SR_WRERR | AES_SR_RDERR)) != (uint16_t)RESET)
{
/* Interrupt occurred */
itstatus = SET;
}
else
{
/* Interrupt didn't occur */
itstatus = RESET;
}
}
else
{
/* Interrupt didn't occur */
itstatus = (ITStatus) RESET;
}
}
/* Return the AES_IT status */
return itstatus;
}
/**
* @brief Clears the AES's interrupt pending bits.
* @param AES_IT: specifies the interrupt pending bit to clear.
* This parameter can be any combinations of the following values:
* @arg AES_IT_CC: Computation Complete Interrupt.
* @arg AES_IT_ERR: Error Interrupt.
* @retval None
*/
void AES_ClearITPendingBit(uint32_t AES_IT)
{
/* Check the parameters */
assert_param(IS_AES_IT(AES_IT));
/* Clear the interrupt pending bit */
AES->CR |= (uint32_t) (AES_IT >> (uint32_t) 0x00000002);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

679
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_aes_util.c
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@ -1,679 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_aes_util.c
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file provides high level functions to encrypt and decrypt an
* input message using AES in ECB/CBC/CTR modes.
*
* @verbatim
================================================================================
##### How to use this driver #####
================================================================================
[..]
(#) Enable The AES controller clock using
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_AES, ENABLE); function.
(#) Use AES_ECB_Encrypt() function to encrypt an input message in ECB mode.
(#) Use AES_ECB_Decrypt() function to decrypt an input message in ECB mode.
(#) Use AES_CBC_Encrypt() function to encrypt an input message in CBC mode.
(#) Use AES_CBC_Decrypt() function to decrypt an input message in CBC mode.
(#) Use AES_CTR_Encrypt() function to encrypt an input message in CTR mode.
(#) Use AES_CTR_Decrypt() function to decrypt an input message in CTR mode.
* @endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_aes.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @addtogroup AES
* @brief AES driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define AES_CC_TIMEOUT ((uint32_t) 0x00010000)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup AES_Private_Functions
* @{
*/
/** @defgroup AES_Group6 High Level AES functions
* @brief High Level AES functions
*
@verbatim
================================================================================
##### High Level AES functions #####
================================================================================
@endverbatim
* @{
*/
/**
* @brief Encrypt using AES in ECB Mode
* @param Key: Key used for AES algorithm.
* @param Input: pointer to the Input buffer.
* @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.
* @param Output: pointer to the returned buffer.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Operation done
* - ERROR: Operation failed
*/
ErrorStatus AES_ECB_Encrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output)
{
AES_InitTypeDef AES_InitStructure;
AES_KeyInitTypeDef AES_KeyInitStructure;
ErrorStatus status = SUCCESS;
uint32_t keyaddr = (uint32_t)Key;
uint32_t inputaddr = (uint32_t)Input;
uint32_t outputaddr = (uint32_t)Output;
__IO uint32_t counter = 0;
uint32_t ccstatus = 0;
uint32_t i = 0;
/* AES Key initialisation */
AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
keyaddr += 4;
AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
keyaddr += 4;
AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
keyaddr += 4;
AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
AES_KeyInit(&AES_KeyInitStructure);
/* AES configuration */
AES_InitStructure.AES_Operation = AES_Operation_Encryp;
AES_InitStructure.AES_Chaining = AES_Chaining_ECB;
AES_InitStructure.AES_DataType = AES_DataType_8b;
AES_Init(&AES_InitStructure);
/* Enable AES */
AES_Cmd(ENABLE);
for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
{
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
/* Wait for CCF flag to be set */
counter = 0;
do
{
ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
counter++;
}while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
if (ccstatus == RESET)
{
status = ERROR;
}
else
{
/* Clear CCF flag */
AES_ClearFlag(AES_FLAG_CCF);
/* Read cipher text */
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
}
}
/* Disable AES before starting new processing */
AES_Cmd(DISABLE);
return status;
}
/**
* @brief Decrypt using AES in ECB Mode
* @param Key: Key used for AES algorithm.
* @param Input: pointer to the Input buffer.
* @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.
* @param Output: pointer to the returned buffer.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Operation done
* - ERROR: Operation failed
*/
ErrorStatus AES_ECB_Decrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output)
{
AES_InitTypeDef AES_InitStructure;
AES_KeyInitTypeDef AES_KeyInitStructure;
ErrorStatus status = SUCCESS;
uint32_t keyaddr = (uint32_t)Key;
uint32_t inputaddr = (uint32_t)Input;
uint32_t outputaddr = (uint32_t)Output;
__IO uint32_t counter = 0;
uint32_t ccstatus = 0;
uint32_t i = 0;
/* AES Key initialisation */
AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
keyaddr += 4;
AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
keyaddr += 4;
AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
keyaddr += 4;
AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
AES_KeyInit(&AES_KeyInitStructure);
/* AES configuration */
AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;
AES_InitStructure.AES_Chaining = AES_Chaining_ECB;
AES_InitStructure.AES_DataType = AES_DataType_8b;
AES_Init(&AES_InitStructure);
/* Enable AES */
AES_Cmd(ENABLE);
for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
{
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
/* Wait for CCF flag to be set */
counter = 0;
do
{
ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
counter++;
}while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
if (ccstatus == RESET)
{
status = ERROR;
}
else
{
/* Clear CCF flag */
AES_ClearFlag(AES_FLAG_CCF);
/* Read cipher text */
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
}
}
/* Disable AES before starting new processing */
AES_Cmd(DISABLE);
return status;
}
/**
* @brief Encrypt using AES in CBC Mode
* @param InitVectors: Initialisation Vectors used for AES algorithm.
* @param Key: Key used for AES algorithm.
* @param Input: pointer to the Input buffer.
* @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.
* @param Output: pointer to the returned buffer.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Operation done
* - ERROR: Operation failed
*/
ErrorStatus AES_CBC_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)
{
AES_InitTypeDef AES_InitStructure;
AES_KeyInitTypeDef AES_KeyInitStructure;
AES_IVInitTypeDef AES_IVInitStructure;
ErrorStatus status = SUCCESS;
uint32_t keyaddr = (uint32_t)Key;
uint32_t inputaddr = (uint32_t)Input;
uint32_t outputaddr = (uint32_t)Output;
uint32_t ivaddr = (uint32_t)InitVectors;
__IO uint32_t counter = 0;
uint32_t ccstatus = 0;
uint32_t i = 0;
/* AES Key initialisation*/
AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
keyaddr += 4;
AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
keyaddr += 4;
AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
keyaddr += 4;
AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
AES_KeyInit(&AES_KeyInitStructure);
/* AES Initialization Vectors */
AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));
ivaddr += 4;
AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));
ivaddr += 4;
AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));
ivaddr += 4;
AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));
AES_IVInit(&AES_IVInitStructure);
/* AES configuration */
AES_InitStructure.AES_Operation = AES_Operation_Encryp;
AES_InitStructure.AES_Chaining = AES_Chaining_CBC;
AES_InitStructure.AES_DataType = AES_DataType_8b;
AES_Init(&AES_InitStructure);
/* Enable AES */
AES_Cmd(ENABLE);
for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
{
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
/* Wait for CCF flag to be set */
counter = 0;
do
{
ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
counter++;
}while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
if (ccstatus == RESET)
{
status = ERROR;
}
else
{
/* Clear CCF flag */
AES_ClearFlag(AES_FLAG_CCF);
/* Read cipher text */
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
}
}
/* Disable AES before starting new processing */
AES_Cmd(DISABLE);
return status;
}
/**
* @brief Decrypt using AES in CBC Mode
* @param InitVectors: Initialisation Vectors used for AES algorithm.
* @param Key: Key used for AES algorithm.
* @param Input: pointer to the Input buffer.
* @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.
* @param Output: pointer to the returned buffer.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Operation done
* - ERROR: Operation failed
*/
ErrorStatus AES_CBC_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)
{
AES_InitTypeDef AES_InitStructure;
AES_KeyInitTypeDef AES_KeyInitStructure;
AES_IVInitTypeDef AES_IVInitStructure;
ErrorStatus status = SUCCESS;
uint32_t keyaddr = (uint32_t)Key;
uint32_t inputaddr = (uint32_t)Input;
uint32_t outputaddr = (uint32_t)Output;
uint32_t ivaddr = (uint32_t)InitVectors;
__IO uint32_t counter = 0;
uint32_t ccstatus = 0;
uint32_t i = 0;
/* AES Key initialisation*/
AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
keyaddr += 4;
AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
keyaddr += 4;
AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
keyaddr += 4;
AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
AES_KeyInit(&AES_KeyInitStructure);
/* AES Initialization Vectors */
AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));
ivaddr += 4;
AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));
ivaddr += 4;
AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));
ivaddr += 4;
AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));
AES_IVInit(&AES_IVInitStructure);
/* AES configuration */
AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;
AES_InitStructure.AES_Chaining = AES_Chaining_CBC;
AES_InitStructure.AES_DataType = AES_DataType_8b;
AES_Init(&AES_InitStructure);
/* Enable AES */
AES_Cmd(ENABLE);
for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
{
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
/* Wait for CCF flag to be set */
counter = 0;
do
{
ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
counter++;
}while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
if (ccstatus == RESET)
{
status = ERROR;
}
else
{
/* Clear CCF flag */
AES_ClearFlag(AES_FLAG_CCF);
/* Read cipher text */
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
}
}
/* Disable AES before starting new processing */
AES_Cmd(DISABLE);
return status;
}
/**
* @brief Encrypt using AES in CTR Mode
* @param InitVectors: Initialisation Vectors used for AES algorithm.
* @param Key: Key used for AES algorithm.
* @param Input: pointer to the Input buffer.
* @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.
* @param Output: pointer to the returned buffer.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Operation done
* - ERROR: Operation failed
*/
ErrorStatus AES_CTR_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)
{
AES_InitTypeDef AES_InitStructure;
AES_KeyInitTypeDef AES_KeyInitStructure;
AES_IVInitTypeDef AES_IVInitStructure;
ErrorStatus status = SUCCESS;
uint32_t keyaddr = (uint32_t)Key;
uint32_t inputaddr = (uint32_t)Input;
uint32_t outputaddr = (uint32_t)Output;
uint32_t ivaddr = (uint32_t)InitVectors;
__IO uint32_t counter = 0;
uint32_t ccstatus = 0;
uint32_t i = 0;
/* AES key initialisation*/
AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
keyaddr += 4;
AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
keyaddr += 4;
AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
keyaddr += 4;
AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
AES_KeyInit(&AES_KeyInitStructure);
/* AES Initialization Vectors */
AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));
ivaddr += 4;
AES_IVInitStructure.AES_IV2= __REV(*(uint32_t*)(ivaddr));
ivaddr += 4;
AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));
ivaddr += 4;
AES_IVInitStructure.AES_IV0= __REV(*(uint32_t*)(ivaddr));
AES_IVInit(&AES_IVInitStructure);
/* AES configuration */
AES_InitStructure.AES_Operation = AES_Operation_Encryp;
AES_InitStructure.AES_Chaining = AES_Chaining_CTR;
AES_InitStructure.AES_DataType = AES_DataType_8b;
AES_Init(&AES_InitStructure);
/* Enable AES */
AES_Cmd(ENABLE);
for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
{
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
/* Wait for CCF flag to be set */
counter = 0;
do
{
ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
counter++;
}while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
if (ccstatus == RESET)
{
status = ERROR;
}
else
{
/* Clear CCF flag */
AES_ClearFlag(AES_FLAG_CCF);
/* Read cipher text */
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
}
}
/* Disable AES before starting new processing */
AES_Cmd(DISABLE);
return status;
}
/**
* @brief Decrypt using AES in CTR Mode
* @param InitVectors: Initialisation Vectors used for AES algorithm.
* @param Key: Key used for AES algorithm.
* @param Input: pointer to the Input buffer.
* @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.
* @param Output: pointer to the returned buffer.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Operation done
* - ERROR: Operation failed
*/
ErrorStatus AES_CTR_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)
{
AES_InitTypeDef AES_InitStructure;
AES_KeyInitTypeDef AES_KeyInitStructure;
AES_IVInitTypeDef AES_IVInitStructure;
ErrorStatus status = SUCCESS;
uint32_t keyaddr = (uint32_t)Key;
uint32_t inputaddr = (uint32_t)Input;
uint32_t outputaddr = (uint32_t)Output;
uint32_t ivaddr = (uint32_t)InitVectors;
__IO uint32_t counter = 0;
uint32_t ccstatus = 0;
uint32_t i = 0;
/* AES Key initialisation*/
AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
keyaddr += 4;
AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
keyaddr += 4;
AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
keyaddr += 4;
AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
AES_KeyInit(&AES_KeyInitStructure);
/* AES Initialization Vectors */
AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));
ivaddr += 4;
AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));
ivaddr += 4;
AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));
ivaddr += 4;
AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));
AES_IVInit(&AES_IVInitStructure);
/* AES configuration */
AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;
AES_InitStructure.AES_Chaining = AES_Chaining_CTR;
AES_InitStructure.AES_DataType = AES_DataType_8b;
AES_Init(&AES_InitStructure);
/* Enable AES */
AES_Cmd(ENABLE);
for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
{
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
AES_WriteSubData(*(uint32_t*)(inputaddr));
inputaddr += 4;
/* Wait for CCF flag to be set */
counter = 0;
do
{
ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
counter++;
}while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
if (ccstatus == RESET)
{
status = ERROR;
}
else
{
/* Clear CCF flag */
AES_ClearFlag(AES_FLAG_CCF);
/* Read cipher text */
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
*(uint32_t*)(outputaddr) = AES_ReadSubData();
outputaddr += 4;
}
}
/* Disable AES before starting new processing */
AES_Cmd(DISABLE);
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

378
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_comp.c
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@ -1,378 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_comp.c
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the comparators (COMP1 and COMP2) peripheral:
* + Comparators configuration
* + Window mode control
* + Internal Reference Voltage (VREFINT) output
*
* @verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..] The device integrates two analog comparators COMP1 and COMP2:
(+) COMP1 is a fixed threshold (VREFINT) that shares the non inverting
input with the ADC channels.
(+) COMP2 is a rail-to-rail comparator whose the inverting input can be
selected among: DAC_OUT1, DAC_OUT2, 1/4 VREFINT, 1/2 VERFINT, 3/4
VREFINT, VREFINT, PB3 and whose the output can be redirected to
embedded timers: TIM2, TIM3, TIM4, TIM10.
(+) The two comparators COMP1 and COMP2 can be combined in window mode.
-@-
(#@) Comparator APB clock must be enabled to get write access
to comparator register using
RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE).
(#@) COMP1 comparator and ADC can't be used at the same time since
they share the same ADC switch matrix (analog switches).
(#@) When an I/O is used as comparator input, the corresponding GPIO
registers should be configured in analog mode.
(#@) Comparators outputs (CMP1OUT and CMP2OUT) are not mapped on
GPIO pin. They are only internal.
To get the comparator output level, use COMP_GetOutputLevel().
(#@) COMP1 and COMP2 outputs are internally connected to EXTI Line 21
and EXTI Line 22 respectively.
Interrupts can be used by configuring the EXTI Line using the
EXTI peripheral driver.
(#@) After enabling the comparator (COMP1 or COMP2), user should wait
for start-up time (tSTART) to get right output levels.
Please refer to product datasheet for more information on tSTART.
(#@) Comparators cannot be used to exit the device from Sleep or Stop
mode when the internal reference voltage is switched off using
the PWR_UltraLowPowerCmd() function (ULP bit in the PWR_CR register).
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_comp.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @defgroup COMP
* @brief COMP driver modules.
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup COMP_Private_Functions
* @{
*/
/** @defgroup COMP_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions.
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes COMP peripheral registers to their default reset values.
* @param None
* @retval None
*/
void COMP_DeInit(void)
{
COMP->CSR = ((uint32_t)0x00000000); /*!< Set COMP->CSR to reset value */
}
/**
* @brief Initializes the COMP2 peripheral according to the specified parameters
* in the COMP_InitStruct.
* @note This function configures only COMP2.
* @note COMP2 comparator is enabled as soon as the INSEL[2:0] bits are
* different from "000".
* @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains
* the configuration information for the specified COMP peripheral.
* @retval None
*/
void COMP_Init(COMP_InitTypeDef* COMP_InitStruct)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));
assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_OutputSelect));
assert_param(IS_COMP_SPEED(COMP_InitStruct->COMP_Speed));
/*!< Get the COMP CSR value */
tmpreg = COMP->CSR;
/*!< Clear the INSEL[2:0], OUTSEL[1:0] and SPEED bits */
tmpreg &= (uint32_t) (~(uint32_t) (COMP_CSR_OUTSEL | COMP_CSR_INSEL | COMP_CSR_SPEED));
/*!< Configure COMP: speed, inversion input selection and output redirection */
/*!< Set SPEED bit according to COMP_InitStruct->COMP_Speed value */
/*!< Set INSEL bits according to COMP_InitStruct->COMP_InvertingInput value */
/*!< Set OUTSEL bits according to COMP_InitStruct->COMP_OutputSelect value */
tmpreg |= (uint32_t)((COMP_InitStruct->COMP_Speed | COMP_InitStruct->COMP_InvertingInput
| COMP_InitStruct->COMP_OutputSelect));
/*!< The COMP2 comparator is enabled as soon as the INSEL[2:0] bits value are
different from "000" */
/*!< Write to COMP_CSR register */
COMP->CSR = tmpreg;
}
/**
* @brief Enable or disable the COMP1 peripheral.
* @note After enabling COMP1, the following functions should be called to
* connect the selected GPIO input to COMP1 non inverting input:
* @note Enable switch control mode using SYSCFG_RISwitchControlModeCmd()
* @note Close VCOMP switch using SYSCFG_RIIOSwitchConfig()
* @note Close the I/O switch number n corresponding to the I/O
* using SYSCFG_RIIOSwitchConfig()
* @param NewState: new state of the COMP1 peripheral.
* This parameter can be: ENABLE or DISABLE.
* @note This function enables/disables only the COMP1.
* @retval None
*/
void COMP_Cmd(FunctionalState NewState)
{
/* Check the parameter */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the COMP1 */
COMP->CSR |= (uint32_t) COMP_CSR_CMP1EN;
}
else
{
/* Disable the COMP1 */
COMP->CSR &= (uint32_t)(~COMP_CSR_CMP1EN);
}
}
/**
* @brief Return the output level (high or low) of the selected comparator.
* @note Comparator output is low when the noninverting input is at a lower
* voltage than the inverting input.
* @note Comparator output is high when the noninverting input is at a higher
* voltage than the inverting input.
* @note Comparators outputs aren't available on GPIO (outputs levels are
* only internal). The COMP1 and COMP2 outputs are connected internally
* to the EXTI Line 21 and Line 22 respectively.
* @param COMP_Selection: the selected comparator.
* This parameter can be one of the following values:
* @arg COMP_Selection_COMP1: COMP1 selected
* @arg COMP_Selection_COMP2: COMP2 selected
* @retval Returns the selected comparator output level.
*/
uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection)
{
uint8_t compout = 0x0;
/* Check the parameters */
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
/* Check if Comparator 1 is selected */
if(COMP_Selection == COMP_Selection_COMP1)
{
/* Check if comparator 1 output level is high */
if((COMP->CSR & COMP_CSR_CMP1OUT) != (uint8_t) RESET)
{
/* Get Comparator 1 output level */
compout = (uint8_t) COMP_OutputLevel_High;
}
/* comparator 1 output level is low */
else
{
/* Get Comparator 1 output level */
compout = (uint8_t) COMP_OutputLevel_Low;
}
}
/* Comparator 2 is selected */
else
{
/* Check if comparator 2 output level is high */
if((COMP->CSR & COMP_CSR_CMP2OUT) != (uint8_t) RESET)
{
/* Get Comparator output level */
compout = (uint8_t) COMP_OutputLevel_High;
}
/* comparator 2 output level is low */
else
{
/* Get Comparator 2 output level */
compout = (uint8_t) COMP_OutputLevel_Low;
}
}
/* Return the comparator output level */
return (uint8_t)(compout);
}
/**
* @brief Close or Open the SW1 switch.
* @param NewState: new state of the SW1 switch.
* This parameter can be: ENABLE or DISABLE.
* @note ENABLE to close the SW1 switch
* @note DISABLE to open the SW1 switch
* @retval None.
*/
void COMP_SW1SwitchConfig(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Close SW1 switch */
COMP->CSR |= (uint32_t) COMP_CSR_SW1;
}
else
{
/* Open SW1 switch */
COMP->CSR &= (uint32_t)(~COMP_CSR_SW1);
}
}
/**
* @}
*/
/** @defgroup COMP_Group2 Window mode control function
* @brief Window mode control function.
*
@verbatim
===============================================================================
##### Window mode control function #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the window mode.
* In window mode:
* @note COMP1 inverting input is fixed to VREFINT defining the first
* threshold.
* @note COMP2 inverting input is configurable (DAC_OUT1, DAC_OUT2, VREFINT
* sub-multiples, PB3) defining the second threshold.
* @note COMP1 and COMP2 non inverting inputs are connected together.
* @note In window mode, only the Group 6 (PB4 or PB5) can be used as
* noninverting inputs.
* @param NewState: new state of the window mode.
* This parameter can be ENABLE or DISABLE.
* @retval None
*/
void COMP_WindowCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the window mode */
COMP->CSR |= (uint32_t) COMP_CSR_WNDWE;
}
else
{
/* Disable the window mode */
COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWE);
}
}
/**
* @}
*/
/** @defgroup COMP_Group3 Internal Reference Voltage output function
* @brief Internal Reference Voltage (VREFINT) output function.
*
@verbatim
===============================================================================
##### Internal Reference Voltage (VREFINT) output function #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the output of internal reference voltage (VREFINT).
* The VREFINT output can be routed to any I/O in group 3: CH8 (PB0) or
* CH9 (PB1).
* To correctly use this function, the SYSCFG_RIIOSwitchConfig() function
* should be called after.
* @param NewState: new state of the Vrefint output.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void COMP_VrefintOutputCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the output of internal reference voltage */
COMP->CSR |= (uint32_t) COMP_CSR_VREFOUTEN;
}
else
{
/* Disable the output of internal reference voltage */
COMP->CSR &= (uint32_t) (~COMP_CSR_VREFOUTEN);
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

133
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_crc.c
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@ -1,133 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_crc.c
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file provides all the CRC firmware functions.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_crc.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @defgroup CRC
* @brief CRC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CRC_Private_Functions
* @{
*/
/**
* @brief Resets the CRC Data register (DR).
* @param None
* @retval None
*/
void CRC_ResetDR(void)
{
/* Reset CRC generator */
CRC->CR = CRC_CR_RESET;
}
/**
* @brief Computes the 32-bit CRC of a given data word(32-bit).
* @param Data: data word(32-bit) to compute its CRC.
* @retval 32-bit CRC
*/
uint32_t CRC_CalcCRC(uint32_t Data)
{
CRC->DR = Data;
return (CRC->DR);
}
/**
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
* @param pBuffer: pointer to the buffer containing the data to be computed.
* @param BufferLength: length of the buffer to be computed
* @retval 32-bit CRC
*/
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index = 0;
for(index = 0; index < BufferLength; index++)
{
CRC->DR = pBuffer[index];
}
return (CRC->DR);
}
/**
* @brief Returns the current CRC value.
* @param None
* @retval 32-bit CRC
*/
uint32_t CRC_GetCRC(void)
{
return (CRC->DR);
}
/**
* @brief Stores a 8-bit data in the Independent Data(ID) register.
* @param IDValue: 8-bit value to be stored in the ID register
* @retval None
*/
void CRC_SetIDRegister(uint8_t IDValue)
{
CRC->IDR = IDValue;
}
/**
* @brief Returns the 8-bit data stored in the Independent Data(ID) register.
* @param None
* @retval 8-bit value of the ID register
*/
uint8_t CRC_GetIDRegister(void)
{
return (CRC->IDR);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

687
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dac.c
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@ -1,687 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_dac.c
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the Digital-to-Analog Converter (DAC) peripheral:
* + DAC channels configuration: trigger, output buffer, data format
* + DMA management
* + Interrupts and flags management
* @verbatim
*
===============================================================================
##### DAC Peripheral features #####
===============================================================================
[..] The device integrates two 12-bit Digital Analog Converters that can
be used independently or simultaneously (dual mode):
(#) DAC channel1 with DAC_OUT1 (PA4) as output.
(#) DAC channel2 with DAC_OUT2 (PA5) as output.
[..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None
and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using
DAC_SetChannel1Data()/DAC_SetChannel2Data.
[..] Digital to Analog conversion can be triggered by:
(#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
The used pin (GPIOx_Pin9) must be configured in input mode.
(#) Timers TRGO: TIM2, TIM4, TIM6, TIM7 and TIM9
(DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...).
The timer TRGO event should be selected using TIM_SelectOutputTrigger()
(#) Software using DAC_Trigger_Software.
[..] Each DAC channel integrates an output buffer that can be used to
reduce the output impedance, and to drive external loads directly
without having to add an external operational amplifier.
To enable, the output buffer use
DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
[..] Refer to the device datasheet for more details about output impedance
value with and without output buffer.
[..] Both DAC channels can be used to generate:
(#) Noise wave using DAC_WaveGeneration_Noise
(#) Triangle wave using DAC_WaveGeneration_Triangle
[..] Wave generation can be disabled using DAC_WaveGeneration_None.
[..] The DAC data format can be:
(#) 8-bit right alignment using DAC_Align_8b_R
(#) 12-bit left alignment using DAC_Align_12b_L
(#) 12-bit right alignment using DAC_Align_12b_R
[..] The analog output voltage on each DAC channel pin is determined
by the following equation: DAC_OUTx = VREF+ * DOR / 4095
with DOR is the Data Output Register.
VEF+ is the input voltage reference (refer to the device datasheet)
e.g. To set DAC_OUT1 to 0.7V, use
DAC_SetChannel1Data(DAC_Align_12b_R, 868);
Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V.
[..] A DMA1 request can be generated when an external trigger (but not
a software trigger) occurs if DMA1 requests are enabled using
DAC_DMACmd()
[..] DMA1 requests are mapped as following:
(#) DAC channel1 is mapped on DMA1 channel3 which must be already
configured.
(#) DAC channel2 is mapped on DMA1 channel4 which must be already
configured.
##### How to use this driver #####
===============================================================================
[..]
(+) DAC APB clock must be enabled to get write access to DAC registers using
RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
(+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
(+) Configure the DAC channel using DAC_Init()
(+) Enable the DAC channel using DAC_Cmd()
@endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_dac.h"
#include "stm32l1xx_rcc.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @defgroup DAC
* @brief DAC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* CR register Mask */
#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
/* DAC Dual Channels SWTRIG masks */
#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
/* DHR registers offsets */
#define DHR12R1_OFFSET ((uint32_t)0x00000008)
#define DHR12R2_OFFSET ((uint32_t)0x00000014)
#define DHR12RD_OFFSET ((uint32_t)0x00000020)
/* DOR register offset */
#define DOR_OFFSET ((uint32_t)0x0000002C)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DAC_Private_Functions
* @{
*/
/** @defgroup DAC_Group1 DAC channels configuration
* @brief DAC channels configuration: trigger, output buffer, data format.
*
@verbatim
===============================================================================
##### DAC channels configuration: trigger, output buffer, data format #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the DAC peripheral registers to their default reset values.
* @param None
* @retval None
*/
void DAC_DeInit(void)
{
/* Enable DAC reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
/* Release DAC from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
}
/**
* @brief Initializes the DAC peripheral according to the specified
* parameters in the DAC_InitStruct.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected.
* @arg DAC_Channel_2: DAC Channel2 selected.
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
* contains the configuration information for the specified DAC channel.
* @retval None
*/
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
{
uint32_t tmpreg1 = 0, tmpreg2 = 0;
/* Check the DAC parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
/*---------------------------- DAC CR Configuration --------------------------*/
/* Get the DAC CR value */
tmpreg1 = DAC->CR;
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
/* Configure for the selected DAC channel: buffer output, trigger, wave generation,
mask/amplitude for wave generation */
/* Set TSELx and TENx bits according to DAC_Trigger value */
/* Set WAVEx bits according to DAC_WaveGeneration value */
/* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
/* Set BOFFx bit according to DAC_OutputBuffer value */
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << DAC_Channel;
/* Write to DAC CR */
DAC->CR = tmpreg1;
}
/**
* @brief Fills each DAC_InitStruct member with its default value.
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
{
/*--------------- Reset DAC init structure parameters values -----------------*/
/* Initialize the DAC_Trigger member */
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
/* Initialize the DAC_WaveGeneration member */
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
/* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
/* Initialize the DAC_OutputBuffer member */
DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
}
/**
* @brief Enables or disables the specified DAC channel.
* @param DAC_Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the DAC channel.
* This parameter can be: ENABLE or DISABLE.
* @note When the DAC channel is enabled the trigger source can no more
* be modified.
* @retval None
*/
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DAC channel */
DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
}
else
{
/* Disable the selected DAC channel */
DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
}
}
/**
* @brief Enables or disables the selected DAC channel software trigger.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the selected DAC channel software trigger.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable software trigger for the selected DAC channel */
DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
}
else
{
/* Disable software trigger for the selected DAC channel */
DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
}
}
/**
* @brief Enables or disables simultaneously the two DAC channels software
* triggers.
* @param NewState: new state of the DAC channels software triggers.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable software trigger for both DAC channels */
DAC->SWTRIGR |= DUAL_SWTRIG_SET;
}
else
{
/* Disable software trigger for both DAC channels */
DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
}
}
/**
* @brief Enables or disables the selected DAC channel wave generation.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_Wave: Specifies the wave type to enable or disable.
* This parameter can be one of the following values:
* @arg DAC_Wave_Noise: noise wave generation
* @arg DAC_Wave_Triangle: triangle wave generation
* @param NewState: new state of the selected DAC channel wave generation.
* This parameter can be: ENABLE or DISABLE.
* @note
* @retval None
*/
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_WAVE(DAC_Wave));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected wave generation for the selected DAC channel */
DAC->CR |= DAC_Wave << DAC_Channel;
}
else
{
/* Disable the selected wave generation for the selected DAC channel */
DAC->CR &= ~(DAC_Wave << DAC_Channel);
}
}
/**
* @brief Set the specified data holding register value for DAC channel1.
* @param DAC_Align: Specifies the data alignment for DAC channel1.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignment selected
* @arg DAC_Align_12b_L: 12bit left data alignment selected
* @arg DAC_Align_12b_R: 12bit right data alignment selected
* @param Data : Data to be loaded in the selected data holding register.
* @retval None
*/
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data));
tmp = (uint32_t)DAC_BASE;
tmp += DHR12R1_OFFSET + DAC_Align;
/* Set the DAC channel1 selected data holding register */
*(__IO uint32_t *) tmp = Data;
}
/**
* @brief Set the specified data holding register value for DAC channel2.
* @param DAC_Align: Specifies the data alignment for DAC channel2.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignment selected
* @arg DAC_Align_12b_L: 12bit left data alignment selected
* @arg DAC_Align_12b_R: 12bit right data alignment selected
* @param Data : Data to be loaded in the selected data holding register.
* @retval None
*/
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data));
tmp = (uint32_t)DAC_BASE;
tmp += DHR12R2_OFFSET + DAC_Align;
/* Set the DAC channel2 selected data holding register */
*(__IO uint32_t *)tmp = Data;
}
/**
* @brief Set the specified data holding register value for dual channel DAC.
* @param DAC_Align: Specifies the data alignment for dual channel DAC.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignment selected
* @arg DAC_Align_12b_L: 12bit left data alignment selected
* @arg DAC_Align_12b_R: 12bit right data alignment selected
* @param Data2: Data for DAC Channel2 to be loaded in the selected data
* holding register.
* @param Data1: Data for DAC Channel1 to be loaded in the selected data
* holding register.
* @note In dual mode, a unique register access is required to write in both
* DAC channels at the same time.
* @retval None
*/
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
{
uint32_t data = 0, tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
assert_param(IS_DAC_DATA(Data1));
assert_param(IS_DAC_DATA(Data2));
/* Calculate and set dual DAC data holding register value */
if (DAC_Align == DAC_Align_8b_R)
{
data = ((uint32_t)Data2 << 8) | Data1;
}
else
{
data = ((uint32_t)Data2 << 16) | Data1;
}
tmp = (uint32_t)DAC_BASE;
tmp += DHR12RD_OFFSET + DAC_Align;
/* Set the dual DAC selected data holding register */
*(__IO uint32_t *)tmp = data;
}
/**
* @brief Returns the last data output value of the selected DAC channel.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @retval The selected DAC channel data output value.
*/
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
tmp = (uint32_t) DAC_BASE ;
tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
/* Returns the DAC channel data output register value */
return (uint16_t) (*(__IO uint32_t*) tmp);
}
/**
* @}
*/
/** @defgroup DAC_Group2 DMA management functions
* @brief DMA management functions
*
@verbatim
===============================================================================
##### DMA management functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified DAC channel DMA request.
* When enabled DMA1 is generated when an external trigger (EXTI Line9,
* TIM2, TIM4, TIM6, TIM7 or TIM9 but not a software trigger) occurs.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the selected DAC channel DMA request.
* This parameter can be: ENABLE or DISABLE.
* @note The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which
* must be already configured.
* @retval None
*/
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DAC channel DMA request */
DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
}
else
{
/* Disable the selected DAC channel DMA request */
DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
}
}
/**
* @}
*/
/** @defgroup DAC_Group3 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
##### Interrupts and flags management functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified DAC interrupts.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
* This parameter can be the following value:
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
* @note The DMA underrun occurs when a second external trigger arrives before
* the acknowledgement for the first external trigger is received (first request).
* @param NewState: new state of the specified DAC interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_DAC_IT(DAC_IT));
if (NewState != DISABLE)
{
/* Enable the selected DAC interrupts */
DAC->CR |= (DAC_IT << DAC_Channel);
}
else
{
/* Disable the selected DAC interrupts */
DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
}
}
/**
* @brief Checks whether the specified DAC flag is set or not.
* @param DAC_Channel: thee selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_FLAG: specifies the flag to check.
* This parameter can be only of the following value:
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
* @note The DMA underrun occurs when a second external trigger arrives before
* the acknowledgement for the first external trigger is received (first request).
* @retval The new state of DAC_FLAG (SET or RESET).
*/
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_FLAG(DAC_FLAG));
/* Check the status of the specified DAC flag */
if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
{
/* DAC_FLAG is set */
bitstatus = SET;
}
else
{
/* DAC_FLAG is reset */
bitstatus = RESET;
}
/* Return the DAC_FLAG status */
return bitstatus;
}
/**
* @brief Clears the DAC channel's pending flags.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_FLAG: specifies the flag to clear.
* This parameter can be the following value:
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
* @retval None
*/
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_FLAG(DAC_FLAG));
/* Clear the selected DAC flags */
DAC->SR = (DAC_FLAG << DAC_Channel);
}
/**
* @brief Checks whether the specified DAC interrupt has occurred or not.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_IT: specifies the DAC interrupt source to check.
* This parameter can be the following values:
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
* @note The DMA underrun occurs when a second external trigger arrives before
* the acknowledgement for the first external trigger is received (first request).
* @retval The new state of DAC_IT (SET or RESET).
*/
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_IT(DAC_IT));
/* Get the DAC_IT enable bit status */
enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
/* Check the status of the specified DAC interrupt */
if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
{
/* DAC_IT is set */
bitstatus = SET;
}
else
{
/* DAC_IT is reset */
bitstatus = RESET;
}
/* Return the DAC_IT status */
return bitstatus;
}
/**
* @brief Clears the DAC channel's interrupt pending bits.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_IT: specifies the DAC interrupt pending bit to clear.
* This parameter can be the following values:
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
* @retval None
*/
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_IT(DAC_IT));
/* Clear the selected DAC interrupt pending bits */
DAC->SR = (DAC_IT << DAC_Channel);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dbgmcu.c
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@ -1,181 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_dbgmcu.c
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file provides all the DBGMCU firmware functions.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_dbgmcu.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @defgroup DBGMCU
* @brief DBGMCU driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DBGMCU_Private_Functions
* @{
*/
/**
* @brief Returns the device revision identifier.
* @param None
* @retval Device revision identifier
*/
uint32_t DBGMCU_GetREVID(void)
{
return(DBGMCU->IDCODE >> 16);
}
/**
* @brief Returns the device identifier.
* @param None
* @retval Device identifier
*/
uint32_t DBGMCU_GetDEVID(void)
{
return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
}
/**
* @brief Configures low power mode behavior when the MCU is in Debug mode.
* @param DBGMCU_Periph: specifies the low power mode.
* This parameter can be any combination of the following values:
* @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
* @arg DBGMCU_STOP: Keep debugger connection during STOP mode
* @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
* @param NewState: new state of the specified low power mode in Debug mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
DBGMCU->CR |= DBGMCU_Periph;
}
else
{
DBGMCU->CR &= ~DBGMCU_Periph;
}
}
/**
* @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
* @param DBGMCU_Periph: specifies the APB1 peripheral.
* This parameter can be any combination of the following values:
* @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
* @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
* @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
* @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
* @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
* @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
* @arg DBGMCU_RTC_STOP:
* + On STM32L1xx Medium-density devices: RTC Wakeup counter stopped when
* Core is halted.
* + On STM32L1xx High-density and Medium-density Plus devices: RTC Calendar
* and Wakeup counter stopped when Core is halted.
* @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
* @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
* @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is
* halted
* @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is
* halted
* @param NewState: new state of the specified APB1 peripheral in Debug mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
DBGMCU->APB1FZ |= DBGMCU_Periph;
}
else
{
DBGMCU->APB1FZ &= ~DBGMCU_Periph;
}
}
/**
* @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.
* @param DBGMCU_Periph: specifies the APB2 peripheral.
* This parameter can be any combination of the following values:
* @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
* @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
* @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
* @param NewState: new state of the specified APB2 peripheral in Debug mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
DBGMCU->APB2FZ |= DBGMCU_Periph;
}
else
{
DBGMCU->APB2FZ &= ~DBGMCU_Periph;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

866
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_dma.c
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@ -1,866 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_dma.c
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the Direct Memory Access controller (DMA):
* + Initialization and Configuration
* + Data Counter
* + Interrupts and flags management
*
* @verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) Enable The DMA controller clock using
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1 or
using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE) function for DMA2.
(#) Enable and configure the peripheral to be connected to the DMA channel
(except for internal SRAM / FLASH memories: no initialization is
necessary).
(#) For a given Channel, program the Source and Destination addresses,
the transfer Direction, the Buffer Size, the Peripheral and Memory
Incrementation mode and Data Size, the Circular or Normal mode,
the channel transfer Priority and the Memory-to-Memory transfer
mode (if needed) using the DMA_Init() function.
(#) Enable the NVIC and the corresponding interrupt(s) using the function
DMA_ITConfig() if you need to use DMA interrupts.
(#) Enable the DMA channel using the DMA_Cmd() function.
(#) Activate the needed channel Request using PPP_DMACmd() function for
any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
The function allowing this operation is provided in each PPP peripheral
driver (ie. SPI_DMACmd for SPI peripheral).
(#) Optionally, you can configure the number of data to be transferred
when the channel is disabled (ie. after each Transfer Complete event
or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
And you can get the number of remaining data to be transferred using
the function DMA_GetCurrDataCounter() at run time (when the DMA channel is
enabled and running).
(#) To control DMA events you can use one of the following two methods:
(##) Check on DMA channel flags using the function DMA_GetFlagStatus().
(##) Use DMA interrupts through the function DMA_ITConfig() at initialization
phase and DMA_GetITStatus() function into interrupt routines in
communication phase.
After checking on a flag you should clear it using DMA_ClearFlag()
function. And after checking on an interrupt event you should
clear it using DMA_ClearITPendingBit() function.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_dma.h"
#include "stm32l1xx_rcc.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @defgroup DMA
* @brief DMA driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* DMA1 Channelx interrupt pending bit masks */
#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
/* DMA2 Channelx interrupt pending bit masks */
#define DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
#define DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
#define DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
#define DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
#define DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
/* DMA FLAG mask */
#define FLAG_MASK ((uint32_t)0x10000000)
/* DMA registers Masks */
#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DMA_Private_Functions
* @{
*/
/** @defgroup DMA_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This subsection provides functions allowing to initialize the DMA channel
source and destination addresses, incrementation and data sizes, transfer
direction, buffer size, circular/normal mode selection, memory-to-memory
mode selection and channel priority value.
[..] The DMA_Init() function follows the DMA configuration procedures as described
in reference manual (RM0038).
@endverbatim
* @{
*/
/**
* @brief Deinitializes the DMAy Channelx registers to their default reset
* values.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @retval None
*/
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
/* Disable the selected DMAy Channelx */
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
/* Reset DMAy Channelx control register */
DMAy_Channelx->CCR = 0;
/* Reset DMAy Channelx remaining bytes register */
DMAy_Channelx->CNDTR = 0;
/* Reset DMAy Channelx peripheral address register */
DMAy_Channelx->CPAR = 0;
/* Reset DMAy Channelx memory address register */
DMAy_Channelx->CMAR = 0;
if (DMAy_Channelx == DMA1_Channel1)
{
/* Reset interrupt pending bits for DMA1 Channel1 */
DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
}
else if (DMAy_Channelx == DMA1_Channel2)
{
/* Reset interrupt pending bits for DMA1 Channel2 */
DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
}
else if (DMAy_Channelx == DMA1_Channel3)
{
/* Reset interrupt pending bits for DMA1 Channel3 */
DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
}
else if (DMAy_Channelx == DMA1_Channel4)
{
/* Reset interrupt pending bits for DMA1 Channel4 */
DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
}
else if (DMAy_Channelx == DMA1_Channel5)
{
/* Reset interrupt pending bits for DMA1 Channel5 */
DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
}
else if (DMAy_Channelx == DMA1_Channel6)
{
/* Reset interrupt pending bits for DMA1 Channel6 */
DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;
}
else if (DMAy_Channelx == DMA1_Channel7)
{
/* Reset interrupt pending bits for DMA1 Channel7 */
DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;
}
else if (DMAy_Channelx == DMA2_Channel1)
{
/* Reset interrupt pending bits for DMA2 Channel1 */
DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK;
}
else if (DMAy_Channelx == DMA2_Channel2)
{
/* Reset interrupt pending bits for DMA2 Channel2 */
DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK;
}
else if (DMAy_Channelx == DMA2_Channel3)
{
/* Reset interrupt pending bits for DMA2 Channel3 */
DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK;
}
else if (DMAy_Channelx == DMA2_Channel4)
{
/* Reset interrupt pending bits for DMA2 Channel4 */
DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK;
}
else
{
if (DMAy_Channelx == DMA2_Channel5)
{
/* Reset interrupt pending bits for DMA2 Channel5 */
DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK;
}
}
}
/**
* @brief Initializes the DMAy Channelx according to the specified
* parameters in the DMA_InitStruct.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
* contains the configuration information for the specified DMA Channel.
* @retval None
*/
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
/* Get the DMAy_Channelx CCR value */
tmpreg = DMAy_Channelx->CCR;
/* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
tmpreg &= CCR_CLEAR_MASK;
/* Configure DMAy Channelx: data transfer, data size, priority level and mode */
/* Set DIR bit according to DMA_DIR value */
/* Set CIRC bit according to DMA_Mode value */
/* Set PINC bit according to DMA_PeripheralInc value */
/* Set MINC bit according to DMA_MemoryInc value */
/* Set PSIZE bits according to DMA_PeripheralDataSize value */
/* Set MSIZE bits according to DMA_MemoryDataSize value */
/* Set PL bits according to DMA_Priority value */
/* Set the MEM2MEM bit according to DMA_M2M value */
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
/* Write to DMAy Channelx CCR */
DMAy_Channelx->CCR = tmpreg;
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
/* Write to DMAy Channelx CNDTR */
DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
/* Write to DMAy Channelx CPAR */
DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
/* Write to DMAy Channelx CMAR */
DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
}
/**
* @brief Fills each DMA_InitStruct member with its default value.
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
{
/*-------------- Reset DMA init structure parameters values ------------------*/
/* Initialize the DMA_PeripheralBaseAddr member */
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
/* Initialize the DMA_MemoryBaseAddr member */
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
/* Initialize the DMA_DIR member */
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
/* Initialize the DMA_BufferSize member */
DMA_InitStruct->DMA_BufferSize = 0;
/* Initialize the DMA_PeripheralInc member */
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
/* Initialize the DMA_MemoryInc member */
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
/* Initialize the DMA_PeripheralDataSize member */
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
/* Initialize the DMA_MemoryDataSize member */
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
/* Initialize the DMA_Mode member */
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
/* Initialize the DMA_Priority member */
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
/* Initialize the DMA_M2M member */
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
}
/**
* @brief Enables or disables the specified DMAy Channelx.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param NewState: new state of the DMAy Channelx.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMAy Channelx */
DMAy_Channelx->CCR |= DMA_CCR1_EN;
}
else
{
/* Disable the selected DMAy Channelx */
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
}
}
/**
* @}
*/
/** @defgroup DMA_Group2 Data Counter functions
* @brief Data Counter functions
*
@verbatim
===============================================================================
##### Data Counter functions #####
===============================================================================
[..] This subsection provides function allowing to configure and read the buffer
size (number of data to be transferred).The DMA data counter can be written
only when the DMA channel is disabled (ie. after transfer complete event).
[..] The following function can be used to write the Channel data counter value:
(+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t
DataNumber).
-@- It is advised to use this function rather than DMA_Init() in situations
where only the Data buffer needs to be reloaded.
[..] The DMA data counter can be read to indicate the number of remaining transfers
for the relative DMA channel. This counter is decremented at the end of each
data transfer and when the transfer is complete:
(+) If Normal mode is selected: the counter is set to 0.
(+) If Circular mode is selected: the counter is reloaded with the initial
value(configured before enabling the DMA channel).
[..] The following function can be used to read the Channel data counter value:
(+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).
@endverbatim
* @{
*/
/**
* @brief Sets the number of data units in the current DMAy Channelx transfer.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param DataNumber: The number of data units in the current DMAy Channelx
* transfer.
* @note This function can only be used when the DMAy_Channelx is disabled.
* @retval None.
*/
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
/* Write to DMAy Channelx CNDTR */
DMAy_Channelx->CNDTR = DataNumber;
}
/**
* @brief Returns the number of remaining data units in the current
* DMAy Channelx transfer.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @retval The number of remaining data units in the current DMAy Channelx
* transfer.
*/
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
/* Return the number of remaining data units for DMAy Channelx */
return ((uint16_t)(DMAy_Channelx->CNDTR));
}
/**
* @}
*/
/** @defgroup DMA_Group3 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
##### Interrupts and flags management functions #####
===============================================================================
[..] This subsection provides functions allowing to configure the DMA Interrupts
sources and check or clear the flags or pending bits status.
The user should identify which mode will be used in his application to manage
the DMA controller events: Polling mode or Interrupt mode.
*** Polling Mode ***
====================
[..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller
number x : DMA channel number ).
(#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.
(#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.
(#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.
(#) DMAy_FLAG_GLx : to indicate that at least one of the events described
above occurred.
-@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the
same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
[..]In this Mode it is advised to use the following functions:
(+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
(+) void DMA_ClearFlag(uint32_t DMA_FLAG);
*** Interrupt Mode ***
======================
[..] Each DMA channel can be managed through 4 Interrupts:
(+) Interrupt Source
(##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete
event.
(##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete
event.
(##) DMA_IT_TE : specifies the interrupt source for the transfer errors event.
(##) DMA_IT_GL : to indicate that at least one of the interrupts described
above occurred.
-@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of
the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
[..]In this Mode it is advised to use the following functions:
(+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT,
FunctionalState NewState);
(+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);
(+) void DMA_ClearITPendingBit(uint32_t DMA_IT);
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified DMAy Channelx interrupts.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param DMA_IT: specifies the DMA interrupts sources to be enabled
* or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @param NewState: new state of the specified DMA interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
assert_param(IS_DMA_CONFIG_IT(DMA_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMA interrupts */
DMAy_Channelx->CCR |= DMA_IT;
}
else
{
/* Disable the selected DMA interrupts */
DMAy_Channelx->CCR &= ~DMA_IT;
}
}
/**
* @brief Checks whether the specified DMAy Channelx flag is set or not.
* @param DMAy_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
*
* @note
* The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags
* relative to the same channel is set (Transfer Complete, Half-transfer
* Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or
* DMAy_FLAG_TEx).
*
* @retval The new state of DMAy_FLAG (SET or RESET).
*/
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
{
FlagStatus bitstatus = RESET;
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
/* Calculate the used DMAy */
if ((DMAy_FLAG & FLAG_MASK) == (uint32_t)RESET)
{
/* Get DMA1 ISR register value */
tmpreg = DMA1->ISR;
}
else
{
/* Get DMA2 ISR register value */
tmpreg = DMA2->ISR;
}
/* Check the status of the specified DMAy flag */
if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
{
/* DMAy_FLAG is set */
bitstatus = SET;
}
else
{
/* DMAy_FLAG is reset */
bitstatus = RESET;
}
/* Return the DMAy_FLAG status */
return bitstatus;
}
/**
* @brief Clears the DMAy Channelx's pending flags.
* @param DMAy_FLAG: specifies the flag to clear.
* This parameter can be any combination (for the same DMA) of the following values:
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
*
* @note
* Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
* relative to the same channel (Transfer Complete, Half-transfer Complete and
* Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
*
* @retval None
*/
void DMA_ClearFlag(uint32_t DMAy_FLAG)
{
/* Check the parameters */
assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
if ((DMAy_FLAG & FLAG_MASK) == (uint32_t)RESET)
{
/* Clear the selected DMAy flags */
DMA1->IFCR = DMAy_FLAG;
}
else
{
/* Clear the selected DMAy flags */
DMA2->IFCR = DMAy_FLAG;
}
}
/**
* @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
* @param DMAy_IT: specifies the DMAy interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
*
* @note
* The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other
* interrupts relative to the same channel is set (Transfer Complete,
* Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx,
* DMAy_IT_HTx or DMAy_IT_TEx).
*
* @retval The new state of DMAy_IT (SET or RESET).
*/
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
{
ITStatus bitstatus = RESET;
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_DMA_GET_IT(DMAy_IT));
/* Calculate the used DMAy */
if ((DMAy_IT & FLAG_MASK) == (uint32_t)RESET)
{
/* Get DMA1 ISR register value */
tmpreg = DMA1->ISR;
}
else
{
/* Get DMA2 ISR register value */
tmpreg = DMA2->ISR;
}
/* Check the status of the specified DMAy interrupt */
if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
{
/* DMAy_IT is set */
bitstatus = SET;
}
else
{
/* DMAy_IT is reset */
bitstatus = RESET;
}
/* Return the DMAy_IT status */
return bitstatus;
}
/**
* @brief Clears the DMAy Channelx's interrupt pending bits.
* @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.
* This parameter can be any combination (for the same DMA) of the following values:
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
*
* @note
* Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other
* interrupts relative to the same channel (Transfer Complete, Half-transfer
* Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and
* DMAy_IT_TEx).
*
* @retval None
*/
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
{
/* Check the parameters */
assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
/* Calculate the used DMAy */
if ((DMAy_IT & FLAG_MASK) == (uint32_t)RESET)
{
/* Clear the selected DMAy interrupt pending bits */
DMA1->IFCR = DMAy_IT;
}
else
{
/* Clear the selected DMAy interrupt pending bits */
DMA2->IFCR = DMAy_IT;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_flash.c
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@ -1,553 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_flash_ramfunc.c
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file provides all the Flash firmware functions which should be
* executed from the internal SRAM. This file should be placed in
* internal SRAM.
* Other FLASH memory functions that can be used from the FLASH are
* defined in the "stm32l1xx_flash.c" file.
@verbatim
*** ARM Compiler ***
--------------------
[..] RAM functions are defined using the toolchain options.
Functions that are be executed in RAM should reside in a separate
source module. Using the 'Options for File' dialog you can simply change
the 'Code / Const' area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the
Options for Target' dialog.
*** ICCARM Compiler ***
-----------------------
[..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
*** GNU Compiler ***
--------------------
[..] RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".data")))".
*** TASKING Compiler ***
------------------------
[..] RAM functions are defined using a specific toolchain pragma. This
pragma is defined inside this file.
@endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_flash.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @defgroup FLASH
* @brief FLASH driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static __RAM_FUNC GetStatus(void);
static __RAM_FUNC WaitForLastOperation(uint32_t Timeout);
/* Private functions ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Functions
* @{
*/
/** @addtogroup FLASH_Group1
*
@verbatim
@endverbatim
* @{
*/
#if defined ( __TASKING__ )
#pragma section_code_init on
#endif
/**
* @brief Enable or disable the power down mode during RUN mode.
* @note This function can be used only when the user code is running from Internal SRAM.
* @param NewState: new state of the power down mode during RUN mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
__RAM_FUNC FLASH_RUNPowerDownCmd(FunctionalState NewState)
{
FLASH_Status status = FLASH_COMPLETE;
if (NewState != DISABLE)
{
/* Unlock the RUN_PD bit */
FLASH->PDKEYR = FLASH_PDKEY1;
FLASH->PDKEYR = FLASH_PDKEY2;
/* Set the RUN_PD bit in FLASH_ACR register to put Flash in power down mode */
FLASH->ACR |= (uint32_t)FLASH_ACR_RUN_PD;
if((FLASH->ACR & FLASH_ACR_RUN_PD) != FLASH_ACR_RUN_PD)
{
status = FLASH_ERROR_PROGRAM;
}
}
else
{
/* Clear the RUN_PD bit in FLASH_ACR register to put Flash in idle mode */
FLASH->ACR &= (uint32_t)(~(uint32_t)FLASH_ACR_RUN_PD);
}
/* Return the Write Status */
return status;
}
/**
* @}
*/
/** @addtogroup FLASH_Group2
*
@verbatim
@endverbatim
* @{
*/
/**
* @brief Erases a specified 2 page in program memory in parallel.
* @note This function can be used only for STM32L1XX_HD density devices.
* To correctly run this function, the FLASH_Unlock() function
* must be called before.
* Call the FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation).
* @param Page_Address1: The page address in program memory to be erased in
* the first Bank (BANK1). This parameter should be between 0x08000000
* and 0x0802FF00.
* @param Page_Address2: The page address in program memory to be erased in
* the second Bank (BANK2). This parameter should be between 0x08030000
* and 0x0805FF00.
* @note A Page is erased in the Program memory only if the address to load
* is the start address of a page (multiple of 256 bytes).
* @retval FLASH Status: The returned value can be:
* FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2)
{
FLASH_Status status = FLASH_COMPLETE;
/* Wait for last operation to be completed */
status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
if(status == FLASH_COMPLETE)
{
/* If the previous operation is completed, proceed to erase the page */
/* Set the PARALLBANK bit */
FLASH->PECR |= FLASH_PECR_PARALLBANK;
/* Set the ERASE bit */
FLASH->PECR |= FLASH_PECR_ERASE;
/* Set PROG bit */
FLASH->PECR |= FLASH_PECR_PROG;
/* Write 00000000h to the first word of the first program page to erase */
*(__IO uint32_t *)Page_Address1 = 0x00000000;
/* Write 00000000h to the first word of the second program page to erase */
*(__IO uint32_t *)Page_Address2 = 0x00000000;
/* Wait for last operation to be completed */
status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
/* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */
FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);
FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK);
}
/* Return the Erase Status */
return status;
}
/**
* @brief Programs a half page in program memory.
* @param Address: specifies the address to be written.
* @param pBuffer: pointer to the buffer containing the data to be written to
* the half page.
* @note To correctly run this function, the FLASH_Unlock() function
* must be called before.
* Call the FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation)
* @note Half page write is possible only from SRAM.
* @note If there are more than 32 words to write, after 32 words another
* Half Page programming operation starts and has to be finished.
* @note A half page is written to the program memory only if the first
* address to load is the start address of a half page (multiple of 128
* bytes) and the 31 remaining words to load are in the same half page.
* @note During the Program memory half page write all read operations are
* forbidden (this includes DMA read operations and debugger read
* operations such as breakpoints, periodic updates, etc.).
* @note If a PGAERR is set during a Program memory half page write, the
* complete write operation is aborted. Software should then reset the
* FPRG and PROG/DATA bits and restart the write operation from the
* beginning.
* @retval FLASH Status: The returned value can be:
* FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
__RAM_FUNC FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer)
{
uint32_t count = 0;
FLASH_Status status = FLASH_COMPLETE;
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
This bit prevents the interruption of multicycle instructions and therefore
will increase the interrupt latency. of Cortex-M3. */
SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
/* Wait for last operation to be completed */
status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to program the new
half page */
FLASH->PECR |= FLASH_PECR_FPRG;
FLASH->PECR |= FLASH_PECR_PROG;
/* Write one half page directly with 32 different words */
while(count < 32)
{
*(__IO uint32_t*) (Address + (4 * count)) = *(pBuffer++);
count ++;
}
/* Wait for last operation to be completed */
status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
/* if the write operation is completed, disable the PROG and FPRG bits */
FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
}
SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
/* Return the Write Status */
return status;
}
/**
* @brief Programs 2 half page in program memory in parallel.
* @param Address1: specifies the first address to be written in the first bank
* (BANK1). This parameter should be between 0x08000000 and 0x0802FF80.
* @param pBuffer1: pointer to the buffer containing the data to be written
* to the first half page in the first bank.
* @param Address2: specifies the second address to be written in the second bank
* (BANK2). This parameter should be between 0x08030000 and 0x0805FF80.
* @param pBuffer2: pointer to the buffer containing the data to be written
* to the second half page in the second bank.
* @note This function can be used only for STM32L1XX_HD density devices.
* @note To correctly run this function, the FLASH_Unlock() function
* must be called before.
* Call the FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation).
* @note Half page write is possible only from SRAM.
* @note If there are more than 32 words to write, after 32 words another
* Half Page programming operation starts and has to be finished.
* @note A half page is written to the program memory only if the first
* address to load is the start address of a half page (multiple of 128
* bytes) and the 31 remaining words to load are in the same half page.
* @note During the Program memory half page write all read operations are
* forbidden (this includes DMA read operations and debugger read
* operations such as breakpoints, periodic updates, etc.).
* @note If a PGAERR is set during a Program memory half page write, the
* complete write operation is aborted. Software should then reset the
* FPRG and PROG/DATA bits and restart the write operation from the
* beginning.
* @retval FLASH Status: The returned value can be:
* FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
__RAM_FUNC FLASH_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)
{
uint32_t count = 0;
FLASH_Status status = FLASH_COMPLETE;
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
This bit prevents the interruption of multicycle instructions and therefore
will increase the interrupt latency. of Cortex-M3. */
SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
/* Wait for last operation to be completed */
status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
if(status == FLASH_COMPLETE)
{
/* If the previous operation is completed, proceed to program the new
half page */
FLASH->PECR |= FLASH_PECR_PARALLBANK;
FLASH->PECR |= FLASH_PECR_FPRG;
FLASH->PECR |= FLASH_PECR_PROG;
/* Write the first half page directly with 32 different words */
while(count < 32)
{
*(__IO uint32_t*) (Address1 + (4 * count)) = *(pBuffer1++);
count ++;
}
count = 0;
/* Write the second half page directly with 32 different words */
while(count < 32)
{
*(__IO uint32_t*) (Address2 + (4 * count)) = *(pBuffer2++);
count ++;
}
/* Wait for last operation to be completed */
status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
/* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */
FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK);
}
SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
/* Return the Write Status */
return status;
}
/**
* @}
*/
/** @addtogroup FLASH_Group3
*
@verbatim
@endverbatim
* @{
*/
/**
* @brief Erase a double word in data memory.
* @param Address: specifies the address to be erased.
* @note To correctly run this function, the DATA_EEPROM_Unlock() function
* must be called before.
* Call the DATA_EEPROM_Lock() to he data EEPROM access
* and Flash program erase control register access(recommended to protect
* the DATA_EEPROM against possible unwanted operation).
* @note Data memory double word erase is possible only from SRAM.
* @note A double word is erased to the data memory only if the first address
* to load is the start address of a double word (multiple of 8 bytes).
* @note During the Data memory double word erase, all read operations are
* forbidden (this includes DMA read operations and debugger read
* operations such as breakpoints, periodic updates, etc.).
* @retval FLASH Status: The returned value can be:
* FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
__RAM_FUNC DATA_EEPROM_EraseDoubleWord(uint32_t Address)
{
FLASH_Status status = FLASH_COMPLETE;
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
This bit prevents the interruption of multicycle instructions and therefore
will increase the interrupt latency. of Cortex-M3. */
SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
/* Wait for last operation to be completed */
status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
if(status == FLASH_COMPLETE)
{
/* If the previous operation is completed, proceed to erase the next double word */
/* Set the ERASE bit */
FLASH->PECR |= FLASH_PECR_ERASE;
/* Set DATA bit */
FLASH->PECR |= FLASH_PECR_DATA;
/* Write 00000000h to the 2 words to erase */
*(__IO uint32_t *)Address = 0x00000000;
Address += 4;
*(__IO uint32_t *)Address = 0x00000000;
/* Wait for last operation to be completed */
status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
/* If the erase operation is completed, disable the ERASE and DATA bits */
FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);
FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA);
}
SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
/* Return the erase status */
return status;
}
/**
* @brief Write a double word in data memory without erase.
* @param Address: specifies the address to be written.
* @param Data: specifies the data to be written.
* @note To correctly run this function, the DATA_EEPROM_Unlock() function
* must be called before.
* Call the DATA_EEPROM_Lock() to he data EEPROM access
* and Flash program erase control register access(recommended to protect
* the DATA_EEPROM against possible unwanted operation).
* @note Data memory double word write is possible only from SRAM.
* @note A data memory double word is written to the data memory only if the
* first address to load is the start address of a double word (multiple
* of double word).
* @note During the Data memory double word write, all read operations are
* forbidden (this includes DMA read operations and debugger read
* operations such as breakpoints, periodic updates, etc.).
* @retval FLASH Status: The returned value can be:
* FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
__RAM_FUNC DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data)
{
FLASH_Status status = FLASH_COMPLETE;
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
This bit prevents the interruption of multicycle instructions and therefore
will increase the interrupt latency. of Cortex-M3. */
SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
/* Wait for last operation to be completed */
status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
if(status == FLASH_COMPLETE)
{
/* If the previous operation is completed, proceed to program the new data*/
FLASH->PECR |= FLASH_PECR_FPRG;
FLASH->PECR |= FLASH_PECR_DATA;
/* Write the 2 words */
*(__IO uint32_t *)Address = (uint32_t) Data;
Address += 4;
*(__IO uint32_t *)Address = (uint32_t) (Data >> 32);
/* Wait for last operation to be completed */
status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
/* If the write operation is completed, disable the FPRG and DATA bits */
FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA);
}
SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
/* Return the Write Status */
return status;
}
/**
* @}
*/
/**
* @brief Returns the FLASH Status.
* @param None
* @retval FLASH Status: The returned value can be: FLASH_BUSY,
* FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE
*/
static __RAM_FUNC GetStatus(void)
{
FLASH_Status FLASHstatus = FLASH_COMPLETE;
if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
{
FLASHstatus = FLASH_BUSY;
}
else
{
if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)
{
FLASHstatus = FLASH_ERROR_WRP;
}
else
{
if((FLASH->SR & (uint32_t)0x1E00) != (uint32_t)0x00)
{
FLASHstatus = FLASH_ERROR_PROGRAM;
}
else
{
FLASHstatus = FLASH_COMPLETE;
}
}
}
/* Return the FLASH Status */
return FLASHstatus;
}
/**
* @brief Waits for a FLASH operation to complete or a TIMEOUT to occur.
* @param Timeout: FLASH programming Timeout
* @retval FLASH Status: The returned value can be: FLASH_BUSY,
* FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or
* FLASH_TIMEOUT.
*/
static __RAM_FUNC WaitForLastOperation(uint32_t Timeout)
{
__IO FLASH_Status status = FLASH_COMPLETE;
/* Check for the FLASH Status */
status = GetStatus();
/* Wait for a FLASH operation to complete or a TIMEOUT to occur */
while((status == FLASH_BUSY) && (Timeout != 0x00))
{
status = GetStatus();
Timeout--;
}
if(Timeout == 0x00 )
{
status = FLASH_TIMEOUT;
}
/* Return the operation status */
return status;
}
#if defined ( __TASKING__ )
#pragma section_code_init restore
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

285
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_fsmc.c
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@ -1,285 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_fsmc.c
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the FSMC peripheral:
* + Initialization
* + Interrupts and flags management
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_fsmc.h"
#include "stm32l1xx_rcc.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @defgroup FSMC
* @brief FSMC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup FSMC_Private_Functions
* @{
*/
/** @defgroup FSMC_Group1 NOR/SRAM Controller functions
* @brief NOR/SRAM Controller functions
*
@verbatim
==============================================================================
##### NOR-SRAM Controller functions #####
==============================================================================
[..] The following sequence should be followed to configure the FSMC to
interface with SRAM, PSRAM, NOR or OneNAND memory connected to the
NOR/SRAM Bank:
(#) Enable the clock for the FSMC and associated GPIOs using the following
functions:
(++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
(++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE);
(#) FSMC pins configuration
(++) Connect the involved FSMC pins to AF12 using the following function
GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
(++) Configure these FSMC pins in alternate function mode by calling the
function GPIO_Init();
(#) Declare a FSMC_NORSRAMInitTypeDef structure, for example:
FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; and fill the
FSMC_NORSRAMInitStructure variable with the allowed values of the
structure member.
(#) Initialize the NOR/SRAM Controller by calling the function
FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
(#) Then enable the NOR/SRAM Bank, for example:
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
(#) At this stage you can read/write from/to the memory connected to the
NOR/SRAM Bank.
@endverbatim
* @{
*/
/**
* @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
* reset values.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
* @retval None
*/
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
{
/* Check the parameter */
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
/* FSMC_Bank1_NORSRAM1 */
if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
{
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
}
/* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
else
{
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
}
FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
}
/**
* @brief Initializes the FSMC NOR/SRAM Banks according to the specified
* parameters in the FSMC_NORSRAMInitStruct.
* @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
* structure that contains the configuration information for
* the FSMC NOR/SRAM specified Banks.
* @retval None
*/
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
{
/* Check the parameters */
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
/* Bank1 NOR/SRAM control register configuration */
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
FSMC_NORSRAMInitStruct->FSMC_MemoryType |
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
FSMC_NORSRAMInitStruct->FSMC_WrapMode |
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
{
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)FSMC_BCR1_FACCEN;
}
/* Bank1 NOR/SRAM timing register configuration */
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
/* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
{
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
}
else
{
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
}
}
/**
* @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
* @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
* structure which will be initialized.
* @retval None
*/
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
{
/* Reset NOR/SRAM Init structure parameters values */
FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
}
/**
* @brief Enables or disables the specified NOR/SRAM Memory Bank.
* @param FSMC_Bank: specifies the FSMC Bank to be used
* This parameter can be one of the following values:
* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
* @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
{
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected NOR/SRAM Bank by setting the MBKEN bit in the BCRx register */
FSMC_Bank1->BTCR[FSMC_Bank] |= FSMC_BCR1_MBKEN;
}
else
{
/* Disable the selected NOR/SRAM Bank by clearing the MBKEN bit in the BCRx register */
FSMC_Bank1->BTCR[FSMC_Bank] &= (uint32_t)(~FSMC_BCR1_MBKEN);
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32l1xx_iwdg.c
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the Independent watchdog (IWDG) peripheral:
* + Prescaler and Counter configuration
* + IWDG activation
* + Flag management
*
* @verbatim
*
==============================================================================
##### IWDG features #####
==============================================================================
[..] The IWDG can be started by either software or hardware (configurable
through option byte).
[..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and
thus stays active even if the main clock fails.
Once the IWDG is started, the LSI is forced ON and cannot be disabled
(LSI cannot be disabled too), and the counter starts counting down from
the reset value of 0xFFF. When it reaches the end of count value (0x000)
a system reset is generated.
The IWDG counter should be reloaded at regular intervals to prevent
an MCU reset.
[..] The IWDG is implemented in the VDD voltage domain that is still functional
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
[..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
reset occurs.
[..] Min-max timeout value @37KHz (LSI): ~108us / ~28.3s
The IWDG timeout may vary due to LSI frequency dispersion. STM32L1xx
devices provide the capability to measure the LSI frequency (LSI clock
connected internally to TIM10 CH1 input capture). The measured value
can be used to have an IWDG timeout with an acceptable accuracy.
For more information, please refer to the STM32L1xx Reference manual.
##### How to use this driver #####
==============================================================================
[..]
(#) Enable write access to IWDG_PR and IWDG_RLR registers using
IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
(#) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
(#) Configure the IWDG counter value using IWDG_SetReload() function.
This value will be loaded in the IWDG counter each time the counter
is reloaded, then the IWDG will start counting down from this value.
(#) Start the IWDG using IWDG_Enable() function, when the IWDG is used
in software mode (no need to enable the LSI, it will be enabled
by hardware).
(#) Then the application program must reload the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
IWDG_ReloadCounter() function.
@endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_iwdg.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @defgroup IWDG
* @brief IWDG driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ---------------------- IWDG registers bit mask ----------------------------*/
/* KR register bit mask */
#define KR_KEY_RELOAD ((uint16_t)0xAAAA)
#define KR_KEY_ENABLE ((uint16_t)0xCCCC)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup IWDG_Private_Functions
* @{
*/
/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
* @brief Prescaler and Counter configuration functions
*
@verbatim
==============================================================================
##### Prescaler and Counter configuration functions #####
==============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
* @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
* This parameter can be one of the following values:
* @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
* @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
* @retval None
*/
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
{
/* Check the parameters */
assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
IWDG->KR = IWDG_WriteAccess;
}
/**
* @brief Sets IWDG Prescaler value.
* @param IWDG_Prescaler: specifies the IWDG Prescaler value.
* This parameter can be one of the following values:
* @arg IWDG_Prescaler_4: IWDG prescaler set to 4
* @arg IWDG_Prescaler_8: IWDG prescaler set to 8
* @arg IWDG_Prescaler_16: IWDG prescaler set to 16
* @arg IWDG_Prescaler_32: IWDG prescaler set to 32
* @arg IWDG_Prescaler_64: IWDG prescaler set to 64
* @arg IWDG_Prescaler_128: IWDG prescaler set to 128
* @arg IWDG_Prescaler_256: IWDG prescaler set to 256
* @retval None
*/
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
{
/* Check the parameters */
assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
IWDG->PR = IWDG_Prescaler;
}
/**
* @brief Sets IWDG Reload value.
* @param Reload: specifies the IWDG Reload value.
* This parameter must be a number between 0 and 0x0FFF.
* @retval None
*/
void IWDG_SetReload(uint16_t Reload)
{
/* Check the parameters */
assert_param(IS_IWDG_RELOAD(Reload));
IWDG->RLR = Reload;
}
/**
* @brief Reloads IWDG counter with value defined in the reload register
* (write access to IWDG_PR and IWDG_RLR registers disabled).
* @param None
* @retval None
*/
void IWDG_ReloadCounter(void)
{
IWDG->KR = KR_KEY_RELOAD;
}
/**
* @}
*/
/** @defgroup IWDG_Group2 IWDG activation function
* @brief IWDG activation function
*
@verbatim
==============================================================================
##### IWDG activation function #####
==============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
* @param None.
* @retval None.
*/
void IWDG_Enable(void)
{
IWDG->KR = KR_KEY_ENABLE;
}
/**
* @}
*/
/** @defgroup IWDG_Group3 Flag management function
* @brief Flag management function
*
@verbatim
===============================================================================
##### Flag management function #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Checks whether the specified IWDG flag is set or not.
* @param IWDG_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg IWDG_FLAG_PVU: Prescaler Value Update on going
* @arg IWDG_FLAG_RVU: Reload Value Update on going
* @retval The new state of IWDG_FLAG (SET or RESET).
*/
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_IWDG_FLAG(IWDG_FLAG));
if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the flag status */
return bitstatus;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32l1xx_opamp.c
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the operational amplifiers (opamp) peripheral:
* + Initialization and configuration
* + Calibration management
*
* @verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..] The device integrates three independent rail-to-rail operational amplifiers
OPAMP1, OPAMP2 and OPAMP3:
(+) Internal connections to the ADC.
(+) Internal connections to the DAC.
(+) Internal connection to COMP1 (only OPAMP3).
(+) Internal connection for unity gain (voltage follower) configuration.
(+) Calibration capability.
(+) Selectable gain-bandwidth (2MHz in normal mode, 500KHz in low power mode).
[..]
(#) COMP AHB clock must be enabled to get write access
to OPAMP registers using
(#) RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE)
(#) Configure the corresponding GPIO to OPAMPx INP, OPAMPx_INN (if used)
and OPAMPx_OUT in analog mode.
(#) Configure (close/open) the OPAMP switches using OPAMP_SwitchCmd()
(#) Enable the OPAMP peripheral using OPAMP_Cmd()
-@- In order to use OPAMP outputs as ADC inputs, the opamps must be enabled
and the ADC must use the OPAMP output channel number:
(+@) OPAMP1 output is connected to ADC channel 3.
(+@) OPAMP2 output is connected to ADC channel 8.
(+@) OPAMP3 output is connected to ADC channel 13 (SW1 switch must be closed).
* @endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_opamp.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @defgroup OPAMP
* @brief OPAMP driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup OPAMP_Private_Functions
* @{
*/
/** @defgroup OPAMP_Group1 Initialization and configuration
* @brief Initialization and configuration
*
@verbatim
===============================================================================
##### Initialization and configuration #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitialize the OPAMPs register to its default reset value.
* @note At startup, OTR and LPOTR registers are set to factory programmed values.
* @param None.
* @retval None.
*/
void OPAMP_DeInit(void)
{
/*!< Set OPAMP_CSR register to reset value */
OPAMP->CSR = 0x00010101;
/*!< Set OPAMP_OTR register to reset value */
OPAMP->OTR = (uint32_t)(* (uint32_t*)FLASH_R_BASE + 0x00000038);
/*!< Set OPAMP_LPOTR register to reset value */
OPAMP->LPOTR = (uint32_t)(* (uint32_t*)FLASH_R_BASE + 0x0000003C);
}
/**
* @brief Close or Open the OPAMP switches.
* @param OPAMP_OPAMPxSwitchy: selects the OPAMPx switch.
* This parameter can be any combinations of the following values:
* @arg OPAMP_OPAMP1Switch3: used to connect internally OPAMP1 output to
* OPAMP1 negative input (internal follower)
* @arg OPAMP_OPAMP1Switch4: used to connect PA2 to OPAMP1 negative input
* @arg OPAMP_OPAMP1Switch5: used to connect PA1 to OPAMP1 positive input
* @arg OPAMP_OPAMP1Switch6: used to connect DAC_OUT1 to OPAMP1 positive input
* @arg OPAMP_OPAMP1SwitchANA: used to meet 1 nA input leakage
* @arg OPAMP_OPAMP2Switch3: used to connect internally OPAMP2 output to
* OPAMP2 negative input (internal follower)
* @arg OPAMP_OPAMP2Switch4: used to connect PA7 to OPAMP2 negative input
* @arg OPAMP_OPAMP2Switch5: used to connect PA6 to OPAMP2 positive input
* @arg OPAMP_OPAMP2Switch6: used to connect DAC_OUT1 to OPAMP2 positive input
* @arg OPAMP_OPAMP2Switch7: used to connect DAC_OUT2 to OPAMP2 positive input
* @arg OPAMP_OPAMP2SwitchANA: used to meet 1 nA input leakage
* @arg OPAMP_OPAMP3Switch3: used to connect internally OPAMP3 output to
* OPAMP3 negative input (internal follower)
* @arg OPAMP_OPAMP3Switch4: used to connect PC2 to OPAMP3 negative input
* @arg OPAMP_OPAMP3Switch5: used to connect PC1 to OPAMP3 positive input
* @arg OPAMP_OPAMP3Switch6: used to connect DAC_OUT1 to OPAMP3 positive input
* @arg OPAMP_OPAMP3SwitchANA: used to meet 1 nA input leakage on negative input
*
* @param NewState: New state of the OPAMP switch.
* This parameter can be:
* ENABLE to close the OPAMP switch
* or DISABLE to open the OPAMP switch
* @note OPAMP_OPAMP2Switch6 and OPAMP_OPAMP2Switch7 mustn't be closed together.
* @retval None
*/
void OPAMP_SwitchCmd(uint32_t OPAMP_OPAMPxSwitchy, FunctionalState NewState)
{
/* Check the parameter */
assert_param(IS_OPAMP_SWITCH(OPAMP_OPAMPxSwitchy));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Close the selected switches */
OPAMP->CSR |= (uint32_t) OPAMP_OPAMPxSwitchy;
}
else
{
/* Open the selected switches */
OPAMP->CSR &= (~(uint32_t)OPAMP_OPAMPxSwitchy);
}
}
/**
* @brief Enable or disable the OPAMP peripheral.
* @param OPAMP_Selection: the selected OPAMP.
* This parameter can be one of the following values:
* @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected
* @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected
* @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected
* @param NewState: new state of the selected OPAMP peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState)
{
/* Check the parameter */
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected OPAMP */
OPAMP->CSR &= (~(uint32_t) OPAMP_Selection);
}
else
{
/* Disable the selected OPAMP */
OPAMP->CSR |= (uint32_t) OPAMP_Selection;
}
}
/**
* @brief Enable or disable the low power mode for OPAMP peripheral.
* @param OPAMP_Selection: the selected OPAMP.
* This parameter can be one of the following values:
* @arg OPAMP_Selection_OPAMP1: OPAMP1 selected
* @arg OPAMP_Selection_OPAMP2: OPAMP2 selected
* @arg OPAMP_Selection_OPAMP3: OPAMP3 selected
* @param NewState: new low power state of the selected OPAMP peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void OPAMP_LowPowerCmd(uint32_t OPAMP_Selection, FunctionalState NewState)
{
/* Check the parameter */
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Set the selected OPAMP in low power mode */
OPAMP->CSR |= (uint32_t) (OPAMP_Selection << 7);
}
else
{
/* Disable the low power mode for the selected OPAMP */
OPAMP->CSR &= (~(uint32_t) (OPAMP_Selection << 7));
}
}
/**
* @brief Select the OPAMP power range.
* @note The OPAMP power range selection must be performed while OPAMPs are powered down.
* @param OPAMP_Range: the selected OPAMP power range.
* This parameter can be one of the following values:
* @arg OPAMP_PowerRange_Low: Low power range is selected (VDDA is lower than 2.4V).
* @arg OPAMP_PowerRange_High: High power range is selected (VDDA is higher than 2.4V).
* @retval None
*/
void OPAMP_PowerRangeSelect(uint32_t OPAMP_PowerRange)
{
/* Check the parameter */
assert_param(IS_OPAMP_RANGE(OPAMP_PowerRange));
/* Reset the OPAMP range bit */
OPAMP->CSR &= (~(uint32_t) (OPAMP_CSR_AOP_RANGE));
/* Select the OPAMP power range */
OPAMP->CSR |= OPAMP_PowerRange;
}
/**
* @}
*/
/** @defgroup OPAMP_Group2 Calibration functions
* @brief Calibration functions
*
@verbatim
===============================================================================
##### Calibration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Select the trimming mode.
* @param OffsetTrimming: the selected offset trimming mode.
* This parameter can be one of the following values:
* @arg OffsetTrimming_Factory: factory trimming values are used for offset
* calibration.
* @arg OffsetTrimming_User: user trimming values are used for offset
* calibration.
* @note When OffsetTrimming_User is selected, use OPAMP_OffsetTrimConfig()
* function or OPAMP_OffsetTrimLowPowerConfig() function to adjust
* trimming value.
* @retval None
*/
void OPAMP_OffsetTrimmingModeSelect(uint32_t OPAMP_Trimming)
{
/* Check the parameter */
assert_param(IS_OPAMP_TRIMMING(OPAMP_Trimming));
/* Reset the OPAMP_OTR range bit */
OPAMP->CSR &= (~(uint32_t) (OPAMP_OTR_OT_USER));
/* Select the OPAMP offset trimming */
OPAMP->CSR |= OPAMP_Trimming;
}
/**
* @brief Configure the trimming value of OPAMPs in normal mode.
* @param OPAMP_Selection: the selected OPAMP.
* This parameter can be one of the following values:
* @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected to configure the trimming value.
* @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected to configure the trimming value.
* @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected to configure the trimming value.
* @param OPAMP_Input: the selected OPAMP input.
* This parameter can be one of the following values:
* @arg OPAMP_Input_NMOS: NMOS input is selected to configure the trimming value.
* @arg OPAMP_Input_PMOS: PMOS input is selected to configure the trimming value.
* @param OPAMP_TrimValue: the trimming value. This parameter can be any value lower
* or equal to 0x0000001F.
* @retval None
*/
void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
{
uint32_t tmpreg = 0;
/* Check the parameter */
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
assert_param(IS_OPAMP_INPUT(OPAMP_Input));
assert_param(IS_OPAMP_TRIMMINGVALUE(OPAMP_TrimValue));
/* Get the OPAMP_OTR value */
tmpreg = OPAMP->OTR;
if(OPAMP_Selection == OPAMP_Selection_OPAMP1)
{
/* Reset the OPAMP inputs selection */
tmpreg &= (uint32_t)~(OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA1CAL_H);
/* Select the OPAMP input */
tmpreg |= OPAMP_Input;
if(OPAMP_Input == OPAMP_Input_PMOS)
{
/* Reset the trimming value corresponding to OPAMP1 PMOS input */
tmpreg &= (0xFFFFFFE0);
/* Set the new trimming value corresponding to OPAMP1 PMOS input */
tmpreg |= (OPAMP_TrimValue);
}
else
{
/* Reset the trimming value corresponding to OPAMP1 NMOS input */
tmpreg &= (0xFFFFFC1F);
/* Set the new trimming value corresponding to OPAMP1 NMOS input */
tmpreg |= (OPAMP_TrimValue<<5);
}
}
else if (OPAMP_Selection == OPAMP_Selection_OPAMP2)
{
/* Reset the OPAMP inputs selection */
tmpreg &= (uint32_t)~(OPAMP_CSR_OPA2CAL_L | OPAMP_CSR_OPA2CAL_H);
/* Select the OPAMP input */
tmpreg |= (uint32_t)(OPAMP_Input<<8);
if(OPAMP_Input == OPAMP_Input_PMOS)
{
/* Reset the trimming value corresponding to OPAMP2 PMOS input */
tmpreg &= (0xFFFF83FF);
/* Set the new trimming value corresponding to OPAMP2 PMOS input */
tmpreg |= (OPAMP_TrimValue<<10);
}
else
{
/* Reset the trimming value corresponding to OPAMP2 NMOS input */
tmpreg &= (0xFFF07FFF);
/* Set the new trimming value corresponding to OPAMP2 NMOS input */
tmpreg |= (OPAMP_TrimValue<<15);
}
}
else
{
/* Reset the OPAMP inputs selection */
tmpreg &= (uint32_t)~(OPAMP_CSR_OPA3CAL_L | OPAMP_CSR_OPA3CAL_H);
/* Select the OPAMP input */
tmpreg |= (uint32_t)(OPAMP_Input<<16);
if(OPAMP_Input == OPAMP_Input_PMOS)
{
/* Reset the trimming value corresponding to OPAMP3 PMOS input */
tmpreg &= (0xFE0FFFFF);
/* Set the new trimming value corresponding to OPAMP3 PMOS input */
tmpreg |= (OPAMP_TrimValue<<20);
}
else
{
/* Reset the trimming value corresponding to OPAMP3 NMOS input */
tmpreg &= (0xC1FFFFFF);
/* Set the new trimming value corresponding to OPAMP3 NMOS input */
tmpreg |= (OPAMP_TrimValue<<25);
}
}
/* Set the OPAMP_OTR register */
OPAMP->OTR = tmpreg;
}
/**
* @brief Configure the trimming value of OPAMPs in low power mode.
* @param OPAMP_Selection: the selected OPAMP.
* This parameter can be one of the following values:
* @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected to configure the trimming value.
* @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected to configure the trimming value.
* @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected to configure the trimming value.
* @param OPAMP_Input: the selected OPAMP input.
* This parameter can be one of the following values:
* @arg OPAMP_Input_NMOS: NMOS input is selected to configure the trimming value.
* @arg OPAMP_Input_PMOS: PMOS input is selected to configure the trimming value.
* @param OPAMP_TrimValue: the trimming value.
* This parameter can be any value lower or equal to 0x0000001F.
* @retval None
*/
void OPAMP_OffsetTrimLowPowerConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
{
uint32_t tmpreg = 0;
/* Check the parameter */
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
assert_param(IS_OPAMP_INPUT(OPAMP_Input));
assert_param(IS_OPAMP_TRIMMINGVALUE(OPAMP_TrimValue));
/* Get the OPAMP_LPOTR value */
tmpreg = OPAMP->LPOTR;
if(OPAMP_Selection == OPAMP_Selection_OPAMP1)
{
/* Reset the OPAMP inputs selection */
tmpreg &= (uint32_t)~(OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA1CAL_H);
/* Select the OPAMP input */
tmpreg |= OPAMP_Input;
if(OPAMP_Input == OPAMP_Input_PMOS)
{
/* Reset the trimming value corresponding to OPAMP1 PMOS input */
tmpreg &= (0xFFFFFFE0);
/* Set the new trimming value corresponding to OPAMP1 PMOS input */
tmpreg |= (OPAMP_TrimValue);
}
else
{
/* Reset the trimming value corresponding to OPAMP1 NMOS input */
tmpreg &= (0xFFFFFC1F);
/* Set the new trimming value corresponding to OPAMP1 NMOS input */
tmpreg |= (OPAMP_TrimValue<<5);
}
}
else if (OPAMP_Selection == OPAMP_Selection_OPAMP2)
{
/* Reset the OPAMP inputs selection */
tmpreg &= (uint32_t)~(OPAMP_CSR_OPA2CAL_L | OPAMP_CSR_OPA2CAL_H);
/* Select the OPAMP input */
tmpreg |= (uint32_t)(OPAMP_Input<<8);
if(OPAMP_Input == OPAMP_Input_PMOS)
{
/* Reset the trimming value corresponding to OPAMP2 PMOS input */
tmpreg &= (0xFFFF83FF);
/* Set the new trimming value corresponding to OPAMP2 PMOS input */
tmpreg |= (OPAMP_TrimValue<<10);
}
else
{
/* Reset the trimming value corresponding to OPAMP2 NMOS input */
tmpreg &= (0xFFF07FFF);
/* Set the new trimming value corresponding to OPAMP2 NMOS input */
tmpreg |= (OPAMP_TrimValue<<15);
}
}
else
{
/* Reset the OPAMP inputs selection */
tmpreg &= (uint32_t)~(OPAMP_CSR_OPA3CAL_L | OPAMP_CSR_OPA3CAL_H);
/* Select the OPAMP input */
tmpreg |= (uint32_t)(OPAMP_Input<<16);
if(OPAMP_Input == OPAMP_Input_PMOS)
{
/* Reset the trimming value corresponding to OPAMP3 PMOS input */
tmpreg &= (0xFE0FFFFF);
/* Set the new trimming value corresponding to OPAMP3 PMOS input */
tmpreg |= (OPAMP_TrimValue<<20);
}
else
{
/* Reset the trimming value corresponding to OPAMP3 NMOS input */
tmpreg &= (0xC1FFFFFF);
/* Set the new trimming value corresponding to OPAMP3 NMOS input */
tmpreg |= (OPAMP_TrimValue<<25);
}
}
/* Set the OPAMP_LPOTR register */
OPAMP->LPOTR = tmpreg;
}
/**
* @brief Checks whether the specified OPAMP calibration flag is set or not.
* @note User should wait until calibration flag change the value when changing
* the trimming value.
* @param OPAMP_Selection: the selected OPAMP.
* This parameter can be one of the following values:
* @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected.
* @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected.
* @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected.
* @retval The new state of the OPAMP calibration flag (SET or RESET).
*/
FlagStatus OPAMP_GetFlagStatus(uint32_t OPAMP_Selection)
{
FlagStatus bitstatus = RESET;
uint32_t tmpreg = 0;
/* Check the parameter */
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
/* Get the CSR register value */
tmpreg = OPAMP->CSR;
/* Check if OPAMP1 is selected */
if(OPAMP_Selection == OPAMP_Selection_OPAMP1)
{
/* Check OPAMP1 CAL bit status */
if ((tmpreg & OPAMP_CSR_OPA1CALOUT) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
/* Check if OPAMP2 is selected */
else if(OPAMP_Selection == OPAMP_Selection_OPAMP2)
{
/* Check OPAMP2 CAL bit status */
if ((tmpreg & OPAMP_CSR_OPA2CALOUT) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
else
{
/* Check OPAMP3 CAL bit status */
if ((tmpreg & OPAMP_CSR_OPA3CALOUT) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
return bitstatus;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_sdio.c
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@ -1,984 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_sdio.c
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the SDIO peripheral:
* + Initialization
* + Interrupts and flags management
*
* @verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL
(PLLVCO) througth a fixed divider by 2.
Before to start working with SDIO peripheral make sure that the PLLVCO is
well configured to 96MHz.
The SDIO peripheral uses two clock signals:
(++) SDIO adapter clock (SDIOCLK = 48 MHz).
(++) APB2 bus clock (PCLK2).
PCLK2 and SDIO_CK clock frequencies must respect the following
condition: Frequenc(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)).
(#) Enable peripheral clock using
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE).
(#) According to the SDIO mode, enable the GPIO clocks using
RCC_AHBPeriphClockCmd() function.
The I/O can be one of the following configurations:
(++) 1-bit data length: SDIO_CMD, SDIO_CK and D0.
(++) 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0].
(++) 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0].
(#) Peripheral's alternate function:
(++) Connect the pin to the desired peripherals' Alternate
Function (AF) using GPIO_PinAFConfig() function.
(++) Configure the desired pin in alternate function by:
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
(++) Select the type, pull-up/pull-down and output speed via
GPIO_PuPd, GPIO_OType and GPIO_Speed members.
(++) Call GPIO_Init() function.
(#) Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide,
hardware, flow control and the Clock Divider using the SDIO_Init()
function.
(#) Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON)
function.
(#) Enable the clock using the SDIO_ClockCmd() function.
(#) Enable the NVIC and the corresponding interrupt using the function
SDIO_ITConfig() if you need to use interrupt mode.
(#) When using the DMA mode
(++) Configure the DMA using DMA_Init() function.
(++) Active the needed channel Request using SDIO_DMACmd() function.
(#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.
(#) To control the CPSM (Command Path State Machine) and send commands to the
card use the SDIO_SendCommand(), SDIO_GetCommandResponse() and
SDIO_GetResponse() functions. First, user has to fill the command
structure (pointer to SDIO_CmdInitTypeDef) according to the selected
command to be sent. The parameters that should be filled are:
(++) Command Argument.
(++) Command Index.
(++) Command Response type.
(++) Command Wait.
(++) CPSM Status (Enable or Disable).
To check if the command is well received, read the SDIO_CMDRESP register
using the SDIO_GetCommandResponse(). The SDIO responses registers
(SDIO_RESP1 to SDIO_RESP2), use the SDIO_GetResponse() function.
(#) To control the DPSM (Data Path State Machine) and send/receive
data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),
SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions.
*** Read Operations ***
-----------------------
[..]
(#) First, user has to fill the data structure (pointer to
SDIO_DataInitTypeDef) according to the selected data type to be received.
The parameters that should be filled are:
(++) Data TimeOut.
(++) Data Length.
(++) Data Block size.
(++) Data Transfer direction: should be from card (To SDIO).
(++) Data Transfer mode.
(++) DPSM Status (Enable or Disable).
(#) Configure the SDIO resources to receive the data from the card
according to selected transfer mode (Refer to Step 8, 9 and 10).
(#) Send the selected Read command (refer to step 11).
(#) Use the SDIO flags/interrupts to check the transfer status.
*** Write Operations ***
------------------------
[..]
(#) First, user has to fill the data structure (pointer to
SDIO_DataInitTypeDef) according to the selected data type to be received.
The parameters that should be filled are:
(++) Data TimeOut.
(++) Data Length.
(++) Data Block size.
(++) Data Transfer direction: should be to card (To CARD).
(++) Data Transfer mode.
(++) DPSM Status (Enable or Disable).
(#) Configure the SDIO resources to send the data to the card
according to selected transfer mode (Refer to Step 8, 9 and 10).
(#) Send the selected Write command (refer to step 11).
(#) Use the SDIO flags/interrupts to check the transfer status.
@endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_sdio.h"
#include "stm32l1xx_rcc.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @defgroup SDIO
* @brief SDIO driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ------------ SDIO registers bit address in the alias region ----------- */
#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
/* --- CLKCR Register ---*/
/* Alias word address of CLKEN bit */
#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
#define CLKEN_BitNumber 0x08
#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
/* --- CMD Register ---*/
/* Alias word address of SDIOSUSPEND bit */
#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
#define SDIOSUSPEND_BitNumber 0x0B
#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
/* Alias word address of ENCMDCOMPL bit */
#define ENCMDCOMPL_BitNumber 0x0C
#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
/* Alias word address of NIEN bit */
#define NIEN_BitNumber 0x0D
#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
/* Alias word address of ATACMD bit */
#define ATACMD_BitNumber 0x0E
#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
/* --- DCTRL Register ---*/
/* Alias word address of DMAEN bit */
#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
#define DMAEN_BitNumber 0x03
#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
/* Alias word address of RWSTART bit */
#define RWSTART_BitNumber 0x08
#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
/* Alias word address of RWSTOP bit */
#define RWSTOP_BitNumber 0x09
#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
/* Alias word address of RWMOD bit */
#define RWMOD_BitNumber 0x0A
#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
/* Alias word address of SDIOEN bit */
#define SDIOEN_BitNumber 0x0B
#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
/* ---------------------- SDIO registers bit mask ------------------------ */
/* --- CLKCR Register ---*/
/* CLKCR register clear mask */
#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
/* --- PWRCTRL Register ---*/
/* SDIO PWRCTRL Mask */
#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
/* --- DCTRL Register ---*/
/* SDIO DCTRL Clear Mask */
#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
/* --- CMD Register ---*/
/* CMD Register clear mask */
#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
/* SDIO RESP Registers Address */
#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SDIO_Private_Functions
* @{
*/
/** @defgroup SDIO_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and Configuration functions #####
==============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the SDIO peripheral registers to their default reset values.
* @param None
* @retval None
*/
void SDIO_DeInit(void)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE);
}
/**
* @brief Initializes the SDIO peripheral according to the specified
* parameters in the SDIO_InitStruct.
* @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
* that contains the configuration information for the SDIO peripheral.
* @retval None
*/
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
/*---------------------------- SDIO CLKCR Configuration ------------------------*/
/* Get the SDIO CLKCR value */
tmpreg = SDIO->CLKCR;
/* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
tmpreg &= CLKCR_CLEAR_MASK;
/* Set CLKDIV bits according to SDIO_ClockDiv value */
/* Set PWRSAV bit according to SDIO_ClockPowerSave value */
/* Set BYPASS bit according to SDIO_ClockBypass value */
/* Set WIDBUS bits according to SDIO_BusWide value */
/* Set NEGEDGE bits according to SDIO_ClockEdge value */
/* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
/* Write to SDIO CLKCR */
SDIO->CLKCR = tmpreg;
}
/**
* @brief Fills each SDIO_InitStruct member with its default value.
* @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
* will be initialized.
* @retval None
*/
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
{
/* SDIO_InitStruct members default value */
SDIO_InitStruct->SDIO_ClockDiv = 0x00;
SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
}
/**
* @brief Enables or disables the SDIO Clock.
* @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SDIO_ClockCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
}
/**
* @brief Sets the power status of the controller.
* @param SDIO_PowerState: new state of the Power state.
* This parameter can be one of the following values:
* @arg SDIO_PowerState_OFF: SDIO Power OFF.
* @arg SDIO_PowerState_ON: SDIO Power ON.
* @retval None
*/
void SDIO_SetPowerState(uint32_t SDIO_PowerState)
{
/* Check the parameters */
assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
SDIO->POWER = SDIO_PowerState;
}
/**
* @brief Gets the power status of the controller.
* @param None
* @retval Power status of the controller. The returned value can
* be one of the following:
* - 0x00: Power OFF
* - 0x02: Power UP
* - 0x03: Power ON
*/
uint32_t SDIO_GetPowerState(void)
{
return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
}
/**
* @}
*/
/** @defgroup SDIO_Group2 DMA transfers management functions
* @brief DMA transfers management functions
*
@verbatim
==============================================================================
##### DMA transfers management functions #####
==============================================================================
[..] This section provide functions allowing to program SDIO DMA transfer.
@endverbatim
* @{
*/
/**
* @brief Enables or disables the SDIO DMA request.
* @param NewState: new state of the selected SDIO DMA request.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SDIO_DMACmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
}
/**
* @}
*/
/** @defgroup SDIO_Group3 Command path state machine (CPSM) management functions
* @brief Command path state machine (CPSM) management functions
*
@verbatim
==============================================================================
##### Command path state machine (CPSM) management functions #####
==============================================================================
[..] This section provide functions allowing to program and read the Command
path state machine (CPSM).
@endverbatim
* @{
*/
/**
* @brief Initializes the SDIO Command according to the specified
* parameters in the SDIO_CmdInitStruct and send the command.
* @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
* structure that contains the configuration information for the SDIO command.
* @retval None
*/
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
/*---------------------------- SDIO ARG Configuration ------------------------*/
/* Set the SDIO Argument value */
SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
/*---------------------------- SDIO CMD Configuration ------------------------*/
/* Get the SDIO CMD value */
tmpreg = SDIO->CMD;
/* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
tmpreg &= CMD_CLEAR_MASK;
/* Set CMDINDEX bits according to SDIO_CmdIndex value */
/* Set WAITRESP bits according to SDIO_Response value */
/* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
/* Set CPSMEN bits according to SDIO_CPSM value */
tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
| SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
/* Write to SDIO CMD */
SDIO->CMD = tmpreg;
}
/**
* @brief Fills each SDIO_CmdInitStruct member with its default value.
* @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
* structure which will be initialized.
* @retval None
*/
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
{
/* SDIO_CmdInitStruct members default value */
SDIO_CmdInitStruct->SDIO_Argument = 0x00;
SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
}
/**
* @brief Returns command index of last command for which response received.
* @param None
* @retval Returns the command index of the last command response received.
*/
uint8_t SDIO_GetCommandResponse(void)
{
return (uint8_t)(SDIO->RESPCMD);
}
/**
* @brief Returns response received from the card for the last command.
* @param SDIO_RESP: Specifies the SDIO response register.
* This parameter can be one of the following values:
* @arg SDIO_RESP1: Response Register 1.
* @arg SDIO_RESP2: Response Register 2.
* @arg SDIO_RESP3: Response Register 3.
* @arg SDIO_RESP4: Response Register 4.
* @retval The Corresponding response register value.
*/
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_SDIO_RESP(SDIO_RESP));
tmp = SDIO_RESP_ADDR + SDIO_RESP;
return (*(__IO uint32_t *) tmp);
}
/**
* @}
*/
/** @defgroup SDIO_Group4 Data path state machine (DPSM) management functions
* @brief Data path state machine (DPSM) management functions
*
@verbatim
==============================================================================
##### Data path state machine (DPSM) management functions #####
==============================================================================
[..] This section provide functions allowing to program and read the Data path
state machine (DPSM).
@endverbatim
* @{
*/
/**
* @brief Initializes the SDIO data path according to the specified
* parameters in the SDIO_DataInitStruct.
* @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
* contains the configuration information for the SDIO command.
* @retval None
*/
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
/*---------------------------- SDIO DTIMER Configuration ---------------------*/
/* Set the SDIO Data TimeOut value */
SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
/*---------------------------- SDIO DLEN Configuration -----------------------*/
/* Set the SDIO DataLength value */
SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
/*---------------------------- SDIO DCTRL Configuration ----------------------*/
/* Get the SDIO DCTRL value */
tmpreg = SDIO->DCTRL;
/* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
tmpreg &= DCTRL_CLEAR_MASK;
/* Set DEN bit according to SDIO_DPSM value */
/* Set DTMODE bit according to SDIO_TransferMode value */
/* Set DTDIR bit according to SDIO_TransferDir value */
/* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
| SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
/* Write to SDIO DCTRL */
SDIO->DCTRL = tmpreg;
}
/**
* @brief Fills each SDIO_DataInitStruct member with its default value.
* @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
* will be initialized.
* @retval None
*/
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
{
/* SDIO_DataInitStruct members default value */
SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
SDIO_DataInitStruct->SDIO_DataLength = 0x00;
SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
}
/**
* @brief Returns number of remaining data bytes to be transferred.
* @param None
* @retval Number of remaining data bytes to be transferred
*/
uint32_t SDIO_GetDataCounter(void)
{
return SDIO->DCOUNT;
}
/**
* @brief Read one data word from Rx FIFO.
* @param None
* @retval Data received
*/
uint32_t SDIO_ReadData(void)
{
return SDIO->FIFO;
}
/**
* @brief Write one data word to Tx FIFO.
* @param Data: 32-bit data word to write.
* @retval None
*/
void SDIO_WriteData(uint32_t Data)
{
SDIO->FIFO = Data;
}
/**
* @brief Returns the number of words left to be written to or read from FIFO.
* @param None
* @retval Remaining number of words.
*/
uint32_t SDIO_GetFIFOCount(void)
{
return SDIO->FIFOCNT;
}
/**
* @}
*/
/** @defgroup SDIO_Group5 SDIO IO Cards mode management functions
* @brief SDIO IO Cards mode management functions
*
@verbatim
==============================================================================
##### SDIO IO Cards mode management functions #####
==============================================================================
[..] This section provide functions allowing to program and read the SDIO IO
Cards.
@endverbatim
* @{
*/
/**
* @brief Starts the SD I/O Read Wait operation.
* @param NewState: new state of the Start SDIO Read Wait operation.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SDIO_StartSDIOReadWait(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
}
/**
* @brief Stops the SD I/O Read Wait operation.
* @param NewState: new state of the Stop SDIO Read Wait operation.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SDIO_StopSDIOReadWait(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
}
/**
* @brief Sets one of the two options of inserting read wait interval.
* @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
* This parametre can be:
* @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK.
* @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2.
* @retval None
*/
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
{
/* Check the parameters */
assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
*(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
}
/**
* @brief Enables or disables the SD I/O Mode Operation.
* @param NewState: new state of SDIO specific operation.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SDIO_SetSDIOOperation(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
}
/**
* @brief Enables or disables the SD I/O Mode suspend command sending.
* @param NewState: new state of the SD I/O Mode suspend command.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
}
/**
* @}
*/
/** @defgroup SDIO_Group6 CE-ATA mode management functions
* @brief CE-ATA mode management functions
*
@verbatim
==============================================================================
##### CE-ATA mode management functions #####
==============================================================================
[..] This section provide functions allowing to program and read the CE-ATA
card.
@endverbatim
* @{
*/
/**
* @brief Enables or disables the command completion signal.
* @param NewState: new state of command completion signal.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SDIO_CommandCompletionCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
}
/**
* @brief Enables or disables the CE-ATA interrupt.
* @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SDIO_CEATAITCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
}
/**
* @brief Sends CE-ATA command (CMD61).
* @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SDIO_SendCEATACmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
}
/**
* @}
*/
/** @defgroup SDIO_Group7 Interrupts and flags management functions
* @brief Interrupts and flags management functions
@verbatim
==============================================================================
##### Interrupts and flags management functions #####
==============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the SDIO interrupts.
* @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt.
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt.
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt.
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt.
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt.
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt.
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
* bus mode interrupt.
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt.
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt.
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt.
* @arg SDIO_IT_RXACT: Data receive in progress interrupt.
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt.
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt.
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt.
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt.
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt.
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt.
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt.
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt.
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt.
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt.
* @param NewState: new state of the specified SDIO interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SDIO_IT(SDIO_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the SDIO interrupts */
SDIO->MASK |= SDIO_IT;
}
else
{
/* Disable the SDIO interrupts */
SDIO->MASK &= ~SDIO_IT;
}
}
/**
* @brief Checks whether the specified SDIO flag is set or not.
* @param SDIO_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed).
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed).
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout.
* @arg SDIO_FLAG_DTIMEOUT: Data timeout.
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error.
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error.
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed).
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required).
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero).
* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
* bus mode.
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed).
* @arg SDIO_FLAG_CMDACT: Command transfer in progress.
* @arg SDIO_FLAG_TXACT: Data transmit in progress.
* @arg SDIO_FLAG_RXACT: Data receive in progress.
* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty.
* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full.
* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full.
* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full.
* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty.
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty.
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO.
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO.
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received.
* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61.
* @retval The new state of SDIO_FLAG (SET or RESET).
*/
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_SDIO_FLAG(SDIO_FLAG));
if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the SDIO's pending flags.
* @param SDIO_FLAG: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed).
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed).
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout.
* @arg SDIO_FLAG_DTIMEOUT: Data timeout.
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error.
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error.
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed).
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required).
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero).
* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
* bus mode.
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed).
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received.
* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61.
* @retval None
*/
void SDIO_ClearFlag(uint32_t SDIO_FLAG)
{
/* Check the parameters */
assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
SDIO->ICR = SDIO_FLAG;
}
/**
* @brief Checks whether the specified SDIO interrupt has occurred or not.
* @param SDIO_IT: specifies the SDIO interrupt source to check.
* This parameter can be one of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt.
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt.
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt.
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt.
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt.
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt.
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
* bus mode interrupt.
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt.
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt.
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt.
* @arg SDIO_IT_RXACT: Data receive in progress interrupt.
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt.
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt.
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt.
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt.
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt.
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt.
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt.
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt.
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt.
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt.
* @retval The new state of SDIO_IT (SET or RESET).
*/
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
{
ITStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_SDIO_GET_IT(SDIO_IT));
if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the SDIO's interrupt pending bits.
* @param SDIO_IT: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt.
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt.
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt.
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt.
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt.
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt.
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
* bus mode interrupt.
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt.
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61.
* @retval None
*/
void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
{
/* Check the parameters */
assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
SDIO->ICR = SDIO_IT;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_spi.c
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FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_usart.c
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FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Libraries/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_wwdg.c
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/**
******************************************************************************
* @file stm32l1xx_wwdg.c
* @author MCD Application Team
* @version V1.1.1
* @date 05-March-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the Window watchdog (WWDG) peripheral:
* + Prescaler, Refresh window and Counter configuration
* + WWDG activation
* + Interrupts and flags management
*
* @verbatim
*
==============================================================================
##### WWDG features #####
==============================================================================
[..] Once enabled the WWDG generates a system reset on expiry of a programmed
time period, unless the program refreshes the counter (downcounter)
before to reach 0x3F value (i.e. a reset is generated when the counter
value rolls over from 0x40 to 0x3F).
[..] An MCU reset is also generated if the counter value is refreshed
before the counter has reached the refresh window value. This
implies that the counter must be refreshed in a limited window.
[..] Once enabled the WWDG cannot be disabled except by a system reset.
[..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
reset occurs.
[..] The WWDG counter input clock is derived from the APB clock divided
by a programmable prescaler.
[..] WWDG counter clock = PCLK1 / Prescaler.
[..] WWDG timeout = (WWDG counter clock) * (counter value).
[..] Min-max timeout value @32MHz (PCLK1): ~128us / ~65.6ms.
##### How to use this driver #####
==============================================================================
[..]
(#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE)
function.
(#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.
(#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.
(#) Set the WWDG counter value and start it using WWDG_Enable() function.
When the WWDG is enabled the counter value should be configured to
a value greater than 0x40 to prevent generating an immediate reset.
(#) Optionally you can enable the Early wakeup interrupt which is
generated when the counter reach 0x40.
Once enabled this interrupt cannot be disabled except by a system reset.
(#) Then the application program must refresh the WWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
WWDG_SetCounter() function. This operation must occur only when
the counter value is lower than the refresh window value,
programmed using WWDG_SetWindowValue().
* @endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_wwdg.h"
#include "stm32l1xx_rcc.h"
/** @addtogroup STM32L1xx_StdPeriph_Driver
* @{
*/
/** @defgroup WWDG
* @brief WWDG driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ----------- WWDG registers bit address in the alias region ----------- */
#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
/* Alias word address of EWI bit */
#define CFR_OFFSET (WWDG_OFFSET + 0x04)
#define EWI_BitNumber 0x09
#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
/* --------------------- WWDG registers bit mask ------------------------ */
/* CFR register bit mask */
#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)
#define CFR_W_MASK ((uint32_t)0xFFFFFF80)
#define BIT_MASK ((uint8_t)0x7F)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup WWDG_Private_Functions
* @{
*/
/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
* @brief Prescaler, Refresh window and Counter configuration functions
*
@verbatim
==============================================================================
##### Prescaler, Refresh window and Counter configuration functions #####
==============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the WWDG peripheral registers to their default reset values.
* @param None
* @retval None
*/
void WWDG_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
}
/**
* @brief Sets the WWDG Prescaler.
* @param WWDG_Prescaler: specifies the WWDG Prescaler.
* This parameter can be one of the following values:
* @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
* @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
* @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
* @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
* @retval None
*/
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
/* Clear WDGTB[1:0] bits */
tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
/* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
tmpreg |= WWDG_Prescaler;
/* Store the new value */
WWDG->CFR = tmpreg;
}
/**
* @brief Sets the WWDG window value.
* @param WindowValue: specifies the window value to be compared to the downcounter.
* This parameter value must be lower than 0x80.
* @retval None
*/
void WWDG_SetWindowValue(uint8_t WindowValue)
{
__IO uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
/* Clear W[6:0] bits */
tmpreg = WWDG->CFR & CFR_W_MASK;
/* Set W[6:0] bits according to WindowValue value */
tmpreg |= WindowValue & (uint32_t) BIT_MASK;
/* Store the new value */
WWDG->CFR = tmpreg;
}
/**
* @brief Enables the WWDG Early Wakeup interrupt(EWI).
* @note Once enabled this interrupt cannot be disabled except by a system reset.
* @param None
* @retval None
*/
void WWDG_EnableIT(void)
{
*(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
}
/**
* @brief Sets the WWDG counter value.
* @param Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F (to prevent generating
* an immediate reset).
* @retval None
*/
void WWDG_SetCounter(uint8_t Counter)
{
/* Check the parameters */
assert_param(IS_WWDG_COUNTER(Counter));
/* Write to T[6:0] bits to configure the counter value, no need to do
a read-modify-write; writing a 0 to WDGA bit does nothing */
WWDG->CR = Counter & BIT_MASK;
}
/**
* @}
*/
/** @defgroup WWDG_Group2 WWDG activation functions
* @brief WWDG activation functions
*
@verbatim
==============================================================================
##### WWDG activation function #####
==============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables WWDG and load the counter value.
* @param Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F (to prevent generating
* an immediate reset).
* @retval None
*/
void WWDG_Enable(uint8_t Counter)
{
/* Check the parameters */
assert_param(IS_WWDG_COUNTER(Counter));
WWDG->CR = WWDG_CR_WDGA | Counter;
}
/**
* @}
*/
/** @defgroup WWDG_Group3 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
==============================================================================
##### Interrupts and flags management functions #####
==============================================================================
@endverbatim
* @{
*/
/**
* @brief Checks whether the Early Wakeup interrupt flag is set or not.
* @param None
* @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
*/
FlagStatus WWDG_GetFlagStatus(void)
{
FlagStatus bitstatus = RESET;
if ((WWDG->SR) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears Early Wakeup interrupt flag.
* @param None
* @retval None
*/
void WWDG_ClearFlag(void)
{
WWDG->SR = (uint32_t)RESET;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file discover_board.h
* @author Microcontroller Division
* @version V1.0.3
* @date May-2013
* @brief Input/Output defines
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __DISCOVER_BOARD_H
#define __DISCOVER_BOARD_H
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
#define bool _Bool
#define FALSE 0
#define TRUE !FALSE
/* MACROs for SET, RESET or TOGGLE Output port */
#define GPIO_HIGH(a,b) a->BSRRL = b
#define GPIO_LOW(a,b) a->BSRRH = b
#define GPIO_TOGGLE(a,b) a->ODR ^= b
#define USERBUTTON_GPIO_PORT GPIOA
#define USERBUTTON_GPIO_PIN GPIO_Pin_0
#define USERBUTTON_GPIO_CLK RCC_AHBPeriph_GPIOA
#define LD_GPIO_PORT GPIOB
#define LD_GREEN_GPIO_PIN GPIO_Pin_7
#define LD_BLUE_GPIO_PIN GPIO_Pin_6
#define LD_GPIO_PORT_CLK RCC_AHBPeriph_GPIOB
#define CTN_GPIO_PORT GPIOC
#define CTN_CNTEN_GPIO_PIN GPIO_Pin_13
#define CTN_GPIO_CLK RCC_AHBPeriph_GPIOC
#define WAKEUP_GPIO_PORT GPIOA
#define IDD_MEASURE_PORT GPIOA
#define IDD_MEASURE GPIO_Pin_4
#endif
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32l_discovery_lcd.c
* @author Microcontroller Division
* @version V1.0.3
* @date May-2013
* @brief This file includes driver for the glass LCD Module mounted on
* STM32l discovery board MB963
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l_discovery_lcd.h"
#include "discover_board.h"
#include "stm32l1xx_lcd.h"
#include "main.h"
/* this variable can be used for accelerate the scrolling exit when push user button */
volatile bool KeyPressed = FALSE;
/* LCD BAR status: We don't write directly in LCD RAM for save the bar setting */
uint8_t t_bar[2]={0x0,0X0};
/* =========================================================================
LCD MAPPING
=========================================================================
A
_ ----------
COL |_| |\ |J /|
F| H | K |B
_ | \ | / |
COL |_| --G-- --M--
| /| \ |
E| Q | N |C
_ | / |P \|
DP |_| -----------
D
An LCD character coding is based on the following matrix:
{ E , D , P , N }
{ M , C , COL , DP}
{ B , A , K , J }
{ G , F , Q , H }
The character 'A' for example is:
-------------------------------
LSB { 1 , 0 , 0 , 0 }
{ 1 , 1 , 0 , 0 }
{ 1 , 1 , 0 , 0 }
MSB { 1 , 1 , 0 , 0 }
-------------------
'A' = F E 0 0 hexa
*/
/* Constant table for cap characters 'A' --> 'Z' */
const uint16_t CapLetterMap[26]=
{
/* A B C D E F G H I */
0xFE00,0x6714,0x1d00,0x4714,0x9d00,0x9c00,0x3f00,0xfa00,0x0014,
/* J K L M N O P Q R */
0x5300,0x9841,0x1900,0x5a48,0x5a09,0x5f00,0xFC00,0x5F01,0xFC01,
/* S T U V W X Y Z */
0xAF00,0x0414,0x5b00,0x18c0,0x5a81,0x00c9,0x0058,0x05c0
};
/* Constant table for number '0' --> '9' */
const uint16_t NumberMap[10]=
{
/* 0 1 2 3 4 5 6 7 8 9 */
0x5F00,0x4200,0xF500,0x6700,0xEa00,0xAF00,0xBF00,0x04600,0xFF00,0xEF00
};
static void LCD_Conv_Char_Seg(uint8_t* c,bool point,bool column,uint8_t* digit);
/**
* @brief Configures the LCD GLASS relative GPIO port IOs and LCD peripheral.
* @param None
* @retval None
*/
void LCD_GLASS_Init(void)
{
LCD_InitTypeDef LCD_InitStruct;
LCD_InitStruct.LCD_Prescaler = LCD_Prescaler_1;
LCD_InitStruct.LCD_Divider = LCD_Divider_31;
LCD_InitStruct.LCD_Duty = LCD_Duty_1_4;
LCD_InitStruct.LCD_Bias = LCD_Bias_1_3;
LCD_InitStruct.LCD_VoltageSource = LCD_VoltageSource_Internal;
/* Initialize the LCD */
LCD_Init(&LCD_InitStruct);
LCD_MuxSegmentCmd(ENABLE);
/* To set contrast to mean value */
LCD_ContrastConfig(LCD_Contrast_Level_4);
LCD_DeadTimeConfig(LCD_DeadTime_0);
LCD_PulseOnDurationConfig(LCD_PulseOnDuration_4);
/* Wait Until the LCD FCR register is synchronized */
LCD_WaitForSynchro();
/* Enable LCD peripheral */
LCD_Cmd(ENABLE);
/* Wait Until the LCD is enabled */
while(LCD_GetFlagStatus(LCD_FLAG_ENS) == RESET)
{
}
/*!< Wait Until the LCD Booster is ready */
while(LCD_GetFlagStatus(LCD_FLAG_RDY) == RESET)
{
}
LCD_BlinkConfig(LCD_BlinkMode_Off,LCD_BlinkFrequency_Div32);
LCD_GLASS_Clear();
}
/**
* @brief To initialize the LCD pins
* @caller main
* @param None
* @retval None
*/
void LCD_GLASS_Configure_GPIO(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
/* Enable GPIOs clock */
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC |
RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE | RCC_AHBPeriph_GPIOH, ENABLE);
/* Configure Output for LCD */
/* Port A */
GPIO_StructInit(&GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_8 | GPIO_Pin_9 |GPIO_Pin_10 |GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_Init( GPIOA, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource1,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOA, GPIO_PinSource2,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOA, GPIO_PinSource3,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOA, GPIO_PinSource8,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOA, GPIO_PinSource9,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOA, GPIO_PinSource10,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOA, GPIO_PinSource15,GPIO_AF_LCD) ;
/* Configure Output for LCD */
/* Port B */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 \
| GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_Init( GPIOB, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOB, GPIO_PinSource3,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOB, GPIO_PinSource4,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOB, GPIO_PinSource5,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOB, GPIO_PinSource8,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOB, GPIO_PinSource9,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOB, GPIO_PinSource10,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOB, GPIO_PinSource11,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOB, GPIO_PinSource12,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOB, GPIO_PinSource13,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOB, GPIO_PinSource14,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOB, GPIO_PinSource15,GPIO_AF_LCD) ;
/* Configure Output for LCD */
/* Port C*/
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6 \
| GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |GPIO_Pin_11 ;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_Init( GPIOC, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource0,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOC, GPIO_PinSource1,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOC, GPIO_PinSource2,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOC, GPIO_PinSource3,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOC, GPIO_PinSource6,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOC, GPIO_PinSource7,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOC, GPIO_PinSource8,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOC, GPIO_PinSource9,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOC, GPIO_PinSource10,GPIO_AF_LCD) ;
GPIO_PinAFConfig(GPIOC, GPIO_PinSource11,GPIO_AF_LCD) ;
/* Disable GPIOs clock */
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC |
RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE | RCC_AHBPeriph_GPIOH, DISABLE);
}
/**
* @brief LCD contrast setting min-->max-->min by pressing user button
* @param None
* @retval None
*/
void LCD_contrast()
{
uint32_t contrast ;
/* To get the actual contrast value in register */
contrast = LCD->FCR & LCD_Contrast_Level_7;
while ((GPIOC->IDR & USERBUTTON_GPIO_PIN) == 0x0)
{
contrast += LCD_Contrast_Level_1;
if (contrast > LCD_Contrast_Level_7)
contrast=LCD_Contrast_Level_0;
LCD_ContrastConfig(contrast);
Delay(100);
}
}
/**
* @brief Setting bar on LCD, writes bar value in LCD frame buffer
* @param None
* @retval None
*/
void LCD_bar()
{
LCD->RAM[LCD_RAMRegister_4] &= 0xffff5fff;
LCD->RAM[LCD_RAMRegister_6] &= 0xffff5fff;
/* bar1 bar3 */
LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)(t_bar[0]<<12);
/*bar0 bar2 */
LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)(t_bar[1]<<12);
}
/**
* @brief Converts an ascii char to the a LCD digit.
* @param c: a char to display.
* @param point: a point to add in front of char
* This parameter can be: POINT_OFF or POINT_ON
* @param column : flag indicating if a column has to be add in front
* of displayed character.
* This parameter can be: COLUMN_OFF or COLUMN_ON.
* @param digit array with segment
* @retval None
*/
static void LCD_Conv_Char_Seg(uint8_t* c,bool point,bool column, uint8_t* digit)
{
uint16_t ch = 0 ;
uint8_t i,j;
switch (*c)
{
case ' ' :
ch = 0x00;
break;
case '*':
ch = star;
break;
case 'µ' :
ch = C_UMAP;
break;
case 'm' :
ch = C_mMap;
break;
case 'n' :
ch = C_nMap;
break;
case '-' :
ch = C_minus;
break;
case '/' :
ch = C_slatch;
break;
case '°' :
ch = C_percent_1;
break;
case '%' :
ch = C_percent_2;
break;
case 255 :
ch = C_full;
break ;
case '0':
case '1':
case '2':
case '3':
case '4':
case '5':
case '6':
case '7':
case '8':
case '9':
ch = NumberMap[*c-0x30];
break;
default:
/* The character c is one letter in upper case*/
if ( (*c < 0x5b) && (*c > 0x40) )
{
ch = CapLetterMap[*c-'A'];
}
/* The character c is one letter in lower case*/
if ( (*c <0x7b) && ( *c> 0x60) )
{
ch = CapLetterMap[*c-'a'];
}
break;
}
/* Set the digital point can be displayed if the point is on */
if (point)
{
ch |= 0x0002;
}
/* Set the "COL" segment in the character that can be displayed if the column is on */
if (column)
{
ch |= 0x0020;
}
for (i = 12,j=0 ;j<4; i-=4,j++)
{
digit[j] = (ch >> i) & 0x0f; //To isolate the less signifiant dibit
}
}
/**
* @brief This function writes a char in the LCD frame buffer.
* @param ch: the character to display.
* @param point: a point to add in front of char
* This parameter can be: POINT_OFF or POINT_ON
* @param column: flag indicating if a column has to be add in front
* of displayed character.
* This parameter can be: COLUMN_OFF or COLUMN_ON.
* @param position: position in the LCD of the caracter to write [0:7]
* @retval None
* @par Required preconditions: The LCD should be cleared before to start the
* write operation.
*/
void LCD_GLASS_WriteChar(uint8_t* ch, bool point, bool column, uint8_t position)
{
uint8_t digit[4]; /* Digit frame buffer */
/* To convert displayed character in segment in array digit */
LCD_Conv_Char_Seg(ch,point,column,digit);
switch (position)
{
/* Position 1 on LCD (Digit1)*/
case 1:
LCD->RAM[LCD_RAMRegister_0] &= 0xcffffffc;
LCD->RAM[LCD_RAMRegister_2] &= 0xcffffffc;
LCD->RAM[LCD_RAMRegister_4] &= 0xcffffffc;
LCD->RAM[LCD_RAMRegister_6] &= 0xcffffffc;
LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 26 ) | (digit[0]& 0x03) ; // 1G 1B 1M 1E
LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 26 ) | (digit[1]& 0x03) ; // 1F 1A 1C 1D
LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 26 ) | (digit[2]& 0x03) ; // 1Q 1K 1Col 1P
LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 26 ) | (digit[3]& 0x03) ; // 1H 1J 1DP 1N
break;
/* Position 2 on LCD (Digit2)*/
case 2:
LCD->RAM[LCD_RAMRegister_0] &= 0xf3ffff03;
LCD->RAM[LCD_RAMRegister_2] &= 0xf3ffff03;
LCD->RAM[LCD_RAMRegister_4] &= 0xf3ffff03;
LCD->RAM[LCD_RAMRegister_6] &= 0xf3ffff03;
LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 24 )|((digit[0]& 0x02) << 6 )|((digit[0]& 0x01) << 2 ) ; // 2G 2B 2M 2E
LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 24 )|((digit[1]& 0x02) << 6 )|((digit[1]& 0x01) << 2 ) ; // 2F 2A 2C 2D
LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 24 )|((digit[2]& 0x02) << 6 )|((digit[2]& 0x01) << 2 ) ; // 2Q 2K 2Col 2P
LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 24 )|((digit[3]& 0x02) << 6 )|((digit[3]& 0x01) << 2 ) ; // 2H 2J 2DP 2N
break;
/* Position 3 on LCD (Digit3)*/
case 3:
LCD->RAM[LCD_RAMRegister_0] &= 0xfcfffcff;
LCD->RAM[LCD_RAMRegister_2] &= 0xfcfffcff;
LCD->RAM[LCD_RAMRegister_4] &= 0xfcfffcff;
LCD->RAM[LCD_RAMRegister_6] &= 0xfcfffcff;
LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 22 ) | ((digit[0]& 0x03) << 8 ) ; // 3G 3B 3M 3E
LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 22 ) | ((digit[1]& 0x03) << 8 ) ; // 3F 3A 3C 3D
LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 22 ) | ((digit[2]& 0x03) << 8 ) ; // 3Q 3K 3Col 3P
LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 22 ) | ((digit[3]& 0x03) << 8 ) ; // 3H 3J 3DP 3N
break;
/* Position 4 on LCD (Digit4)*/
case 4:
LCD->RAM[LCD_RAMRegister_0] &= 0xffcff3ff;
LCD->RAM[LCD_RAMRegister_2] &= 0xffcff3ff;
LCD->RAM[LCD_RAMRegister_4] &= 0xffcff3ff;
LCD->RAM[LCD_RAMRegister_6] &= 0xffcff3ff;
LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 18 ) | ((digit[0]& 0x03) << 10 ) ; // 4G 4B 4M 4E
LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 18 ) | ((digit[1]& 0x03) << 10 ) ; // 4F 4A 4C 4D
LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 18 ) | ((digit[2]& 0x03) << 10 ) ; // 4Q 4K 4Col 4P
LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 18 ) | ((digit[3]& 0x03) << 10 ) ; // 4H 4J 4DP 4N
break;
/* Position 5 on LCD (Digit5)*/
case 5:
LCD->RAM[LCD_RAMRegister_0] &= 0xfff3cfff;
LCD->RAM[LCD_RAMRegister_2] &= 0xfff3cfff;
LCD->RAM[LCD_RAMRegister_4] &= 0xfff3efff;
LCD->RAM[LCD_RAMRegister_6] &= 0xfff3efff;
LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 16 ) | ((digit[0]& 0x03) << 12 ) ; // 5G 5B 5M 5E
LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 16 ) | ((digit[1]& 0x03) << 12 ) ; // 5F 5A 5C 5D
LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 16 ) | ((digit[2]& 0x01) << 12 ) ; // 5Q 5K 5P
LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 16 ) | ((digit[3]& 0x01) << 12 ) ; // 5H 5J 5N
break;
/* Position 6 on LCD (Digit6)*/
case 6:
LCD->RAM[LCD_RAMRegister_0] &= 0xfffc3fff;
LCD->RAM[LCD_RAMRegister_2] &= 0xfffc3fff;
LCD->RAM[LCD_RAMRegister_4] &= 0xfffc3fff;
LCD->RAM[LCD_RAMRegister_6] &= 0xfffc3fff;
LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x04) << 15 ) | ((digit[0]& 0x08) << 13 ) | ((digit[0]& 0x03) << 14 ) ; // 6B 6G 6M 6E
LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x04) << 15 ) | ((digit[1]& 0x08) << 13 ) | ((digit[1]& 0x03) << 14 ) ; // 6A 6F 6C 6D
LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x04) << 15 ) | ((digit[2]& 0x08) << 13 ) | ((digit[2]& 0x01) << 14 ) ; // 6K 6Q 6P
LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x04) << 15 ) | ((digit[3]& 0x08) << 13 ) | ((digit[3]& 0x01) << 14 ) ; // 6J 6H 6N
break;
default:
break;
}
/* Refresh LCD bar */
LCD_bar();
}
/**
* @brief This function writes a char in the LCD RAM.
* @param ptr: Pointer to string to display on the LCD Glass.
* @retval None
*/
void LCD_GLASS_DisplayString(uint8_t* ptr)
{
uint8_t i = 0x01;
/* wait for LCD Ready */
while( LCD_GetFlagStatus (LCD_FLAG_UDR) != RESET) ;
/* Send the string character by character on lCD */
while ((*ptr != 0) & (i < 8))
{
/* Display one character on LCD */
LCD_GLASS_WriteChar(ptr, FALSE, FALSE, i);
/* Point on the next character */
ptr++;
/* Increment the character counter */
i++;
}
/* Update the LCD display */
LCD_UpdateDisplayRequest();
}
/**
* @brief This function writes a char in the LCD RAM.
* @param ptr: Pointer to string to display on the LCD Glass.
* @retval None
* @par Required preconditions: Char is ASCCI value "Ored" with decimal point or Column flag
*/
void LCD_GLASS_DisplayStrDeci(uint16_t* ptr)
{
uint8_t i = 0x01;
uint8_t char_tmp;
/* TO wait LCD Ready */
while( LCD_GetFlagStatus (LCD_FLAG_UDR) != RESET) ;
/* Send the string character by character on lCD */
while ((*ptr != 0) & (i < 8))
{
char_tmp = (*ptr) & 0x00ff;
switch ((*ptr) & 0xf000)
{
case DOT:
/* Display one character on LCD with decimal point */
LCD_GLASS_WriteChar(&char_tmp, POINT_ON, COLUMN_OFF, i);
break;
case DOUBLE_DOT:
/* Display one character on LCD with decimal point */
LCD_GLASS_WriteChar(&char_tmp, POINT_OFF, COLUMN_ON, i);
break;
default:
LCD_GLASS_WriteChar(&char_tmp, POINT_OFF, COLUMN_OFF, i);
break;
}/* Point on the next character */
ptr++;
/* Increment the character counter */
i++;
}
/* Update the LCD display */
LCD_UpdateDisplayRequest();
}
/**
* @brief This function Clear the whole LCD RAM.
* @param None
* @retval None
*/
void LCD_GLASS_Clear(void)
{
uint32_t counter = 0;
/* TO wait LCD Ready */
while( LCD_GetFlagStatus (LCD_FLAG_UDR) != RESET) ;
for (counter = LCD_RAMRegister_0; counter <= LCD_RAMRegister_15; counter++)
{
LCD->RAM[counter] = 0;
}
/* Update the LCD display */
LCD_UpdateDisplayRequest();
}
/**
* @brief Display a string in scrolling mode
* @param ptr: Pointer to string to display on the LCD Glass.
* @param nScroll: Specifies how many time the message will be scrolled
* @param ScrollSpeed : Speciifes the speed of the scroll, low value gives
* higher speed
* @retval None
* @par Required preconditions: The LCD should be cleared before to start the
* write operation.
*/
void LCD_GLASS_ScrollSentence(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed)
{
uint8_t Repetition;
uint8_t Char_Nb;
uint8_t* ptr1;
uint8_t str[7]="";
uint8_t Str_size;
if (ptr == 0) return;
/* To calculate end of string */
for (ptr1=ptr,Str_size = 0 ; *ptr1 != 0; Str_size++,ptr1++) ;
ptr1 = ptr;
LCD_GLASS_DisplayString(ptr);
Delay(ScrollSpeed);
/* To shift the string for scrolling display*/
for (Repetition=0; Repetition<nScroll; Repetition++)
{
for (Char_Nb=0; Char_Nb<Str_size; Char_Nb++)
{
*(str) =* (ptr1+((Char_Nb+1)%Str_size));
*(str+1) =* (ptr1+((Char_Nb+2)%Str_size));
*(str+2) =* (ptr1+((Char_Nb+3)%Str_size));
*(str+3) =* (ptr1+((Char_Nb+4)%Str_size));
*(str+4) =* (ptr1+((Char_Nb+5)%Str_size));
*(str+5) =* (ptr1+((Char_Nb+6)%Str_size));
LCD_GLASS_Clear();
LCD_GLASS_DisplayString(str);
/* user button pressed stop the scrolling sentence */
if (KeyPressed)
return;
Delay(ScrollSpeed);
}
}
}
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

127
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/ST_Code/Utilities/STM32L-DISCOVERY/stm32l_discovery_lcd.h
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@ -1,127 +0,0 @@
/**
******************************************************************************
* @file stm32l_discovery_lcd.h
* @author Microcontroller Division
* @version V1.0.3
* @date May-2013
* @brief This file contains all the functions prototypes for the glass LCD
* firmware driver.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __stm32l_discovery_lcd
#define __stm32l_discovery_lcd
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
#include "discover_board.h"
/* Define for scrolling sentences*/
#define SCROLL_SPEED 75
#define SCROLL_SPEED_L 600
#define SCROLL_NUM 1
/* Define for character '.' */
#define POINT_OFF FALSE
#define POINT_ON TRUE
/* Define for caracter ":" */
#define COLUMN_OFF FALSE
#define COLUMN_ON TRUE
#define DOT 0x8000 /* for add decimal point in string */
#define DOUBLE_DOT 0x4000 /* for add decimal point in string */
/* =========================================================================
LCD MAPPING
=========================================================================
A
_ ----------
COL |_| |\ |J /|
F| H | K |B
_ | \ | / |
COL |_| --G-- --M--
| /| \ |
E| Q | N |C
_ | / |P \|
DP |_| -----------
D
An LCD character coding is based on the following matrix:
{ E , D , P , N }
{ M , C , COL , DP}
{ B , A , K , J }
{ G , F , Q , H }
The character 'A' for example is:
-------------------------------
LSB { 1 , 0 , 0 , 0 }
{ 1 , 1 , 0 , 0 }
{ 1 , 1 , 0 , 0 }
MSB { 1 , 1 , 0 , 0 }
-------------------
'A' = F E 0 0 hexa
*/
/* Macros used for set/reset bar LCD bar */
#define BAR0_ON t_bar[1] |= 8
#define BAR0_OFF t_bar[1] &= ~8
#define BAR1_ON t_bar[0] |= 8
#define BAR1_OFF t_bar[0] &= ~8
#define BAR2_ON t_bar[1] |= 2
#define BAR2_OFF t_bar[1] &= ~2
#define BAR3_ON t_bar[0] |= 2
#define BAR3_OFF t_bar[0] &= ~2
/* code for 'µ' character */
#define C_UMAP 0x6084
/* code for 'm' character */
#define C_mMap 0xb210
/* code for 'n' character */
#define C_nMap 0x2210
/* constant code for '*' character */
#define star 0xA0DD
/* constant code for '-' character */
#define C_minus 0xA000
/* constant code for '/' */
#define C_slatch 0x00c0
/* constant code for ° */
#define C_percent_1 0xec00
/* constant code for small o */
#define C_percent_2 0xb300
#define C_full 0xffdd
void LCD_bar(void);
void LCD_GLASS_Init(void);
void LCD_GLASS_WriteChar(uint8_t* ch, bool point, bool column,uint8_t position);
void LCD_GLASS_DisplayString(uint8_t* ptr);
void LCD_GLASS_DisplayStrDeci(uint16_t* ptr);
void LCD_GLASS_ClearChar(uint8_t position);
void LCD_GLASS_Clear(void);
void LCD_GLASS_ScrollSentence(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed);
void LCD_GLASS_WriteTime(char a, uint8_t posi, bool column);
void LCD_GLASS_Configure_GPIO(void);
#endif /* stm32l_discovery_lcd*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

683
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/discover_functions.c
View file

@ -1,683 +0,0 @@
/**
******************************************************************************
* @file discover_functions.c
* @author Microcontroller Division
* @version V1.0.3
* @date May-2013
* @brief Discover demo functions
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
/* stm32l1xxx std peripheral drivers headers*/
#include "stm32l1xx_exti.h"
#include "misc.h"
/* touch sensing library headers*/
//#include "stm32_tsl_api.h" -- superseded
//#include "stm32l15x_tsl_ct_acquisition.h" -- superseded
#include "tsl.h"
#include "tsl_user.h"
/* discover application headers*/
#include "discover_board.h"
#include "discover_functions.h"
#include "stm32l_discovery_lcd.h"
#include "icc_measure.h"
/*Variables placed in DataFlash */
/* ADC converter value for Bias current value*/
#if (defined ( __CC_ARM ))
uint8_t Bias_Current __attribute__((at(0x08080000)));
#elif (defined (__ICCARM__))
uint8_t Bias_Current @ ".DataFlash" ;
#elif (defined (__GNUC__))
/* ADC converter value for Bias current value*/
uint8_t Bias_Current __attribute__((section(".DataFlash")));
#endif
/* Flag for autotest placed in Data Flash for return from RESET after STANDBY */
#if (defined ( __CC_ARM ))
bool self_test __attribute__((at(0x08080004)));
#elif (defined (__ICCARM__))
bool self_test @ ".DataFlash" ;
#elif (defined (__GNUC__))
/* Flag for autotest placed in Data Flash for return from RESET after STANDBY */
bool self_test __attribute__((section(".DataFlash")));
#endif
extern float Current_STBY;
extern uint8_t t_bar[2];
extern uint16_t Int_CurrentSTBY;
/* Used for indicate that the automatic test is ON (set in interrupt handler).*/
/* To indicate if user button function is actived*/
bool UserButton ;
/* Used for detect keypressed*/
extern volatile bool KeyPressed;
/**
* @brief automatic test for VDD
* @caller auto_test
* @param None
* @retval None
*/
void test_vdd(void)
{
uint16_t vdd_test;
uint16_t Message[6];
/* Display test name*/
LCD_GLASS_DisplayString(" VDD ");
DELAY;
/* get VDD voltage value */
vdd_test = (int)Vref_measure();
DELAY;
/* Check if value is correct */
if ((vdd_test>VCC_MAX) || (vdd_test<VCC_MIN))
{
/* if not correct stay in following infinit loop -- Press reset for exit */
while(1)
{
/* Display VDD ERROR message*/
LCD_GLASS_ScrollSentence("VDD ERROR ",1,SCROLL_SPEED);
DELAY;
/*convert vdd_test value in char and stor it into Message */
convert_into_char (vdd_test, Message);
/* Add unit and decimal point to Message */
Message[5] = 'V';
Message[4] = ' ';
Message[1] |= DOT;
Message[0] = ' ';
/*Display Message*/
LCD_GLASS_DisplayStrDeci(Message);
DELAY;
DELAY;
}
}
/* Display VDD OK message*/
LCD_GLASS_DisplayString("VDD OK");
DELAY ;
}
/**
* @brief Automatic test current in Run Mode
* @caller auto_test
* @param None
* @retval None
*/
void test_icc_Run(void)
{
uint16_t icc_test;
uint16_t Message[6];
/* Display test name*/
LCD_GLASS_DisplayString("RUN ");
DELAY;
/* get ICC current value in RUN mode*/
icc_test = (int)Icc_RUN();
DELAY;
/* Check if value is correct */
if ((icc_test>ICC_RUN_MAX) || (icc_test<ICC_RUN_MIN))
{
/* if not correct stay in following infinit loop -- Press reset for exit */
while (1)
{
KeyPressed = FALSE;
/* Display RUN ERROR message*/
LCD_GLASS_ScrollSentence("RUN ERROR ",1,SCROLL_SPEED);
DELAY;
/*convert icc_test value in char and stor it into tab */
convert_into_char((uint32_t)(icc_test), Message);
/* Add unit and decimal point to Message */
Message[5] = 'A';
Message[4] = 'm';
Message[3] = ' ';
Message[0] |= DOT;
/*Display Message*/
LCD_GLASS_DisplayStrDeci(Message);
DELAY;
DELAY;
}
}
/* Display RUN OK message*/
LCD_GLASS_DisplayString("RUN OK");
DELAY;
}
/**
* @brief Automatic test bias value
* @caller auto_test
* @param None
* @retval None
*/
void test_Bias(void)
{
float Current = 0;
/* Display test name*/
LCD_GLASS_DisplayString("BIAS ");
DELAY;
/* Get operational amplifier BIAS current value*/
Current = Bias_Current * Vdd_appli()/ADC_CONV;
Current *= 20L;
display_MuAmp((uint32_t)Current);
DELAY;
/* Check if value is correct */
if ((Bias_Current > ICC_BIAS_MAX) || (Bias_Current == 0 ))
{
/* if not correct stay in following infinit loop */
while (1)
{
KeyPressed = FALSE;
/* Display BIAS ERROR message and BIAS current*/
LCD_GLASS_ScrollSentence("BIAS ERROR ",1,SCROLL_SPEED);
DELAY;
display_MuAmp((uint32_t)Current);
DELAY;
DELAY;
}
}
/* Display BIAS OK message*/
LCD_GLASS_DisplayString("BIASOK");
DELAY;
}
/**
* @brief Automatic test current in STOP Mode
* @caller auto_test
* @param None
* @retval None
*/
void test_icc_STOP(void)
{
uint16_t icc_test;
/* Display test name*/
LCD_GLASS_DisplayString("STOP ");
DELAY;
/* Get operational Icc current value in Stop mode no RTC*/
icc_test = (int)Icc_Stop_NoRTC();
DELAY;
/* Test if value is correct */
if ((icc_test>ICC_STOP_MAX) || (icc_test<ICC_STOP_MIN))
{
/* if not correct stay in following infinite loop */
while (1)
{
KeyPressed = FALSE;
/* Display ICC STOP ERROR message*/
LCD_GLASS_ScrollSentence("ICC STOP ERROR ",1,SCROLL_SPEED);
DELAY;
/* Display ICC STOPvalue*/
display_MuAmp((uint32_t)icc_test);
DELAY;
DELAY;
}
}
/* Display STOP OK message*/
LCD_GLASS_DisplayString("STOPOK");
DELAY;
}
/**
* @brief Automatic test current in STBY Mode
* @caller auto_test
* @param None
* @retval None
*/
void test_icc_STBY(void)
{
/* Display test name*/
LCD_GLASS_DisplayString("STBY ");
DELAY;
/* Current value measured in Standby mode*/
ADC_Icc_Test(MCU_STBY);
/* No Return software reset performed in ADC_Icc_Test function */
}
/**
* @brief Run auto test
* @caller main
* @param None
* @retval None
*/
void auto_test(void)
{
uint16_t tab[6]={0x20,0x20,0x20,0x20,0x20,0x20};
AUTOTEST(TRUE) ;
/* Switch off leds*/
GPIO_LOW(LD_GPIO_PORT,LD_GREEN_GPIO_PIN);
GPIO_LOW(LD_GPIO_PORT,LD_BLUE_GPIO_PIN);
/* reset LCD bar indicator*/
BAR0_OFF;
BAR1_OFF;
BAR2_OFF;
BAR3_OFF;
/* To display version */
LCD_GLASS_DisplayString(" TEST ");
DELAY;
STR_VERSION;
LCD_GLASS_DisplayStrDeci(tab);
DELAY;
DELAY;
/* And launch the tests*/
test_vdd();
test_icc_Run();
test_Bias();
test_icc_STOP();
test_icc_STBY();
/* Infinite loop: Press reset button at the end of test for exit*/
while (1)
{
LCD_GLASS_ScrollSentence("TEST OK ",1,SCROLL_SPEED);
KeyPressed = FALSE;
}
}
/**
* @brief Second part of Run auto test (run after sw reset)
* @caller main after RESET
* @param None
* @retval None
*/
void auto_test_part2(void)
{
float Current_STBY;
/* Substract operational amplifier bias current from mesured standby current*/
if ( Int_CurrentSTBY > Bias_Current )
Int_CurrentSTBY -= Bias_Current;
/* convert value in uA */
Current_STBY = Int_CurrentSTBY * Vdd_appli()/ADC_CONV;
Current_STBY *= 20L;
/*Display Standby Icc current value*/
display_MuAmp((uint32_t)Current_STBY);
DELAY;
/* Test if value is correct */
if ((Current_STBY > ICC_STBY_MAX) || (Current_STBY < ICC_STBY_MIN))
{
/* if not correct stay in following infinite loop */
while (1)
{
KeyPressed = FALSE;
/* Display ICC STBY error message */
LCD_GLASS_ScrollSentence("ICC STBY ERROR ",1,SCROLL_SPEED);
DELAY;
/* Display ICC STBY current */
display_MuAmp((uint32_t)Current_STBY);
DELAY;
DELAY;
}
}
/* Display ICC STBY test OK*/
LCD_GLASS_DisplayString("STBYOK");
DELAY;
/* Infinite loop: Press reset button at the end of autotest to restart application*/
while (1)
{
LCD_GLASS_ScrollSentence("TEST OK ",1,SCROLL_SPEED);
KeyPressed = FALSE;
}
}
/**
* @brief Measures the BIAS current PJ1 Must be on OFF position
* @caller main
* @param None
* @retval None
*/
void Bias_measurement(void)
{
float Current;
uint16_t MeasurINT;
/* indicate that applicartion run in ** BIAS CURRENT ** mode */
LCD_GLASS_ScrollSentence(" ** BIAS CURRENT ** JP1 OFF **",1,SCROLL_SPEED);
/* Get operational amplifier Bias current value */
MeasurINT = ADC_Icc_Test(MCU_STOP_NoRTC);
/* convert mesured value in uA*/
Current = MeasurINT * Vdd_appli()/ADC_CONV;
Current *= 20L;
/*display bias current value */
display_MuAmp((uint32_t)Current);
/* unlock E²Prom write access*/
DATA_EEPROM_Unlock();
/* Store the value in E²Prom for application needs*/
DATA_EEPROM_FastProgramByte((uint32_t)&Bias_Current, MeasurINT) ;
/* Lock back E²PROM write access */
DATA_EEPROM_Lock();
/* Infinite loop: BIAS current display -- Press reset button in order to restart application*/
while (1)
{
/* Get operational amplifier Bias current value */
MeasurINT = ADC_Icc_Test(MCU_STOP_NoRTC);
/* convert mesured value in uA*/
Current = MeasurINT * Vdd_appli()/ADC_CONV;
Current *= 20L;
/*display bias current value */
display_MuAmp((uint32_t)Current);
Delay(800) ;
}
}
/**
* @brief converts a 32bit unsined int into ASCII
* @caller several callers for display values
* @param Number digit to displays
* p_tab values in array in ASCII
* @retval None
*/
void convert_into_char(uint32_t number, uint16_t *p_tab)
{
uint16_t units=0, tens=0, hundreds=0, thousands=0, misc=0;
units = (((number%10000)%1000)%100)%10;
tens = ((((number-units)/10)%1000)%100)%10;
hundreds = (((number-tens-units)/100))%100%10;
thousands = ((number-hundreds-tens-units)/1000)%10;
misc = ((number-thousands-hundreds-tens-units)/10000);
*(p_tab+4) = units + 0x30;
*(p_tab+3) = tens + 0x30;
*(p_tab+2) = hundreds + 0x30;
*(p_tab+1) = thousands + 0x30;
*(p_tab) = misc + 0x30;
}
/**
* @brief Function to return the VDD measurement
* @caller All measurements: VDD display or Current
*
* Method for VDD measurement:
* The VREFINT is not stored in memory.
* In this case:
* Vdd_appli = (Theorical_Vref/Vref mesure) * ADC_Converter
* Theorical_Vref = 1.224V
* ADC_Converter 4096
* ---> LSBIdeal = VREF/4096 or VDA/4096
* @param None
* @retval VDD measurements
*/
float Vdd_appli(void)
{
uint16_t MeasurINT ;
float f_Vdd_appli ;
/*Read the BandGap value on ADC converter*/
MeasurINT = ADC_Supply();
/* We use the theorical value */
f_Vdd_appli = (VREF/MeasurINT) * ADC_CONV;
/* convert Vdd_appli into mV */
f_Vdd_appli *= 1000L;
return f_Vdd_appli;
}
/**
* @brief Function to measure VDD
* @caller main
* @param None
* @retval Vdd value in mV
*/
uint16_t Vref_measure(void)
{
uint16_t tab[6];
uint16_t Vdd_mV ;
Vdd_mV = (uint16_t)Vdd_appli();
convert_into_char (Vdd_mV, tab);
/* To add unit and decimal point */
tab[5] = 'V';
tab[4] = ' ';
tab[1] |= DOT; /* To add decimal point for display in volt */
tab[0] = ' ';
LCD_GLASS_DisplayStrDeci(tab);
return Vdd_mV;
}
/**
* @brief funtion to display the current in µA
* @caller several funcions
* @param Current value.
* @retval none
*/
void display_MuAmp (uint32_t Current)
{
uint16_t tab[6];
convert_into_char(Current, tab);
tab[5] = 'A';
tab[4] = 'µ';
/* Test the significant digit for displays 3 or 4 digits*/
if ( tab[0] != '0')
{
tab[1] |= DOT; /* To add decimal point */
} else {
/* To shift for suppress '0' before decimal */
tab[0] = tab[1] ;
tab[0] |= DOT ;
tab[1] = tab[2] ;
tab[2] = tab[3] ;
tab[3] = ' ';
}
LCD_GLASS_DisplayStrDeci(tab);
}
/**
* @brief funtion Current measurement in RUN mode
* @caller main and test_icc_RUN
* @param none
* @retval Current (mA)
*/
float Icc_RUN(void)
{
float Current;
uint16_t MeasurINT;
uint16_t tab[6];
/* Get Icc current value in Run mode*/
MeasurINT = ADC_Icc_Test(MCU_RUN);
/* Convert value in mA*/
Current = MeasurINT * Vdd_appli()/ADC_CONV;
Current *= 100L;
/* Convert value in ASCII and store it into tab*/
convert_into_char((uint32_t)(Current), tab);
/* Add unit and decimal point */
tab[5] = 'A';
tab[4] = 'm';
tab[3] = ' ';
tab[0] |= DOT;
/* Display mesured value */
LCD_GLASS_DisplayStrDeci(tab);
return (Current);
}
/**
* @brief funtion Current measurement in SLEEP mode
* @caller main
* @param none
* @retval Current (mA)
*/
float Icc_SLEEP(void)
{
float Current;
uint16_t MeasurINT;
uint16_t tab[6];
/* Get Icc current value in Sleep mode*/
MeasurINT = ADC_Icc_Test(MCU_SLEEP);
/* Substract operational amplifier bias current from value*/
Current = MeasurINT * Vdd_appli()/ADC_CONV;
/* Convert value in mA*/
Current *= 100L;
/* Convert value in ASCII and store it into tab*/
convert_into_char((uint32_t)(Current), tab);
/* Add unit and decimal point */
tab[5] = 'A';
tab[4] = 'm';
tab[3] = ' ';
tab[0] |= DOT;
/*Display mesured value */
LCD_GLASS_DisplayStrDeci(tab);
/* Return value in mA*/
return(Current);
}
/**
* @brief funtion Current measurement in Low power
* @caller main
* @param none
* @retval Current (uA)
*/
float Icc_LPRUN(void)
{
float Current;
uint16_t MeasurINT;
/* Get Icc current value in Low power mode*/
MeasurINT = ADC_Icc_Test(MCU_LP_RUN);
/* Substract operational amplifier bias current from value*/
if ( MeasurINT > Bias_Current )
MeasurINT -= Bias_Current;
/* Convert value in uA*/
Current = MeasurINT * Vdd_appli()/ADC_CONV;
Current *= 20L;
/* Display mesured value */
display_MuAmp((uint32_t)Current);
/* Return value in uA*/
return(Current);
}
/**
* @brief funtion Current measurement in Low power
* @caller main
* @param none
* @retval Current (µA)
*/
float Icc_LPSLEEP(void)
{
float Current;
uint16_t MeasurINT;
/* Get Icc current value in Low power sleep mode*/
MeasurINT = ADC_Icc_Test(MCU_LP_SLEEP);
/* Substract operational amplifier bias current from value*/
if ( MeasurINT > Bias_Current )
MeasurINT -= Bias_Current;
/* Convert value in uA*/
Current = MeasurINT * Vdd_appli()/ADC_CONV;
Current *= 20L;
/* Test if value is correct */
if ((int) Current<MAX_CURRENT)
{
/* if correct : Display mesured value */
display_MuAmp((uint32_t)Current);
} else{
/* if not correct : Display ERROR */
LCD_GLASS_Clear();
LCD_GLASS_DisplayString("Error");
}
/* Return value in uA*/
return(Current);
}
/**
* @brief funtion Current measurement in Stop mode with LCD ON
* @caller main and test_icc_LCD
* @param none
* @retval Current (µA)
*/
float Icc_STOP(void)
{
float Current;
uint16_t MeasurINT;
/* Get Icc current value in STOP mode*/
MeasurINT = ADC_Icc_Test(MCU_STOP_RTC);
/* Substract operational amplifier bias current from value*/
if ( MeasurINT > Bias_Current )
MeasurINT -= Bias_Current;
/* Convert value in uA*/
Current = MeasurINT * Vdd_appli()/ADC_CONV;
Current *= 20L;
/* test if value is correct */
if ((int) Current<MAX_CURRENT)
{
/* if correct : Display mesured value */
display_MuAmp((uint32_t)Current);
}
else
{
/* if not correct : Display error if not in autotest */
if (!self_test)
{
LCD_GLASS_Clear();
LCD_GLASS_DisplayString("Error");
}
}
/* Return value in uA*/
return (Current);
}
/**
* @brief funtion Current measurement in Stop mode with LCD OFF
* @caller main
* @param none
* @retval none
*/
float Icc_Stop_NoRTC(void)
{
float Current;
uint16_t MeasurINT;
/* Get Icc current value in STOP mode with no RTC */
MeasurINT = ADC_Icc_Test(MCU_STOP_NoRTC);
/* Substract operational amplifier bias current from value*/
if ( MeasurINT > Bias_Current )
MeasurINT -= Bias_Current;
/* Convert value in uA*/
Current = MeasurINT * Vdd_appli()/ADC_CONV;
Current *= 20L;
/* Display mesured value */
display_MuAmp((uint32_t)Current);
/* Return value in uA*/
return (Current);
}
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

2
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/include/FreeRTOSConfig.h
View file

@ -89,7 +89,7 @@ assembler. */
/* Set configCREATE_LOW_POWER_DEMO to one to run the simple blinky low power
demo, or 0 to run the more comprehensive test and demo application. */
#define configCREATE_LOW_POWER_DEMO 0
#define configCREATE_LOW_POWER_DEMO 1
/* A few settings are dependent on the configCREATE_LOW_POWER_DEMO setting. */
#if configCREATE_LOW_POWER_DEMO == 1

126
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/include/discover_functions.h
View file

@ -1,126 +0,0 @@
/**
******************************************************************************
* @file discover_functions.h
* @author Microcontroller Division
* @version V1.0.3
* @date May-2013
* @brief This file contains measurement values and board
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __DISCOVER_FUNCTIONS_H
#define __DISCOVER_FUNCTIONS_H
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
#define DELAY Delay(150)
#define TEMPO if(!KeyPressed) DELAY
//#define SLIDER_DETECTED (sMCKeyInfo[0].Setting.b.DETECTED)
//#define SLIDER_POSITION (sMCKeyInfo[0].UnScaledPosition)
#define enableGlobalInterrupts() __set_PRIMASK(0);
#define disableGlobalInterrupts() __set_PRIMASK(1);
#define STR_VERSION tab[1] = 'V';tab[2] = '2'|DOT; tab[3] = '0'|DOT; tab[4] = '4'
#define STATE_VREF 0
#define STATE_SLIDER_VALUE 1
#define STATE_SLIDER_BUTTON 2
#define STATE_ICC_RUN 3
#define STATE_ICC_LP_RUN 4
#define STATE_ICC_STOP 5
#define STATE_ICC_STBY 6
#define MAX_STATE 7
/* Theorically BandGAP 1.224volt */
#define VREF 1.224L
/*
ADC Converter
LSBIdeal = VREF/4096 or VDA/4096
*/
#define ADC_CONV 4096
/*
VDD Factory for VREFINT measurement
*/
#define VDD_FACTORY 3.0L
#define MAX_CURRENT 99999
/* AUTO TEST VALUE */
#define VCC_MIN 2920 /* nominal Vcc/Vdd is 2.99V, allow 2.5% lower - Vref can be ~2% lower than 1.225 */
#define VCC_MAX 3100
#define ICC_RUN_MIN 6000
#define ICC_RUN_MAX 11000 /* typical ICC_RUN is ~0.9mA */
#define ICC_STOP_MIN 250
#define ICC_STOP_MAX 800 /* typical ICC_STOP is 0.6uA */
#define ICC_BIAS_MAX 30 /* ! converter value in decimal ! --> 3.0volts/4036* 30 = 21 mV */
#define ICC_STBY_MIN 150 /* typical ICC_STAND BY is 0.3 uA */
#define ICC_STBY_MAX 450
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
#define AUTOTEST(a) DATA_EEPROM_Unlock(); DATA_EEPROM_FastProgramByte((uint32_t)&self_test,a ) ; DATA_EEPROM_Lock()
/* Exported functions ------------------------------------------------------- */
void Init_Port (void);
void convert_into_char(uint32_t number, uint16_t *p_tab);
void LPR_init(void);
void Halt_Init(void);
uint16_t Vref_measure(void);
void Icc_measure(void);
float Icc_RUN(void);
float Icc_SLEEP(void);
float Icc_LPRUN(void);
float Icc_LPSLEEP(void);
float Icc_STOP(void);
float Icc_Stop_NoRTC(void);
void Icc_STBY(void);
float Icc_STBY_NoRTC(void);
void auto_test(void);
void Bias_measurement(void);
void test_vdd(void);
void test_icc_Run(void);
void test_icc_STOP(void);
void test_icc_STBY(void);
void display_MuAmp (uint32_t);
void FLASH_ProgramBias(uint8_t) ;
float Vdd_appli(void);
uint16_t wake_up_measurement (void);
void RCC_Configuration(void);
void Init_clocks(void);
void Init_GPIOs (void);
void TimingDelay_Decrement(void);
void Delay(uint32_t nTime);
void ExtraCode_StateMachine(void);
void Config_Systick(void);
void Config_Systick_50ms(void);
void Button_value(void);
void Slider_value(void);
void auto_test_part2(void);
#endif /* __DISCOVER_FUNCTIONS_H*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

1
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/include/main.h
View file

@ -36,7 +36,6 @@
/* discovery board and specific drivers headers*/
#include "discover_board.h"
#include "icc_measure.h"
#include "discover_functions.h"
#include "stm32l_discovery_lcd.h"

24
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/include/stm32l1xx_conf.h
View file

@ -25,26 +25,26 @@
/* Includes ------------------------------------------------------------------*/
/* Comment the line below to disable peripheral header file inclusion */
#include "stm32l1xx_adc.h"
#include "stm32l1xx_crc.h"
#include "stm32l1xx_comp.h"
#include "stm32l1xx_dac.h"
#include "stm32l1xx_dbgmcu.h"
#include "stm32l1xx_dma.h"
//#include "stm32l1xx_adc.h"
//#include "stm32l1xx_crc.h"
//#include "stm32l1xx_comp.h"
//#include "stm32l1xx_dac.h"
//#include "stm32l1xx_dbgmcu.h"
//#include "stm32l1xx_dma.h"
#include "stm32l1xx_exti.h"
#include "stm32l1xx_flash.h"
//#include "stm32l1xx_flash.h"
#include "stm32l1xx_gpio.h"
#include "stm32l1xx_syscfg.h"
#include "stm32l1xx_i2c.h"
#include "stm32l1xx_iwdg.h"
//#include "stm32l1xx_i2c.h"
//#include "stm32l1xx_iwdg.h"
#include "stm32l1xx_lcd.h"
#include "stm32l1xx_pwr.h"
#include "stm32l1xx_rcc.h"
#include "stm32l1xx_rtc.h"
#include "stm32l1xx_spi.h"
//#include "stm32l1xx_spi.h"
#include "stm32l1xx_tim.h"
#include "stm32l1xx_usart.h"
#include "stm32l1xx_wwdg.h"
//#include "stm32l1xx_usart.h"
//#include "stm32l1xx_wwdg.h"
#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
/* Exported types ------------------------------------------------------------*/

1
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/main.c
View file

@ -83,7 +83,6 @@
/* ST library functions. */
#include "stm32l1xx.h"
#include "discover_board.h"
#include "discover_functions.h"
/*-----------------------------------------------------------*/

74
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/main_full.c
View file

@ -122,7 +122,6 @@
/* ST library functions. */
#include "stm32l1xx.h"
#include "discover_board.h"
#include "discover_functions.h"
#include "stm32l_discovery_lcd.h"
/* Priorities for the demo application tasks. */
@ -150,12 +149,20 @@ in ticks using the portTICK_RATE_MS constant. */
*/
static void prvCheckTimerCallback( xTimerHandle xTimer );
/*
* Configure the LCD, then write welcome message.
*/
static void prvConfigureLCD( void );
/*-----------------------------------------------------------*/
void main_full( void )
{
xTimerHandle xCheckTimer = NULL;
/* The LCD is only used in the Full demo. */
prvConfigureLCD();
/* Start all the other standard demo/test tasks. They have not particular
functionality, but do demonstrate how to use the FreeRTOS API and test the
kernel port. */
@ -261,3 +268,68 @@ unsigned long ulErrorFound = pdFALSE;
}
/*-----------------------------------------------------------*/
static void prvConfigureLCD( void )
{
GPIO_InitTypeDef GPIO_InitStructure;
/* Enable necessary clocks. */
RCC_AHBPeriphClockCmd( RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC, ENABLE );
RCC_APB1PeriphClockCmd( RCC_APB1Periph_LCD, ENABLE );
PWR_RTCAccessCmd( ENABLE );
RCC_LSEConfig( ENABLE );
RCC_RTCCLKConfig( RCC_RTCCLKSource_LSE );
RCC_RTCCLKCmd( ENABLE );
/* Configure Port A LCD Output pins as alternate function. */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_8 | GPIO_Pin_9 |GPIO_Pin_10 |GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_Init( GPIOA, &GPIO_InitStructure );
/* Select LCD alternate function for Port A LCD Output pins. */
GPIO_PinAFConfig( GPIOA, GPIO_PinSource1, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOA, GPIO_PinSource2, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOA, GPIO_PinSource3, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOA, GPIO_PinSource8, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOA, GPIO_PinSource9, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOA, GPIO_PinSource10, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOA, GPIO_PinSource15, GPIO_AF_LCD );
/* Configure Port B LCD Output pins as alternate function */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_Init( GPIOB, &GPIO_InitStructure );
/* Select LCD alternate function for Port B LCD Output pins */
GPIO_PinAFConfig( GPIOB, GPIO_PinSource3, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOB, GPIO_PinSource4, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOB, GPIO_PinSource5, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOB, GPIO_PinSource8, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOB, GPIO_PinSource9, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOB, GPIO_PinSource10, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOB, GPIO_PinSource11, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOB, GPIO_PinSource12, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOB, GPIO_PinSource13, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOB, GPIO_PinSource14, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOB, GPIO_PinSource15, GPIO_AF_LCD );
/* Configure Port C LCD Output pins as alternate function */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |GPIO_Pin_11 ;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_Init( GPIOC, &GPIO_InitStructure );
/* Select LCD alternate function for Port B LCD Output pins */
GPIO_PinAFConfig( GPIOC, GPIO_PinSource0, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOC, GPIO_PinSource1, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOC, GPIO_PinSource2, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOC, GPIO_PinSource3, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOC, GPIO_PinSource6, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOC, GPIO_PinSource7, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOC, GPIO_PinSource8, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOC, GPIO_PinSource9, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOC, GPIO_PinSource10, GPIO_AF_LCD );
GPIO_PinAFConfig( GPIOC, GPIO_PinSource11, GPIO_AF_LCD );
LCD_GLASS_Init();
LCD_GLASS_DisplayString( "F'RTOS" );
}

1
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/main_low_power.c
View file

@ -156,7 +156,6 @@
/* ST library functions. */
#include "stm32l1xx.h"
#include "discover_board.h"
#include "discover_functions.h"
#include "stm32l_discovery_lcd.h"
/* Priorities at which the Rx and Tx tasks are created. */

1
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/stm32l1xx_it.c
View file

@ -24,7 +24,6 @@
#include "stm32l1xx_it.h"
#include "stm32l1xx_exti.h"
#include "stm32l1xx_rtc.h"
#include "discover_functions.h"
#include "discover_board.h"
#include "stm32l_discovery_lcd.h"
#include "tsl.h"