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<msg type="warning" file="Xst" num="2211" delta="new" >&quot;<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>&quot; line <arg fmt="%d" index="2">3615</arg>: Instantiating black box module &lt;<arg fmt="%s" index="3">IOBUF</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2211" delta="new" >&quot;<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>&quot; line <arg fmt="%d" index="2">3623</arg>: Instantiating black box module &lt;<arg fmt="%s" index="3">IOBUF</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2211" delta="new" >&quot;<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>&quot; line <arg fmt="%d" index="2">3631</arg>: Instantiating black box module &lt;<arg fmt="%s" index="3">IOBUF</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2211" delta="new" >&quot;<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>&quot; line <arg fmt="%d" index="2">3639</arg>: Instantiating black box module &lt;<arg fmt="%s" index="3">IOBUF</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2211" delta="new" >&quot;<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>&quot; line <arg fmt="%d" index="2">3647</arg>: Instantiating black box module &lt;<arg fmt="%s" index="3">IOBUF</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2211" delta="new" >&quot;<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>&quot; line <arg fmt="%d" index="2">3655</arg>: Instantiating black box module &lt;<arg fmt="%s" index="3">IOBUF</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2211" delta="new" >&quot;<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>&quot; line <arg fmt="%d" index="2">3663</arg>: Instantiating black box module &lt;<arg fmt="%s" index="3">IOBUF</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2211" delta="new" >&quot;<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>&quot; line <arg fmt="%d" index="2">3671</arg>: Instantiating black box module &lt;<arg fmt="%s" index="3">IOBUF</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2211" delta="new" >&quot;<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>&quot; line <arg fmt="%d" index="2">3679</arg>: Instantiating black box module &lt;<arg fmt="%s" index="3">IOBUF</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2211" delta="new" >&quot;<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>&quot; line <arg fmt="%d" index="2">3687</arg>: Instantiating black box module &lt;<arg fmt="%s" index="3">IOBUF</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2211" delta="new" >&quot;<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>&quot; line <arg fmt="%d" index="2">3695</arg>: Instantiating black box module &lt;<arg fmt="%s" index="3">IOBUF</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2211" delta="new" >&quot;<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>&quot; line <arg fmt="%d" index="2">3703</arg>: Instantiating black box module &lt;<arg fmt="%s" index="3">IOBUF</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2211" delta="new" >&quot;<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>&quot; line <arg fmt="%d" index="2">3711</arg>: Instantiating black box module &lt;<arg fmt="%s" index="3">IOBUF</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="2211" delta="new" >&quot;<arg fmt="%s" index="1">C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/hdl/system.vhd</arg>&quot; line <arg fmt="%d" index="2">3719</arg>: Instantiating black box module &lt;<arg fmt="%s" index="3">IBUFGDS</arg>&gt;.
</msg>

<msg type="warning" file="Xst" num="646" delta="old" >Signal &lt;<arg fmt="%s" index="1">pgassign9</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
</msg>

<msg type="warning" file="Xst" num="646" delta="old" >Signal &lt;<arg fmt="%s" index="1">pgassign11&lt;0:6&gt;</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
</msg>

<msg type="warning" file="Xst" num="646" delta="old" >Signal &lt;<arg fmt="%s" index="1">pgassign11&lt;31&gt;</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
</msg>

<msg type="warning" file="Xst" num="646" delta="old" >Signal &lt;<arg fmt="%s" index="1">pgassign10&lt;0&gt;</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">plb_v46_0/GEN_MPLB_RST[0].I_MPLB_RST</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">plb_v46_0</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">13 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;plb_v46_0/GEN_SPLB_RST[11].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[10].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[9].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[8].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[7].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[6].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[5].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[4].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[3].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[2].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[1].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[0].I_SPLB_RST&gt; &lt;plb_v46_0/I_PLB_RST&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_ATTACH/I_FLOP_ADDRACK</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">xps_bram_if_cntlr_1</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_ATTACH/I_FLOP_SET_SLBUSY&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_ATTACH/I_FLOP_WRACK_2BUS</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">xps_bram_if_cntlr_1</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_ATTACH/I_FLOP_WRACK&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_BURST_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">SRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.I_BURST_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sl_wrdack_i</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">SRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/GEN_WRITE_BUFFER.GEN_WRBUF_WREN1&gt; &lt;SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/GEN_WRITE_BUFFER.GEN_WRBUF_WREN2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_SNGL_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">SRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.I_SNGL_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[1].I_SIZE_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">SRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[1].I_SIZE_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[2].I_SIZE_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">SRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[2].I_SIZE_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[3].I_SIZE_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">SRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[3].I_SIZE_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">SRAM/EMC_CTRL_I/IO_REGISTERS_I/mem_wen_reg</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">SRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;SRAM/EMC_CTRL_I/MEM_STEER_I/SYNC_MEM_DQT.REG_DQT_GEN[0].DQT_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_CACHLN_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">SRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.I_CACHLN_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/I_SNGL_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/I_SNGL_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_SIZE_REG1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_SIZE_REG2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/flop[0].tx_power_down0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/flop[0].rx_power_down0&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[29].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[29].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[28].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[28].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/I_BURST_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/I_BURST_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[27].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[27].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[31].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[31].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[26].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[26].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/I_CACHLN_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/I_CACHLN_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[30].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[30].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[25].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[25].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[19].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[19].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[24].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[24].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[23].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[23].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[18].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[18].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.GEN_FOR_64.DPHASE_REG2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.GEN_FOR_64.DPHASE_REG1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[22].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[22].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[17].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[17].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[21].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[21].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[16].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[16].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[20].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[20].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[15].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[15].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[14].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[14].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[13].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[13].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[12].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[12].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[11].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[11].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[10].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[10].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[9].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[9].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/flop[0].tx_power_down1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/flop[0].rx_power_down1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[8].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[8].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[7].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[7].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[6].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[6].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[5].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[5].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[3].I_SIZE_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[3].I_SIZE_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[4].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[4].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[2].I_SIZE_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[2].I_SIZE_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[3].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[3].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[1].I_SIZE_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[1].I_SIZE_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[2].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[2].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[1].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[1].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[0].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[0].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BURST_SUPPORT/BTERM_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BURST_SUPPORT/BTERM_CLNUP&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.GEN_WRITE_BUFFER.GEN_WRBUF_WREN2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.GEN_WRITE_BUFFER.GEN_WRBUF_WREN1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/plb_size_reg_3</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/plb_size_reg_3_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/plb_size_reg_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/plb_size_reg_2_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">BU3</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">BU3</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">BU3</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">BU3</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">U0/grf.rf/gl0.rd/gr1.rfwft/aempty_fwft_i</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">BU2</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;U0/grf.rf/gl0.rd/gr1.rfwft/aempty_fwft_fb&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">BU2</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">U0/grf.rf/rstblk/wr_rst_reg_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">BU2</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;U0/grf.rf/rstblk/wr_rst_reg_0&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">BU2</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">U0/grf.rf/rstblk/rd_rst_reg_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">BU2</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;U0/grf.rf/rstblk/rd_rst_reg_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">ppc440_0_SPLB0/GEN_MPLB_RST[0].I_MPLB_RST</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">ppc440_0_SPLB0</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;ppc440_0_SPLB0/GEN_SPLB_RST[0].I_SPLB_RST&gt; &lt;ppc440_0_SPLB0/I_PLB_RST&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_state_machine/state21a</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">Ethernet_MAC</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_state_machine/state19a&gt; &lt;Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_state/state21a&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/clk_reset/rst0_sync_r_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rst0_sync_r_2_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">6 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_2&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_3&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_4&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_5&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_6&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[0].u_ff_rd_data_sel&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[1].u_ff_rd_data_sel&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[2].u_ff_rd_data_sel&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_3</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[3].u_ff_rd_data_sel&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_usr_top/usr_rd/gen_rden_sel_mux[0].u_ff_rden_sel_mux</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_usr_top/usr_rd/rden_sel_r_0&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_4</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[4].u_ff_rd_data_sel&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_26</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_26_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_26_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_31</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_31_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_31_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_5</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[5].u_ff_rd_data_sel&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_6</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[6].u_ff_rd_data_sel&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_7</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[7].u_ff_rd_data_sel&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_6</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_6_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_11</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_11_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_18</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_18_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_18_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_23</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_23_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_23_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_5</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_5_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_10</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_10_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_35</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_35_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_35_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_40</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_40_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_40_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_39</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_39_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_39_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_44</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_44_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_44_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_25</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_25_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_25_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_30</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_30_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_30_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_1_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_hit_r_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_hit_r_1_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_13</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_13_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_17</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_17_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_17_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_22</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_22_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_22_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">40 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_2&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_3&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_4&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_5&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_6&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_7&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_8&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_9&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_10&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_11&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_12&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_13&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_14&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_15&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_16&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_17&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_18&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_19&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_20&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_21&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_22&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_23&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_24&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_25&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_26&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_27&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_28&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_29&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_30&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_31&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_32&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_33&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_34&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_35&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_36&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_37&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_38&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_39&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_40&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_0_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_12</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_12_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_29</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_29_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_29_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_34</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_34_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_34_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_38</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_38_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_38_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_43</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_43_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_43_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_59</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_59_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_16</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_16_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_16_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_21</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_21_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_21_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_2_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_7</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_7_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_28</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_28_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_28_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_33</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_33_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_33_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_14</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_14_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/dqs_rst_n_r</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">7 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/dqs_rst_n_r&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/dqs_rst_n_r&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/dqs_rst_n_r&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/dqs_rst_n_r&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/dqs_rst_n_r&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/dqs_rst_n_r&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/dqs_rst_n_r&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_37</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_37_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_37_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_42</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_42_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_42_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_58</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_58_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_hit_r_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_hit_r_2_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_15</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_15_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_15_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_20</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_20_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_20_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_27</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_27_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_27_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_32</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_32_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_32_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_4</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_4_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_9</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_9_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_19</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_19_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_19_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_24</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_24_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_24_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[0].u_iob_dm/u_dm_ce</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">7 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[1].u_iob_dm/u_dm_ce&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[2].u_iob_dm/u_dm_ce&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[3].u_iob_dm/u_dm_ce&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[4].u_iob_dm/u_dm_ce&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[5].u_iob_dm/u_dm_ce&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[6].u_iob_dm/u_dm_ce&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[7].u_iob_dm/u_dm_ce&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_3</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_3_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_8</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_8_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_36</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_36_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_36_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_41</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_41_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_41_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">plb_v46_0/GEN_MPLB_RST[0].I_MPLB_RST</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">plb_v46_0</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">13 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;plb_v46_0/GEN_SPLB_RST[11].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[10].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[9].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[8].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[7].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[6].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[5].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[4].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[3].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[2].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[1].I_SPLB_RST&gt; &lt;plb_v46_0/GEN_SPLB_RST[0].I_SPLB_RST&gt; &lt;plb_v46_0/I_PLB_RST&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_ATTACH/I_FLOP_ADDRACK</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">xps_bram_if_cntlr_1</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_ATTACH/I_FLOP_SET_SLBUSY&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_ATTACH/I_FLOP_WRACK_2BUS</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">xps_bram_if_cntlr_1</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_ATTACH/I_FLOP_WRACK&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_BURST_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">SRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.I_BURST_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sl_wrdack_i</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">SRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/GEN_WRITE_BUFFER.GEN_WRBUF_WREN1&gt; &lt;SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/GEN_WRITE_BUFFER.GEN_WRBUF_WREN2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_SNGL_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">SRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.I_SNGL_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[1].I_SIZE_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">SRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[1].I_SIZE_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[2].I_SIZE_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">SRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[2].I_SIZE_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[3].I_SIZE_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">SRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[3].I_SIZE_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">SRAM/EMC_CTRL_I/IO_REGISTERS_I/mem_wen_reg</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">SRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;SRAM/EMC_CTRL_I/MEM_STEER_I/SYNC_MEM_DQT.REG_DQT_GEN[0].DQT_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_CACHLN_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">SRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.I_CACHLN_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/I_SNGL_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/I_SNGL_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_SIZE_REG1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_SIZE_REG2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/flop[0].tx_power_down0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/flop[0].rx_power_down0&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[29].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[29].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[28].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[28].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/I_BURST_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/I_BURST_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[27].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[27].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[31].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[31].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[26].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[26].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/I_CACHLN_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/I_CACHLN_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[30].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[30].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[25].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[25].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[19].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[19].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[24].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[24].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[23].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[23].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[18].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[18].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.GEN_FOR_64.DPHASE_REG2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.GEN_FOR_64.DPHASE_REG1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[22].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[22].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[17].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[17].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[21].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[21].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[16].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[16].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[20].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[20].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[15].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[15].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[14].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[14].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[13].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[13].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[12].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[12].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[11].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[11].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[10].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[10].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[9].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[9].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/flop[0].tx_power_down1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/flop[0].rx_power_down1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[8].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[8].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[7].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[7].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[6].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[6].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[5].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[5].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[3].I_SIZE_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[3].I_SIZE_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[4].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[4].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[2].I_SIZE_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[2].I_SIZE_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[3].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[3].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[1].I_SIZE_S_H_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[1].I_SIZE_S_H_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[2].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[2].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[1].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[1].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR2_INPUT[0].I_ADDR_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_EQL_TO_32_ADDR.REG_ADDR1_INPUT[0].I_ADDR_REG&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BURST_SUPPORT/BTERM_REG</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.I_BURST_SUPPORT/BTERM_CLNUP&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.GEN_WRITE_BUFFER.GEN_WRBUF_WREN2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_BURSTXFER.GEN_WRITE_BUFFER.GEN_WRBUF_WREN1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/plb_size_reg_3</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/plb_size_reg_3_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="new" >The FF/Latch &lt;<arg fmt="%s" index="1">PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/plb_size_reg_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">PCIe_Bridge</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/plb_size_reg_2_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">BU3</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">BU3</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">BU3</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">BU3</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">U0/grf.rf/gl0.rd/gr1.rfwft/aempty_fwft_i</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">BU2</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;U0/grf.rf/gl0.rd/gr1.rfwft/aempty_fwft_fb&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">BU2</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">U0/grf.rf/rstblk/wr_rst_reg_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">BU2</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;U0/grf.rf/rstblk/wr_rst_reg_0&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">BU2</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">U0/grf.rf/rstblk/rd_rst_reg_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">BU2</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;U0/grf.rf/rstblk/rd_rst_reg_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">ppc440_0_SPLB0/GEN_MPLB_RST[0].I_MPLB_RST</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">ppc440_0_SPLB0</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;ppc440_0_SPLB0/GEN_SPLB_RST[0].I_SPLB_RST&gt; &lt;ppc440_0_SPLB0/I_PLB_RST&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_state_machine/state21a</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">Ethernet_MAC</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_state_machine/state19a&gt; &lt;Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_state/state21a&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/clk_reset/rst0_sync_r_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rst0_sync_r_2_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">6 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_2&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_3&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_4&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_5&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rst90_sync_r_2_6&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[0].u_ff_rd_data_sel&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[1].u_ff_rd_data_sel&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[2].u_ff_rd_data_sel&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_3</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[3].u_ff_rd_data_sel&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_usr_top/usr_rd/gen_rden_sel_mux[0].u_ff_rden_sel_mux</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_usr_top/usr_rd/rden_sel_r_0&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_4</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[4].u_ff_rd_data_sel&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_26</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_26_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_26_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_31</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_31_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_31_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_5</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[5].u_ff_rd_data_sel&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_6</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[6].u_ff_rd_data_sel&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal2_rd_data_sel_r_7</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[7].u_ff_rd_data_sel&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_11</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_11_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_6</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_6_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_23</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_23_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_23_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_18</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_18_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_18_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_10</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_10_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_5</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_5_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_40</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_40_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_40_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_35</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_35_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_35_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_44</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_44_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_44_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_39</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_39_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_39_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_30</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_30_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_30_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_25</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_25_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_25_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_1_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_hit_r_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_hit_r_1_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_13</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_13_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_22</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_22_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_22_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_17</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_17_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_17_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">40 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_2&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_3&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_4&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_5&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_6&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_7&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_8&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_9&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_10&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_11&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_12&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_13&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_14&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_15&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_16&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_17&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_18&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_19&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_20&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_21&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_22&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_23&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_24&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_25&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_26&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_27&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_28&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_29&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_30&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_31&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_32&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_33&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_34&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_35&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_36&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_37&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_38&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_39&gt; &lt;DDR2_SDRAM/u_ddr2_top/clk_reset/rstdiv0_sync_r_0_40&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_0_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_12</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_12_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_34</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_34_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_34_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_29</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_29_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_29_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_43</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_43_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_43_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_38</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_38_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_38_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_59</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_59_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_21</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_21_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_21_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_16</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_16_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_16_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_7</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_7_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_2_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_33</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_33_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_33_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_28</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_28_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_28_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_14</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_14_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/dqs_rst_n_r</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">7 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/dqs_rst_n_r&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/dqs_rst_n_r&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/dqs_rst_n_r&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/dqs_rst_n_r&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/dqs_rst_n_r&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/dqs_rst_n_r&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/dqs_rst_n_r&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_42</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_42_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_42_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_37</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_37_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_37_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_58</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_58_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_hit_r_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_hit_r_2_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_15</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_15_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_15_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_20</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_20_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_20_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_32</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_32_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_32_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_27</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_27_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_27_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_9</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_9_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_4</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_4_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_24</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_24_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_24_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_19</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_19_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_19_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[0].u_iob_dm/u_dm_ce</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">7 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[1].u_iob_dm/u_dm_ce&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[2].u_iob_dm/u_dm_ce&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[3].u_iob_dm/u_dm_ce&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[4].u_iob_dm/u_dm_ce&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[5].u_iob_dm/u_dm_ce&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[6].u_iob_dm/u_dm_ce&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dm[7].u_iob_dm/u_dm_ce&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_8</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_8_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_3</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_3_1&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_41</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_41_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_41_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_36</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">DDR2_SDRAM</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg> : <arg fmt="%s" index="4">&lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_36_1&gt; &lt;DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_u_ctrl/bank_cmp_addr_r_36_2&gt; </arg>
</msg>

<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>

</messages>

