Zynq PS7 Summary Report
User Configurations
MIO Configurations

CLK Configurations

DDR Configurations

SMC Configurations
Select Version:
Zynq Register View
MIO Registers
PLL Registers
Clock Registers
DDR Registers
Peripherals Registers
This design is targeted for7vx485tboard (part number: )

# Zynq Design Summary

Device | 7vx485t
SpeedGrade | 7vx485t
Part |
Description | Zynq PS Configuration Report with register details
Vendor | Xilinx

## MIO Table View

MIO Pin | Peripheral | Signal | IO Type | Speed | Pullup | Direction
MIO 0 | Single Quad SPI (4bit) | sclk_out | 0 | 0 | 1 | out
MIO 1 | Single Quad SPI (4bit) | so_mo1 | 0 | 0 | 1 | inout
MIO 2 | Single Quad SPI (4bit) | mo2 | 0 | 0 | 1 | inout
MIO 3 | Single Quad SPI (4bit) | mo3 | 0 | 0 | 1 | inout
MIO 4 | Single Quad SPI (4bit) | si_mi0 | 0 | 0 | 1 | inout
MIO 5 | Single Quad SPI (4bit) | n_ss_out | 0 | 0 | 1 | out
MIO 6 | GPIO0 MIO | gpio0[6] | 0 | 0 | 1 | inout
MIO 7 | GPIO0 MIO | gpio0[7] | 0 | 0 | 1 | inout
MIO 8 | GPIO0 MIO | gpio0[8] | 0 | 0 | 1 | inout
MIO 9 | GPIO0 MIO | gpio0[9] | 0 | 0 | 1 | inout
MIO 10 | NAND | nfc_rb_n[0] | 0 | 0 | 1 | in
MIO 11 | NAND | nfc_rb_n[1] | 0 | 0 | 1 | in
MIO 12 | GPIO0 MIO | gpio0[12] | 0 | 0 | 1 | inout
MIO 13 | NAND | nfc_ce[0] | 0 | 0 | 1 | out
MIO 14 | NAND | nfc_cle | 0 | 0 | 1 | out
MIO 15 | NAND | nfc_ale | 0 | 0 | 1 | out
MIO 16 | NAND | nfc_dq_out[0] | 0 | 0 | 1 | inout
MIO 17 | NAND | nfc_dq_out[1] | 0 | 0 | 1 | inout
MIO 18 | NAND | nfc_dq_out[2] | 0 | 0 | 1 | inout
MIO 19 | NAND | nfc_dq_out[3] | 0 | 0 | 1 | inout
MIO 20 | NAND | nfc_dq_out[4] | 0 | 0 | 1 | inout
MIO 21 | NAND | nfc_dq_out[5] | 0 | 0 | 1 | inout
MIO 22 | NAND | nfc_we_b | 0 | 0 | 1 | out
MIO 23 | NAND | nfc_dq_out[6] | 0 | 0 | 1 | inout
MIO 24 | NAND | nfc_dq_out[7] | 0 | 0 | 1 | inout
MIO 25 | NAND | nfc_re_n | 0 | 0 | 1 | out
MIO 26 | NAND | nfc_ce[1] | 0 | 0 | 1 | out
MIO 27 | GPIO1 MIO | gpio1[27] | 0 | 0 | 1 | inout
MIO 28 | GPIO1 MIO | gpio1[28] | 0 | 0 | 1 | inout
MIO 29 | SPI 0 | n_ss_out[0] | 0 | 0 | 1 | inout
MIO 30 | GPIO1 MIO | gpio1[30] | 0 | 0 | 1 | inout
MIO 31 | GPIO1 MIO | gpio1[31] | 0 | 0 | 1 | inout
MIO 32 | NAND | nfc_dqs_out | 0 | 0 | 1 | inout
MIO 33 | GPIO1 MIO | gpio1[33] | 0 | 0 | 1 | inout
MIO 34 | GPIO1 MIO | gpio1[34] | 0 | 0 | 1 | inout
MIO 35 | SPI 1 | n_ss_out[0] | 0 | 0 | 1 | inout
MIO 36 | GPIO1 MIO | gpio1[36] | 0 | 0 | 1 | inout
MIO 37 | GPIO1 MIO | gpio1[37] | 0 | 0 | 1 | inout
MIO 38 | GPIO1 MIO | gpio1[38] | 0 | 0 | 1 | inout
MIO 39 | SD 1 | sdio1_data_out[4] | 0 | 0 | 1 | inout
MIO 40 | SD 1 | sdio1_data_out[5] | 0 | 0 | 1 | inout
MIO 41 | SD 1 | sdio1_data_out[6] | 0 | 0 | 1 | inout
MIO 42 | SD 1 | sdio1_data_out[7] | 0 | 0 | 1 | inout
MIO 43 | SD 1 | sdio1_bus_pow | 0 | 0 | 1 | out
MIO 44 | GPIO1 MIO | gpio1[44] | 0 | 0 | 1 | inout
MIO 45 | GPIO1 MIO | gpio1[45] | 0 | 0 | 1 | inout
MIO 46 | SD 1 | sdio1_data_out[0] | 0 | 0 | 1 | inout
MIO 47 | SD 1 | sdio1_data_out[1] | 0 | 0 | 1 | inout
MIO 48 | SD 1 | sdio1_data_out[2] | 0 | 0 | 1 | inout
MIO 49 | SD 1 | sdio1_data_out[3] | 0 | 0 | 1 | inout
MIO 50 | SD 1 | sdio1_cmd_out | 0 | 0 | 1 | inout
MIO 51 | SD 1 | sdio1_clk_out | 0 | 0 | 1 | out
MIO 52 | USB 0 | ulpi_clk_in | 0 | 0 | 1 | in
MIO 53 | USB 0 | ulpi_dir | 0 | 0 | 1 | in

## psu_pll_init_data

Register Name | Address | Width | Type | Reset Value | Description
PSU_CRL_APB_RPLL_CTRL | 0XFF5E0030 | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRL_APB_RPLL_CTRL | 0XFF5E0030 | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRL_APB_RPLL_CTRL | 0XFF5E0030 | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRL_APB_RPLL_CTRL | 0XFF5E0030 | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRL_APB_RPLL_CTRL | 0XFF5E0030 | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRL_APB_RPLL_TO_FPD_CTRL | 0XFF5E0048 | 32 | RW | 0x000000 | Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
PSU_CRL_APB_IOPLL_CTRL | 0XFF5E0020 | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRL_APB_IOPLL_CTRL | 0XFF5E0020 | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRL_APB_IOPLL_CTRL | 0XFF5E0020 | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRL_APB_IOPLL_CTRL | 0XFF5E0020 | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRL_APB_IOPLL_CTRL | 0XFF5E0020 | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRL_APB_IOPLL_TO_FPD_CTRL | 0XFF5E0044 | 32 | RW | 0x000000 | Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
PSU_CRF_APB_APLL_CTRL | 0XFD1A0020 | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRF_APB_APLL_CTRL | 0XFD1A0020 | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRF_APB_APLL_CTRL | 0XFD1A0020 | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRF_APB_APLL_CTRL | 0XFD1A0020 | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRF_APB_APLL_CTRL | 0XFD1A0020 | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRF_APB_APLL_TO_LPD_CTRL | 0XFD1A0048 | 32 | RW | 0x000000 | Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
PSU_CRF_APB_DPLL_CTRL | 0XFD1A002C | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRF_APB_DPLL_CTRL | 0XFD1A002C | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRF_APB_DPLL_CTRL | 0XFD1A002C | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRF_APB_DPLL_CTRL | 0XFD1A002C | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRF_APB_DPLL_CTRL | 0XFD1A002C | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRF_APB_DPLL_TO_LPD_CTRL | 0XFD1A004C | 32 | RW | 0x000000 | Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
PSU_CRF_APB_VPLL_CTRL | 0XFD1A0038 | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRF_APB_VPLL_CTRL | 0XFD1A0038 | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRF_APB_VPLL_CTRL | 0XFD1A0038 | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRF_APB_VPLL_CTRL | 0XFD1A0038 | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRF_APB_VPLL_CTRL | 0XFD1A0038 | 32 | RW | 0x000000 | PLL Basic Control
PSU_CRF_APB_VPLL_TO_LPD_CTRL | 0XFD1A0050 | 32 | RW | 0x000000 | Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.

## psu_pll_init_data

Register Name | Address | Width | Type | Reset Value | Description

# RPLL INIT

# UPDATE FB_DIV

## Register ( slcr )RPLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
RPLL_CTRL | 0XFF5E0030 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_RPLL_CTRL_FBDIV | 14:8 | 7f00 | 30 | 3000 | The integer portion of the feedback divider to the PLL
PSU_CRL_APB_RPLL_CTRL_DIV2 | 16:16 | 10000 | 1 | 10000 | This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
PSU_CRL_APB_RPLL_CTRL@0XFF5E0030 | 31:0 | 17f00 |  | 13000 | PLL Basic Control

# BY PASS PLL

## Register ( slcr )RPLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
RPLL_CTRL | 0XFF5E0030 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_RPLL_CTRL_BYPASS | 3:3 | 8 | 1 | 8 | Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_RPLL_CTRL@0XFF5E0030 | 31:0 | 8 |  | 8 | PLL Basic Control

# ASSERT RESET

## Register ( slcr )RPLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
RPLL_CTRL | 0XFF5E0030 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_RPLL_CTRL_RESET | 0:0 | 1 | 1 | 1 | Asserts Reset to the PLL
PSU_CRL_APB_RPLL_CTRL@0XFF5E0030 | 31:0 | 1 |  | 1 | PLL Basic Control

# DEASSERT RESET

## Register ( slcr )RPLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
RPLL_CTRL | 0XFF5E0030 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_RPLL_CTRL_RESET | 0:0 | 1 | 0 | 0 | Asserts Reset to the PLL
PSU_CRL_APB_RPLL_CTRL@0XFF5E0030 | 31:0 | 1 |  | 0 | PLL Basic Control

# CHECK PLL STATUS

## Register ( slcr )PLL_STATUS

Register Name | Address | Width | Type | Reset Value | Description
PLL_STATUS | 0XFF5E0040 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_PLL_STATUS_RPLL_LOCK | 1:1 | 2 | 1 | 2 | RPLL is locked
PSU_CRL_APB_PLL_STATUS@0XFF5E0040 | 31:0 | 2 |  | 2 | tobe

# REMOVE PLL BY PASS

## Register ( slcr )RPLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
RPLL_CTRL | 0XFF5E0030 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_RPLL_CTRL_BYPASS | 3:3 | 8 | 0 | 0 | Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_RPLL_CTRL@0XFF5E0030 | 31:0 | 8 |  | 0 | PLL Basic Control

## Register ( slcr )RPLL_TO_FPD_CTRL

Register Name | Address | Width | Type | Reset Value | Description
RPLL_TO_FPD_CTRL | 0XFF5E0048 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 | 13:8 | 3f00 | 3 | 300 | Divisor value for this clock.
PSU_CRL_APB_RPLL_TO_FPD_CTRL@0XFF5E0048 | 31:0 | 3f00 |  | 300 | Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.

# RPLL FRAC CFG

# IOPLL INIT

# UPDATE FB_DIV

## Register ( slcr )IOPLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
IOPLL_CTRL | 0XFF5E0020 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_IOPLL_CTRL_FBDIV | 14:8 | 7f00 | 3c | 3c00 | The integer portion of the feedback divider to the PLL
PSU_CRL_APB_IOPLL_CTRL_DIV2 | 16:16 | 10000 | 1 | 10000 | This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
PSU_CRL_APB_IOPLL_CTRL@0XFF5E0020 | 31:0 | 17f00 |  | 13c00 | PLL Basic Control

# BY PASS PLL

## Register ( slcr )IOPLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
IOPLL_CTRL | 0XFF5E0020 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_IOPLL_CTRL_BYPASS | 3:3 | 8 | 1 | 8 | Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_IOPLL_CTRL@0XFF5E0020 | 31:0 | 8 |  | 8 | PLL Basic Control

# ASSERT RESET

## Register ( slcr )IOPLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
IOPLL_CTRL | 0XFF5E0020 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_IOPLL_CTRL_RESET | 0:0 | 1 | 1 | 1 | Asserts Reset to the PLL
PSU_CRL_APB_IOPLL_CTRL@0XFF5E0020 | 31:0 | 1 |  | 1 | PLL Basic Control

# DEASSERT RESET

## Register ( slcr )IOPLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
IOPLL_CTRL | 0XFF5E0020 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_IOPLL_CTRL_RESET | 0:0 | 1 | 0 | 0 | Asserts Reset to the PLL
PSU_CRL_APB_IOPLL_CTRL@0XFF5E0020 | 31:0 | 1 |  | 0 | PLL Basic Control

# CHECK PLL STATUS

## Register ( slcr )PLL_STATUS

Register Name | Address | Width | Type | Reset Value | Description
PLL_STATUS | 0XFF5E0040 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK | 0:0 | 1 | 1 | 1 | IOPLL is locked
PSU_CRL_APB_PLL_STATUS@0XFF5E0040 | 31:0 | 1 |  | 1 | tobe

# REMOVE PLL BY PASS

## Register ( slcr )IOPLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
IOPLL_CTRL | 0XFF5E0020 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_IOPLL_CTRL_BYPASS | 3:3 | 8 | 0 | 0 | Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_IOPLL_CTRL@0XFF5E0020 | 31:0 | 8 |  | 0 | PLL Basic Control

## Register ( slcr )IOPLL_TO_FPD_CTRL

Register Name | Address | Width | Type | Reset Value | Description
IOPLL_TO_FPD_CTRL | 0XFF5E0044 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 | 13:8 | 3f00 | 4 | 400 | Divisor value for this clock.
PSU_CRL_APB_IOPLL_TO_FPD_CTRL@0XFF5E0044 | 31:0 | 3f00 |  | 400 | Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.

# IOPLL FRAC CFG

# APU_PLL INIT

# UPDATE FB_DIV

## Register ( slcr )APLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
APLL_CTRL | 0XFD1A0020 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_APLL_CTRL_FBDIV | 14:8 | 7f00 | 3c | 3c00 | The integer portion of the feedback divider to the PLL
PSU_CRF_APB_APLL_CTRL_DIV2 | 16:16 | 10000 | 1 | 10000 | This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
PSU_CRF_APB_APLL_CTRL@0XFD1A0020 | 31:0 | 17f00 |  | 13c00 | PLL Basic Control

# BY PASS PLL

## Register ( slcr )APLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
APLL_CTRL | 0XFD1A0020 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_APLL_CTRL_BYPASS | 3:3 | 8 | 1 | 8 | Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_APLL_CTRL@0XFD1A0020 | 31:0 | 8 |  | 8 | PLL Basic Control

# ASSERT RESET

## Register ( slcr )APLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
APLL_CTRL | 0XFD1A0020 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_APLL_CTRL_RESET | 0:0 | 1 | 1 | 1 | Asserts Reset to the PLL
PSU_CRF_APB_APLL_CTRL@0XFD1A0020 | 31:0 | 1 |  | 1 | PLL Basic Control

# DEASSERT RESET

## Register ( slcr )APLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
APLL_CTRL | 0XFD1A0020 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_APLL_CTRL_RESET | 0:0 | 1 | 0 | 0 | Asserts Reset to the PLL
PSU_CRF_APB_APLL_CTRL@0XFD1A0020 | 31:0 | 1 |  | 0 | PLL Basic Control

# CHECK PLL STATUS

## Register ( slcr )PLL_STATUS

Register Name | Address | Width | Type | Reset Value | Description
PLL_STATUS | 0XFD1A0044 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_PLL_STATUS_APLL_LOCK | 0:0 | 1 | 1 | 1 | APLL is locked
PSU_CRF_APB_PLL_STATUS@0XFD1A0044 | 31:0 | 1 |  | 1 | tobe

# REMOVE PLL BY PASS

## Register ( slcr )APLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
APLL_CTRL | 0XFD1A0020 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_APLL_CTRL_BYPASS | 3:3 | 8 | 0 | 0 | Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_APLL_CTRL@0XFD1A0020 | 31:0 | 8 |  | 0 | PLL Basic Control

## Register ( slcr )APLL_TO_LPD_CTRL

Register Name | Address | Width | Type | Reset Value | Description
APLL_TO_LPD_CTRL | 0XFD1A0048 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0 | 13:8 | 3f00 | 4 | 400 | Divisor value for this clock.
PSU_CRF_APB_APLL_TO_LPD_CTRL@0XFD1A0048 | 31:0 | 3f00 |  | 400 | Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.

# APLL FRAC CFG

# DDR_PLL INIT

# UPDATE FB_DIV

## Register ( slcr )DPLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
DPLL_CTRL | 0XFD1A002C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_DPLL_CTRL_FBDIV | 14:8 | 7f00 | 3c | 3c00 | The integer portion of the feedback divider to the PLL
PSU_CRF_APB_DPLL_CTRL_DIV2 | 16:16 | 10000 | 1 | 10000 | This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
PSU_CRF_APB_DPLL_CTRL@0XFD1A002C | 31:0 | 17f00 |  | 13c00 | PLL Basic Control

# BY PASS PLL

## Register ( slcr )DPLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
DPLL_CTRL | 0XFD1A002C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_DPLL_CTRL_BYPASS | 3:3 | 8 | 1 | 8 | Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_DPLL_CTRL@0XFD1A002C | 31:0 | 8 |  | 8 | PLL Basic Control

# ASSERT RESET

## Register ( slcr )DPLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
DPLL_CTRL | 0XFD1A002C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_DPLL_CTRL_RESET | 0:0 | 1 | 1 | 1 | Asserts Reset to the PLL
PSU_CRF_APB_DPLL_CTRL@0XFD1A002C | 31:0 | 1 |  | 1 | PLL Basic Control

# DEASSERT RESET

## Register ( slcr )DPLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
DPLL_CTRL | 0XFD1A002C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_DPLL_CTRL_RESET | 0:0 | 1 | 0 | 0 | Asserts Reset to the PLL
PSU_CRF_APB_DPLL_CTRL@0XFD1A002C | 31:0 | 1 |  | 0 | PLL Basic Control

# CHECK PLL STATUS

## Register ( slcr )PLL_STATUS

Register Name | Address | Width | Type | Reset Value | Description
PLL_STATUS | 0XFD1A0044 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_PLL_STATUS_DPLL_LOCK | 1:1 | 2 | 1 | 2 | DPLL is locked
PSU_CRF_APB_PLL_STATUS@0XFD1A0044 | 31:0 | 2 |  | 2 | tobe

# REMOVE PLL BY PASS

## Register ( slcr )DPLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
DPLL_CTRL | 0XFD1A002C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_DPLL_CTRL_BYPASS | 3:3 | 8 | 0 | 0 | Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_DPLL_CTRL@0XFD1A002C | 31:0 | 8 |  | 0 | PLL Basic Control

## Register ( slcr )DPLL_TO_LPD_CTRL

Register Name | Address | Width | Type | Reset Value | Description
DPLL_TO_LPD_CTRL | 0XFD1A004C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 | 13:8 | 3f00 | 4 | 400 | Divisor value for this clock.
PSU_CRF_APB_DPLL_TO_LPD_CTRL@0XFD1A004C | 31:0 | 3f00 |  | 400 | Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.

# DPLL FRAC CFG

# VIDEO_PLL INIT

# UPDATE FB_DIV

## Register ( slcr )VPLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
VPLL_CTRL | 0XFD1A0038 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_VPLL_CTRL_FBDIV | 14:8 | 7f00 | 3f | 3f00 | The integer portion of the feedback divider to the PLL
PSU_CRF_APB_VPLL_CTRL_DIV2 | 16:16 | 10000 | 1 | 10000 | This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
PSU_CRF_APB_VPLL_CTRL@0XFD1A0038 | 31:0 | 17f00 |  | 13f00 | PLL Basic Control

# BY PASS PLL

## Register ( slcr )VPLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
VPLL_CTRL | 0XFD1A0038 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_VPLL_CTRL_BYPASS | 3:3 | 8 | 1 | 8 | Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_VPLL_CTRL@0XFD1A0038 | 31:0 | 8 |  | 8 | PLL Basic Control

# ASSERT RESET

## Register ( slcr )VPLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
VPLL_CTRL | 0XFD1A0038 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_VPLL_CTRL_RESET | 0:0 | 1 | 1 | 1 | Asserts Reset to the PLL
PSU_CRF_APB_VPLL_CTRL@0XFD1A0038 | 31:0 | 1 |  | 1 | PLL Basic Control

# DEASSERT RESET

## Register ( slcr )VPLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
VPLL_CTRL | 0XFD1A0038 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_VPLL_CTRL_RESET | 0:0 | 1 | 0 | 0 | Asserts Reset to the PLL
PSU_CRF_APB_VPLL_CTRL@0XFD1A0038 | 31:0 | 1 |  | 0 | PLL Basic Control

# CHECK PLL STATUS

## Register ( slcr )PLL_STATUS

Register Name | Address | Width | Type | Reset Value | Description
PLL_STATUS | 0XFD1A0044 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_PLL_STATUS_VPLL_LOCK | 2:2 | 4 | 1 | 4 | VPLL is locked
PSU_CRF_APB_PLL_STATUS@0XFD1A0044 | 31:0 | 4 |  | 4 | tobe

# REMOVE PLL BY PASS

## Register ( slcr )VPLL_CTRL

Register Name | Address | Width | Type | Reset Value | Description
VPLL_CTRL | 0XFD1A0038 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_VPLL_CTRL_BYPASS | 3:3 | 8 | 0 | 0 | Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_VPLL_CTRL@0XFD1A0038 | 31:0 | 8 |  | 0 | PLL Basic Control

## Register ( slcr )VPLL_TO_LPD_CTRL

Register Name | Address | Width | Type | Reset Value | Description
VPLL_TO_LPD_CTRL | 0XFD1A0050 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0 | 13:8 | 3f00 | 4 | 400 | Divisor value for this clock.
PSU_CRF_APB_VPLL_TO_LPD_CTRL@0XFD1A0050 | 31:0 | 3f00 |  | 400 | Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.

# VIDEO FRAC CFG

## psu_clock_init_data

Register Name | Address | Width | Type | Reset Value | Description
PSU_CRL_APB_GEM0_REF_CTRL | 0XFF5E0050 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_GEM1_REF_CTRL | 0XFF5E0054 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_GEM2_REF_CTRL | 0XFF5E0058 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_GEM3_REF_CTRL | 0XFF5E005C | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_USB0_BUS_REF_CTRL | 0XFF5E0060 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_USB3_DUAL_REF_CTRL | 0XFF5E004C | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_QSPI_REF_CTRL | 0XFF5E0068 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_SDIO0_REF_CTRL | 0XFF5E006C | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_SDIO1_REF_CTRL | 0XFF5E0070 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_UART0_REF_CTRL | 0XFF5E0074 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_UART1_REF_CTRL | 0XFF5E0078 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_I2C0_REF_CTRL | 0XFF5E0120 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_I2C1_REF_CTRL | 0XFF5E0124 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_SPI0_REF_CTRL | 0XFF5E007C | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_SPI1_REF_CTRL | 0XFF5E0080 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_CAN0_REF_CTRL | 0XFF5E0084 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_CAN1_REF_CTRL | 0XFF5E0088 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_CPU_R5_CTRL | 0XFF5E0090 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_IOU_SWITCH_CTRL | 0XFF5E009C | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_PCAP_CTRL | 0XFF5E00A4 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_LPD_SWITCH_CTRL | 0XFF5E00A8 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_LPD_LSBUS_CTRL | 0XFF5E00AC | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_DBG_LPD_CTRL | 0XFF5E00B0 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_NAND_REF_CTRL | 0XFF5E00B4 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_ADMA_REF_CTRL | 0XFF5E00B8 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_AMS_REF_CTRL | 0XFF5E0108 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_DLL_REF_CTRL | 0XFF5E0104 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRL_APB_TIMESTAMP_REF_CTRL | 0XFF5E0128 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRF_APB_PCIE_REF_CTRL | 0XFD1A00B4 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRF_APB_DP_VIDEO_REF_CTRL | 0XFD1A0070 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRF_APB_DP_AUDIO_REF_CTRL | 0XFD1A0074 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRF_APB_DP_STC_REF_CTRL | 0XFD1A007C | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRF_APB_ACPU_CTRL | 0XFD1A0060 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRF_APB_DBG_TRACE_CTRL | 0XFD1A0064 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRF_APB_DBG_FPD_CTRL | 0XFD1A0068 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRF_APB_DDR_CTRL | 0XFD1A0080 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRF_APB_GPU_REF_CTRL | 0XFD1A0084 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRF_APB_GDMA_REF_CTRL | 0XFD1A00B8 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRF_APB_DPDMA_REF_CTRL | 0XFD1A00BC | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRF_APB_TOPSW_MAIN_CTRL | 0XFD1A00C0 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRF_APB_TOPSW_LSBUS_CTRL | 0XFD1A00C4 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRF_APB_GTGREF0_REF_CTRL | 0XFD1A00C8 | 32 | RW | 0x000000 | This register controls this reference clock
PSU_CRF_APB_DBG_TSTMP_CTRL | 0XFD1A00F8 | 32 | RW | 0x000000 | This register controls this reference clock

## psu_clock_init_data

Register Name | Address | Width | Type | Reset Value | Description

# CLOCK CONTROL SLCR REGISTER

## Register ( slcr )GEM0_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
GEM0_REF_CTRL | 0XFF5E0050 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_GEM0_REF_CTRL_RX_CLKACT | 26:26 | 4000000 | 1 | 4000000 | Clock active for the RX channel
PSU_CRL_APB_GEM0_REF_CTRL_CLKACT | 25:25 | 2000000 | 1 | 2000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | 2 | 20000 | 6 bit divider
PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 28 | 2800 | 6 bit divider
PSU_CRL_APB_GEM0_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_GEM0_REF_CTRL@0XFF5E0050 | 31:0 | 63f3f07 |  | 6022800 | This register controls this reference clock

## Register ( slcr )GEM1_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
GEM1_REF_CTRL | 0XFF5E0054 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_GEM1_REF_CTRL_RX_CLKACT | 26:26 | 4000000 | 1 | 4000000 | Clock active for the RX channel
PSU_CRL_APB_GEM1_REF_CTRL_CLKACT | 25:25 | 2000000 | 1 | 2000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | 2 | 20000 | 6 bit divider
PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 28 | 2800 | 6 bit divider
PSU_CRL_APB_GEM1_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_GEM1_REF_CTRL@0XFF5E0054 | 31:0 | 63f3f07 |  | 6022800 | This register controls this reference clock

## Register ( slcr )GEM2_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
GEM2_REF_CTRL | 0XFF5E0058 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_GEM2_REF_CTRL_RX_CLKACT | 26:26 | 4000000 | 1 | 4000000 | Clock active for the RX channel
PSU_CRL_APB_GEM2_REF_CTRL_CLKACT | 25:25 | 2000000 | 1 | 2000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | 2 | 20000 | 6 bit divider
PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 28 | 2800 | 6 bit divider
PSU_CRL_APB_GEM2_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_GEM2_REF_CTRL@0XFF5E0058 | 31:0 | 63f3f07 |  | 6022800 | This register controls this reference clock

## Register ( slcr )GEM3_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
GEM3_REF_CTRL | 0XFF5E005C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT | 26:26 | 4000000 | 1 | 4000000 | Clock active for the RX channel
PSU_CRL_APB_GEM3_REF_CTRL_CLKACT | 25:25 | 2000000 | 1 | 2000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | 2 | 20000 | 6 bit divider
PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 28 | 2800 | 6 bit divider
PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_GEM3_REF_CTRL@0XFF5E005C | 31:0 | 63f3f07 |  | 6022800 | This register controls this reference clock

## Register ( slcr )USB0_BUS_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
USB0_BUS_REF_CTRL | 0XFF5E0060 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT | 25:25 | 2000000 | 1 | 2000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | 1 | 10000 | 6 bit divider
PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 32 | 3200 | 6 bit divider
PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_USB0_BUS_REF_CTRL@0XFF5E0060 | 31:0 | 23f3f07 |  | 2013200 | This register controls this reference clock

## Register ( slcr )USB3_DUAL_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
USB3_DUAL_REF_CTRL | 0XFF5E004C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT | 25:25 | 2000000 | 1 | 2000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | 1 | 10000 | 6 bit divider
PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 8 | 800 | 6 bit divider
PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_USB3_DUAL_REF_CTRL@0XFF5E004C | 31:0 | 23f3f07 |  | 2010800 | This register controls this reference clock

## Register ( slcr )QSPI_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
QSPI_REF_CTRL | 0XFF5E0068 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_QSPI_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | 2 | 20000 | 6 bit divider
PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 32 | 3200 | 6 bit divider
PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_QSPI_REF_CTRL@0XFF5E0068 | 31:0 | 13f3f07 |  | 1023200 | This register controls this reference clock

## Register ( slcr )SDIO0_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
SDIO0_REF_CTRL | 0XFF5E006C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_SDIO0_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | 2 | 20000 | 6 bit divider
PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 32 | 3200 | 6 bit divider
PSU_CRL_APB_SDIO0_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_SDIO0_REF_CTRL@0XFF5E006C | 31:0 | 13f3f07 |  | 1023200 | This register controls this reference clock

## Register ( slcr )SDIO1_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
SDIO1_REF_CTRL | 0XFF5E0070 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | 2 | 20000 | 6 bit divider
PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 32 | 3200 | 6 bit divider
PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_SDIO1_REF_CTRL@0XFF5E0070 | 31:0 | 13f3f07 |  | 1023200 | This register controls this reference clock

## Register ( slcr )UART0_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
UART0_REF_CTRL | 0XFF5E0074 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_UART0_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | 2 | 20000 | 6 bit divider
PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 28 | 2800 | 6 bit divider
PSU_CRL_APB_UART0_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_UART0_REF_CTRL@0XFF5E0074 | 31:0 | 13f3f07 |  | 1022800 | This register controls this reference clock

## Register ( slcr )UART1_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
UART1_REF_CTRL | 0XFF5E0078 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_UART1_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | 2 | 20000 | 6 bit divider
PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 28 | 2800 | 6 bit divider
PSU_CRL_APB_UART1_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_UART1_REF_CTRL@0XFF5E0078 | 31:0 | 13f3f07 |  | 1022800 | This register controls this reference clock

## Register ( slcr )I2C0_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
I2C0_REF_CTRL | 0XFF5E0120 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_I2C0_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | 2 | 20000 | 6 bit divider
PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 28 | 2800 | 6 bit divider
PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_I2C0_REF_CTRL@0XFF5E0120 | 31:0 | 13f3f07 |  | 1022800 | This register controls this reference clock

## Register ( slcr )I2C1_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
I2C1_REF_CTRL | 0XFF5E0124 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_I2C1_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | a | a0000 | 6 bit divider
PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 32 | 3200 | 6 bit divider
PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_I2C1_REF_CTRL@0XFF5E0124 | 31:0 | 13f3f07 |  | 10a3200 | This register controls this reference clock

## Register ( slcr )SPI0_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
SPI0_REF_CTRL | 0XFF5E007C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_SPI0_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | 2 | 20000 | 6 bit divider
PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 28 | 2800 | 6 bit divider
PSU_CRL_APB_SPI0_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_SPI0_REF_CTRL@0XFF5E007C | 31:0 | 13f3f07 |  | 1022800 | This register controls this reference clock

## Register ( slcr )SPI1_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
SPI1_REF_CTRL | 0XFF5E0080 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_SPI1_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | a | a0000 | 6 bit divider
PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 32 | 3200 | 6 bit divider
PSU_CRL_APB_SPI1_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_SPI1_REF_CTRL@0XFF5E0080 | 31:0 | 13f3f07 |  | 10a3200 | This register controls this reference clock

## Register ( slcr )CAN0_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
CAN0_REF_CTRL | 0XFF5E0084 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_CAN0_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | 2 | 20000 | 6 bit divider
PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 28 | 2800 | 6 bit divider
PSU_CRL_APB_CAN0_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_CAN0_REF_CTRL@0XFF5E0084 | 31:0 | 13f3f07 |  | 1022800 | This register controls this reference clock

## Register ( slcr )CAN1_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
CAN1_REF_CTRL | 0XFF5E0088 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_CAN1_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | 2 | 20000 | 6 bit divider
PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 28 | 2800 | 6 bit divider
PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_CAN1_REF_CTRL@0XFF5E0088 | 31:0 | 13f3f07 |  | 1022800 | This register controls this reference clock

## Register ( slcr )CPU_R5_CTRL

Register Name | Address | Width | Type | Reset Value | Description
CPU_R5_CTRL | 0XFF5E0090 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_CPU_R5_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 | 13:8 | 3f00 | 3f | 3f00 | 6 bit divider
PSU_CRL_APB_CPU_R5_CTRL_SRCSEL | 2:0 | 7 | 2 | 2 | 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_CPU_R5_CTRL@0XFF5E0090 | 31:0 | 1003f07 |  | 1003f02 | This register controls this reference clock

## Register ( slcr )IOU_SWITCH_CTRL

Register Name | Address | Width | Type | Reset Value | Description
IOU_SWITCH_CTRL | 0XFF5E009C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 | 13:8 | 3f00 | 6 | 600 | 6 bit divider
PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_IOU_SWITCH_CTRL@0XFF5E009C | 31:0 | 1003f07 |  | 1000600 | This register controls this reference clock

## Register ( slcr )PCAP_CTRL

Register Name | Address | Width | Type | Reset Value | Description
PCAP_CTRL | 0XFF5E00A4 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_PCAP_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_PCAP_CTRL_DIVISOR0 | 13:8 | 3f00 | 8 | 800 | 6 bit divider
PSU_CRL_APB_PCAP_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_PCAP_CTRL@0XFF5E00A4 | 31:0 | 1003f07 |  | 1000800 | This register controls this reference clock

## Register ( slcr )LPD_SWITCH_CTRL

Register Name | Address | Width | Type | Reset Value | Description
LPD_SWITCH_CTRL | 0XFF5E00A8 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 | 13:8 | 3f00 | 4 | 400 | 6 bit divider
PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL | 2:0 | 7 | 2 | 2 | 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_LPD_SWITCH_CTRL@0XFF5E00A8 | 31:0 | 1003f07 |  | 1000402 | This register controls this reference clock

## Register ( slcr )LPD_LSBUS_CTRL

Register Name | Address | Width | Type | Reset Value | Description
LPD_LSBUS_CTRL | 0XFF5E00AC | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 | 13:8 | 3f00 | 14 | 1400 | 6 bit divider
PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL | 2:0 | 7 | 2 | 2 | 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_LPD_LSBUS_CTRL@0XFF5E00AC | 31:0 | 1003f07 |  | 1001402 | This register controls this reference clock

## Register ( slcr )DBG_LPD_CTRL

Register Name | Address | Width | Type | Reset Value | Description
DBG_LPD_CTRL | 0XFF5E00B0 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_DBG_LPD_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 | 13:8 | 3f00 | 3f | 3f00 | 6 bit divider
PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_DBG_LPD_CTRL@0XFF5E00B0 | 31:0 | 1003f07 |  | 1003f00 | This register controls this reference clock

## Register ( slcr )NAND_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
NAND_REF_CTRL | 0XFF5E00B4 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_NAND_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_NAND_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | 2 | 20000 | 6 bit divider
PSU_CRL_APB_NAND_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 32 | 3200 | 6 bit divider
PSU_CRL_APB_NAND_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_NAND_REF_CTRL@0XFF5E00B4 | 31:0 | 13f3f07 |  | 1023200 | This register controls this reference clock

## Register ( slcr )ADMA_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
ADMA_REF_CTRL | 0XFF5E00B8 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_ADMA_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 4 | 400 | 6 bit divider
PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL | 2:0 | 7 | 2 | 2 | 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_ADMA_REF_CTRL@0XFF5E00B8 | 31:0 | 1003f07 |  | 1000402 | This register controls this reference clock

## Register ( slcr )AMS_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
AMS_REF_CTRL | 0XFF5E0108 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | 1 | 10000 | 6 bit divider
PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 28 | 2800 | 6 bit divider
PSU_CRL_APB_AMS_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_AMS_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_AMS_REF_CTRL@0XFF5E0108 | 31:0 | 13f3f07 |  | 1012800 | This register controls this reference clock

## Register ( slcr )DLL_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
DLL_REF_CTRL | 0XFF5E0104 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_DLL_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_DLL_REF_CTRL@0XFF5E0104 | 31:0 | 7 |  | 0 | This register controls this reference clock

## Register ( slcr )TIMESTAMP_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
TIMESTAMP_REF_CTRL | 0XFF5E0128 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 14 | 1400 | 6 bit divider
PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL | 2:0 | 7 | 2 | 2 | 1XX = pss_ref_clk; 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRL_APB_TIMESTAMP_REF_CTRL@0XFF5E0128 | 31:0 | 1003f07 |  | 1001402 | This register controls this reference clock

## Register ( slcr )PCIE_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
PCIE_REF_CTRL | 0XFD1A00B4 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_PCIE_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 3f | 3f00 | 6 bit divider
PSU_CRF_APB_PCIE_REF_CTRL@0XFD1A00B4 | 31:0 | 1003f07 |  | 1003f00 | This register controls this reference clock

## Register ( slcr )DP_VIDEO_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
DP_VIDEO_REF_CTRL | 0XFD1A0070 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | 15 | 150000 | 6 bit divider
PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 32 | 3200 | 6 bit divider
PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = VPLL; 010 = DPLL; 011 = RPLL - might be using extra mux; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRF_APB_DP_VIDEO_REF_CTRL@0XFD1A0070 | 31:0 | 13f3f07 |  | 1153200 | This register controls this reference clock

## Register ( slcr )DP_AUDIO_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
DP_AUDIO_REF_CTRL | 0XFD1A0074 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | 2 | 20000 | 6 bit divider
PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 2a | 2a00 | 6 bit divider
PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = VPLL; 010 = DPLL; 011 = RPLL - might be using extra mux; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRF_APB_DP_AUDIO_REF_CTRL@0XFD1A0074 | 31:0 | 13f3f07 |  | 1022a00 | This register controls this reference clock

## Register ( slcr )DP_STC_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
DP_STC_REF_CTRL | 0XFD1A007C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1 | 21:16 | 3f0000 | 2 | 20000 | 6 bit divider
PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 2a | 2a00 | 6 bit divider
PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = VPLL; 010 = DPLL; 011 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRF_APB_DP_STC_REF_CTRL@0XFD1A007C | 31:0 | 13f3f07 |  | 1022a00 | This register controls this reference clock

## Register ( slcr )ACPU_CTRL

Register Name | Address | Width | Type | Reset Value | Description
ACPU_CTRL | 0XFD1A0060 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_ACPU_CTRL_DIVISOR0 | 13:8 | 3f00 | 3f | 3f00 | 6 bit divider
PSU_CRF_APB_ACPU_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF | 25:25 | 2000000 | 1 | 2000000 | Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock
PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed clock to the entire APU
PSU_CRF_APB_ACPU_CTRL@0XFD1A0060 | 31:0 | 3003f07 |  | 3003f00 | This register controls this reference clock

## Register ( slcr )DBG_TRACE_CTRL

Register Name | Address | Width | Type | Reset Value | Description
DBG_TRACE_CTRL | 0XFD1A0064 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_DBG_TRACE_CTRL_DIVISOR0 | 13:8 | 3f00 | 3f | 3f00 | 6 bit divider
PSU_CRF_APB_DBG_TRACE_CTRL_SRCSEL | 2:0 | 7 | 2 | 2 | 000 = IOPLL; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_DBG_TRACE_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRF_APB_DBG_TRACE_CTRL@0XFD1A0064 | 31:0 | 1003f07 |  | 1003f02 | This register controls this reference clock

## Register ( slcr )DBG_FPD_CTRL

Register Name | Address | Width | Type | Reset Value | Description
DBG_FPD_CTRL | 0XFD1A0068 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0 | 13:8 | 3f00 | 3f | 3f00 | 6 bit divider
PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL | 2:0 | 7 | 2 | 2 | 000 = IOPLL; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_DBG_FPD_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRF_APB_DBG_FPD_CTRL@0XFD1A0068 | 31:0 | 1003f07 |  | 1003f02 | This register controls this reference clock

## Register ( slcr )DDR_CTRL

Register Name | Address | Width | Type | Reset Value | Description
DDR_CTRL | 0XFD1A0080 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_DDR_CTRL_DIVISOR0 | 13:8 | 3f00 | a | a00 | 6 bit divider
PSU_CRF_APB_DDR_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_DDR_CTRL@0XFD1A0080 | 31:0 | 3f07 |  | a00 | This register controls this reference clock

## Register ( slcr )GPU_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
GPU_REF_CTRL | 0XFD1A0084 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 3f | 3f00 | 6 bit divider
PSU_CRF_APB_GPU_REF_CTRL_SRCSEL | 2:0 | 7 | 2 | 2 | 000 = IOPLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_GPU_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock. Will stop clock for both Pixel Processors below
PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT | 25:25 | 2000000 | 1 | 2000000 | Clock active signal for Pixel Processor. Switch to 0 to disable the clock
PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT | 26:26 | 4000000 | 1 | 4000000 | Clock active signal for Pixel Processor. Switch to 0 to disable the clock
PSU_CRF_APB_GPU_REF_CTRL@0XFD1A0084 | 31:0 | 7003f07 |  | 7003f02 | This register controls this reference clock

## Register ( slcr )GDMA_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
GDMA_REF_CTRL | 0XFD1A00B8 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 3 | 300 | 6 bit divider
PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL | 2:0 | 7 | 3 | 3 | 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_GDMA_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRF_APB_GDMA_REF_CTRL@0XFD1A00B8 | 31:0 | 1003f07 |  | 1000303 | This register controls this reference clock

## Register ( slcr )DPDMA_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
DPDMA_REF_CTRL | 0XFD1A00BC | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 3 | 300 | 6 bit divider
PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL | 2:0 | 7 | 3 | 3 | 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRF_APB_DPDMA_REF_CTRL@0XFD1A00BC | 31:0 | 1003f07 |  | 1000303 | This register controls this reference clock

## Register ( slcr )TOPSW_MAIN_CTRL

Register Name | Address | Width | Type | Reset Value | Description
TOPSW_MAIN_CTRL | 0XFD1A00C0 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0 | 13:8 | 3f00 | 3 | 300 | 6 bit divider
PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL | 2:0 | 7 | 3 | 3 | 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRF_APB_TOPSW_MAIN_CTRL@0XFD1A00C0 | 31:0 | 1003f07 |  | 1000303 | This register controls this reference clock

## Register ( slcr )TOPSW_LSBUS_CTRL

Register Name | Address | Width | Type | Reset Value | Description
TOPSW_LSBUS_CTRL | 0XFD1A00C4 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0 | 13:8 | 3f00 | 14 | 1400 | 6 bit divider
PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL | 2:0 | 7 | 0 | 0 | 000 = APLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRF_APB_TOPSW_LSBUS_CTRL@0XFD1A00C4 | 31:0 | 1003f07 |  | 1001400 | This register controls this reference clock

## Register ( slcr )GTGREF0_REF_CTRL

Register Name | Address | Width | Type | Reset Value | Description
GTGREF0_REF_CTRL | 0XFD1A00C8 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_GTGREF0_REF_CTRL_DIVISOR0 | 13:8 | 3f00 | 11 | 1100 | 6 bit divider
PSU_CRF_APB_GTGREF0_REF_CTRL_SRCSEL | 2:0 | 7 | 2 | 2 | 000 = IOPLL; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_GTGREF0_REF_CTRL_CLKACT | 24:24 | 1000000 | 1 | 1000000 | Clock active signal. Switch to 0 to disable the clock
PSU_CRF_APB_GTGREF0_REF_CTRL@0XFD1A00C8 | 31:0 | 1003f07 |  | 1001102 | This register controls this reference clock

## Register ( slcr )DBG_TSTMP_CTRL

Register Name | Address | Width | Type | Reset Value | Description
DBG_TSTMP_CTRL | 0XFD1A00F8 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0 | 13:8 | 3f00 | 8 | 800 | 6 bit divider
PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL | 2:0 | 7 | 2 | 2 | 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
PSU_CRF_APB_DBG_TSTMP_CTRL@0XFD1A00F8 | 31:0 | 3f07 |  | 802 | This register controls this reference clock

## psu_ddr_init_data_3_0

Register Name | Address | Width | Type | Reset Value | Description

## psu_ddr_init_data_3_0

Register Name | Address | Width | Type | Reset Value | Description

## psu_mio_init_data

Register Name | Address | Width | Type | Reset Value | Description
PSU_IOU_SLCR_MIO_PIN_0 | 0XFF180000 | 32 | RW | 0x000000 | Configures MIO Pin 0 peripheral interface mapping. S
PSU_IOU_SLCR_MIO_PIN_1 | 0XFF180004 | 32 | RW | 0x000000 | Configures MIO Pin 1 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_2 | 0XFF180008 | 32 | RW | 0x000000 | Configures MIO Pin 2 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_3 | 0XFF18000C | 32 | RW | 0x000000 | Configures MIO Pin 3 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_4 | 0XFF180010 | 32 | RW | 0x000000 | Configures MIO Pin 4 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_5 | 0XFF180014 | 32 | RW | 0x000000 | Configures MIO Pin 5 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_6 | 0XFF180018 | 32 | RW | 0x000000 | Configures MIO Pin 6 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_7 | 0XFF18001C | 32 | RW | 0x000000 | Configures MIO Pin 7 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_8 | 0XFF180020 | 32 | RW | 0x000000 | Configures MIO Pin 8 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_9 | 0XFF180024 | 32 | RW | 0x000000 | Configures MIO Pin 9 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_10 | 0XFF180028 | 32 | RW | 0x000000 | Configures MIO Pin 10 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_11 | 0XFF18002C | 32 | RW | 0x000000 | Configures MIO Pin 11 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_12 | 0XFF180030 | 32 | RW | 0x000000 | Configures MIO Pin 12 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_13 | 0XFF180034 | 32 | RW | 0x000000 | Configures MIO Pin 13 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_14 | 0XFF180038 | 32 | RW | 0x000000 | Configures MIO Pin 14 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_15 | 0XFF18003C | 32 | RW | 0x000000 | Configures MIO Pin 15 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_16 | 0XFF180040 | 32 | RW | 0x000000 | Configures MIO Pin 16 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_17 | 0XFF180044 | 32 | RW | 0x000000 | Configures MIO Pin 17 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_18 | 0XFF180048 | 32 | RW | 0x000000 | Configures MIO Pin 18 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_19 | 0XFF18004C | 32 | RW | 0x000000 | Configures MIO Pin 19 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_20 | 0XFF180050 | 32 | RW | 0x000000 | Configures MIO Pin 20 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_21 | 0XFF180054 | 32 | RW | 0x000000 | Configures MIO Pin 21 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_22 | 0XFF180058 | 32 | RW | 0x000000 | Configures MIO Pin 22 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_23 | 0XFF18005C | 32 | RW | 0x000000 | Configures MIO Pin 23 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_24 | 0XFF180060 | 32 | RW | 0x000000 | Configures MIO Pin 24 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_25 | 0XFF180064 | 32 | RW | 0x000000 | Configures MIO Pin 25 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_26 | 0XFF180068 | 32 | RW | 0x000000 | Configures MIO Pin 26 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_27 | 0XFF18006C | 32 | RW | 0x000000 | Configures MIO Pin 27 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_28 | 0XFF180070 | 32 | RW | 0x000000 | Configures MIO Pin 28 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_29 | 0XFF180074 | 32 | RW | 0x000000 | Configures MIO Pin 29 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_30 | 0XFF180078 | 32 | RW | 0x000000 | Configures MIO Pin 30 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_31 | 0XFF18007C | 32 | RW | 0x000000 | Configures MIO Pin 31 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_32 | 0XFF180080 | 32 | RW | 0x000000 | Configures MIO Pin 32 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_33 | 0XFF180084 | 32 | RW | 0x000000 | Configures MIO Pin 33 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_34 | 0XFF180088 | 32 | RW | 0x000000 | Configures MIO Pin 34 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_35 | 0XFF18008C | 32 | RW | 0x000000 | Configures MIO Pin 35 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_36 | 0XFF180090 | 32 | RW | 0x000000 | Configures MIO Pin 36 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_37 | 0XFF180094 | 32 | RW | 0x000000 | Configures MIO Pin 37 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_38 | 0XFF180098 | 32 | RW | 0x000000 | Configures MIO Pin 38 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_39 | 0XFF18009C | 32 | RW | 0x000000 | Configures MIO Pin 39 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_40 | 0XFF1800A0 | 32 | RW | 0x000000 | Configures MIO Pin 40 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_41 | 0XFF1800A4 | 32 | RW | 0x000000 | Configures MIO Pin 41 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_42 | 0XFF1800A8 | 32 | RW | 0x000000 | Configures MIO Pin 42 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_43 | 0XFF1800AC | 32 | RW | 0x000000 | Configures MIO Pin 43 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_44 | 0XFF1800B0 | 32 | RW | 0x000000 | Configures MIO Pin 44 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_45 | 0XFF1800B4 | 32 | RW | 0x000000 | Configures MIO Pin 45 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_46 | 0XFF1800B8 | 32 | RW | 0x000000 | Configures MIO Pin 46 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_47 | 0XFF1800BC | 32 | RW | 0x000000 | Configures MIO Pin 47 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_48 | 0XFF1800C0 | 32 | RW | 0x000000 | Configures MIO Pin 48 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_49 | 0XFF1800C4 | 32 | RW | 0x000000 | Configures MIO Pin 49 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_50 | 0XFF1800C8 | 32 | RW | 0x000000 | Configures MIO Pin 50 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_51 | 0XFF1800CC | 32 | RW | 0x000000 | Configures MIO Pin 51 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_52 | 0XFF1800D0 | 32 | RW | 0x000000 | Configures MIO Pin 52 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_53 | 0XFF1800D4 | 32 | RW | 0x000000 | Configures MIO Pin 53 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_54 | 0XFF1800D8 | 32 | RW | 0x000000 | Configures MIO Pin 54 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_55 | 0XFF1800DC | 32 | RW | 0x000000 | Configures MIO Pin 55 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_56 | 0XFF1800E0 | 32 | RW | 0x000000 | Configures MIO Pin 56 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_57 | 0XFF1800E4 | 32 | RW | 0x000000 | Configures MIO Pin 57 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_58 | 0XFF1800E8 | 32 | RW | 0x000000 | Configures MIO Pin 58 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_59 | 0XFF1800EC | 32 | RW | 0x000000 | Configures MIO Pin 59 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_60 | 0XFF1800F0 | 32 | RW | 0x000000 | Configures MIO Pin 60 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_61 | 0XFF1800F4 | 32 | RW | 0x000000 | Configures MIO Pin 61 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_62 | 0XFF1800F8 | 32 | RW | 0x000000 | Configures MIO Pin 62 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_63 | 0XFF1800FC | 32 | RW | 0x000000 | Configures MIO Pin 63 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_64 | 0XFF180100 | 32 | RW | 0x000000 | Configures MIO Pin 64 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_65 | 0XFF180104 | 32 | RW | 0x000000 | Configures MIO Pin 65 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_66 | 0XFF180108 | 32 | RW | 0x000000 | Configures MIO Pin 66 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_67 | 0XFF18010C | 32 | RW | 0x000000 | Configures MIO Pin 67 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_68 | 0XFF180110 | 32 | RW | 0x000000 | Configures MIO Pin 68 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_69 | 0XFF180114 | 32 | RW | 0x000000 | Configures MIO Pin 69 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_70 | 0XFF180118 | 32 | RW | 0x000000 | Configures MIO Pin 70 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_71 | 0XFF18011C | 32 | RW | 0x000000 | Configures MIO Pin 71 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_72 | 0XFF180120 | 32 | RW | 0x000000 | Configures MIO Pin 72 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_73 | 0XFF180124 | 32 | RW | 0x000000 | Configures MIO Pin 73 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_74 | 0XFF180128 | 32 | RW | 0x000000 | Configures MIO Pin 74 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_75 | 0XFF18012C | 32 | RW | 0x000000 | Configures MIO Pin 75 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_76 | 0XFF180130 | 32 | RW | 0x000000 | Configures MIO Pin 76 peripheral interface mapping
PSU_IOU_SLCR_MIO_PIN_77 | 0XFF180134 | 32 | RW | 0x000000 | Configures MIO Pin 77 peripheral interface mapping
PSU_IOU_SLCR_MIO_MST_TRI0 | 0XFF180204 | 32 | RW | 0x000000 | MIO pin Tri-state Enables, 31:0
PSU_IOU_SLCR_MIO_MST_TRI1 | 0XFF180208 | 32 | RW | 0x000000 | MIO pin Tri-state Enables, 63:32
PSU_IOU_SLCR_MIO_MST_TRI2 | 0XFF18020C | 32 | RW | 0x000000 | MIO pin Tri-state Enables, 77:64
PSU_IOU_SLCR_MIO_LOOPBACK | 0XFF180200 | 32 | RW | 0x000000 | Loopback function within MIO

## psu_mio_init_data

Register Name | Address | Width | Type | Reset Value | Description

# MIO PROGRAMMING

## Register ( slcr )MIO_PIN_0

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_0 | 0XFF180000 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_0_L0_SEL | 1:1 | 2 | 1 | 2 | Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)
PSU_IOU_SLCR_MIO_PIN_0_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_0_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0]- (Test Scan Port) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_0_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_clk- (Trace Port Clock)
PSU_IOU_SLCR_MIO_PIN_0@0XFF180000 | 31:0 | fe |  | 2 | Configures MIO Pin 0 peripheral interface mapping. S

## Register ( slcr )MIO_PIN_1

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_1 | 0XFF180004 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_1_L0_SEL | 1:1 | 2 | 1 | 2 | Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus)
PSU_IOU_SLCR_MIO_PIN_1_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_1_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1]- (Test Scan Port) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_1_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control Signal)
PSU_IOU_SLCR_MIO_PIN_1@0XFF180004 | 31:0 | fe |  | 2 | Configures MIO Pin 1 peripheral interface mapping

## Register ( slcr )MIO_PIN_2

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_2 | 0XFF180008 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_2_L0_SEL | 1:1 | 2 | 1 | 2 | Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
PSU_IOU_SLCR_MIO_PIN_2_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_2_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2]- (Test Scan Port) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_2_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_2@0XFF180008 | 31:0 | fe |  | 2 | Configures MIO Pin 2 peripheral interface mapping

## Register ( slcr )MIO_PIN_3

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_3 | 0XFF18000C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_3_L0_SEL | 1:1 | 2 | 1 | 2 | Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
PSU_IOU_SLCR_MIO_PIN_3_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_3_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3]- (Test Scan Port) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_3_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_3@0XFF18000C | 31:0 | fe |  | 2 | Configures MIO Pin 3 peripheral interface mapping

## Register ( slcr )MIO_PIN_4

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_4 | 0XFF180010 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_4_L0_SEL | 1:1 | 2 | 1 | 2 | Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus)
PSU_IOU_SLCR_MIO_PIN_4_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_4_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4]- (Test Scan Port) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_4_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[2]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_4@0XFF180010 | 31:0 | fe |  | 2 | Configures MIO Pin 4 peripheral interface mapping

## Register ( slcr )MIO_PIN_5

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_5 | 0XFF180014 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_5_L0_SEL | 1:1 | 2 | 1 | 2 | Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)
PSU_IOU_SLCR_MIO_PIN_5_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_5_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5]- (Test Scan Port) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_5_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[3]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_5@0XFF180014 | 31:0 | fe |  | 2 | Configures MIO Pin 5 peripheral interface mapping

## Register ( slcr )MIO_PIN_6

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_6 | 0XFF180018 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_6_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)
PSU_IOU_SLCR_MIO_PIN_6_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_6_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6]- (Test Scan Port) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_6_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_6@0XFF180018 | 31:0 | fe |  | 0 | Configures MIO Pin 6 peripheral interface mapping

## Register ( slcr )MIO_PIN_7

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_7 | 0XFF18001C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_7_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)
PSU_IOU_SLCR_MIO_PIN_7_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_7_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7]- (Test Scan Port) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_7_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_7@0XFF18001C | 31:0 | fe |  | 0 | Configures MIO Pin 7 peripheral interface mapping

## Register ( slcr )MIO_PIN_8

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_8 | 0XFF180020 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_8_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus)
PSU_IOU_SLCR_MIO_PIN_8_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_8_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8]- (Test Scan Port) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_8_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_8@0XFF180020 | 31:0 | fe |  | 0 | Configures MIO Pin 8 peripheral interface mapping

## Register ( slcr )MIO_PIN_9

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_9 | 0XFF180024 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_9_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus)
PSU_IOU_SLCR_MIO_PIN_9_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
PSU_IOU_SLCR_MIO_PIN_9_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9]- (Test Scan Port) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_9_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_9@0XFF180024 | 31:0 | fe |  | 0 | Configures MIO Pin 9 peripheral interface mapping

## Register ( slcr )MIO_PIN_10

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_10 | 0XFF180028 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_10_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus)
PSU_IOU_SLCR_MIO_PIN_10_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
PSU_IOU_SLCR_MIO_PIN_10_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[10]- (Test Scan Port) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_10_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[8]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_10@0XFF180028 | 31:0 | fe |  | 4 | Configures MIO Pin 10 peripheral interface mapping

## Register ( slcr )MIO_PIN_11

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_11 | 0XFF18002C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_11_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus)
PSU_IOU_SLCR_MIO_PIN_11_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
PSU_IOU_SLCR_MIO_PIN_11_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[11]- (Test Scan Port) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_11_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[9]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_11@0XFF18002C | 31:0 | fe |  | 4 | Configures MIO Pin 11 peripheral interface mapping

## Register ( slcr )MIO_PIN_12

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_12 | 0XFF180030 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_12_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)
PSU_IOU_SLCR_MIO_PIN_12_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe)
PSU_IOU_SLCR_MIO_PIN_12_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[12]- (Test Scan Port) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_12_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[10]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_12@0XFF180030 | 31:0 | fe |  | 0 | Configures MIO Pin 12 peripheral interface mapping

## Register ( slcr )MIO_PIN_13

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_13 | 0XFF180034 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_13_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_13_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)
PSU_IOU_SLCR_MIO_PIN_13_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_13_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_13@0XFF180034 | 31:0 | fe |  | 4 | Configures MIO Pin 13 peripheral interface mapping

## Register ( slcr )MIO_PIN_14

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_14 | 0XFF180038 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_14_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_14_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)
PSU_IOU_SLCR_MIO_PIN_14_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_14_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_14@0XFF180038 | 31:0 | fe |  | 4 | Configures MIO Pin 14 peripheral interface mapping

## Register ( slcr )MIO_PIN_15

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_15 | 0XFF18003C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_15_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_15_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)
PSU_IOU_SLCR_MIO_PIN_15_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_15_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_15@0XFF18003C | 31:0 | fe |  | 4 | Configures MIO Pin 15 peripheral interface mapping

## Register ( slcr )MIO_PIN_16

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_16 | 0XFF180040 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_16_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_16_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus)
PSU_IOU_SLCR_MIO_PIN_16_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_16_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[14]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_16@0XFF180040 | 31:0 | fe |  | 4 | Configures MIO Pin 16 peripheral interface mapping

## Register ( slcr )MIO_PIN_17

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_17 | 0XFF180044 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_17_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_17_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus)
PSU_IOU_SLCR_MIO_PIN_17_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_17_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[15]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_17@0XFF180044 | 31:0 | fe |  | 4 | Configures MIO Pin 17 peripheral interface mapping

## Register ( slcr )MIO_PIN_18

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_18 | 0XFF180048 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_18_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_18_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus)
PSU_IOU_SLCR_MIO_PIN_18_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
PSU_IOU_SLCR_MIO_PIN_18_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_18@0XFF180048 | 31:0 | fe |  | 4 | Configures MIO Pin 18 peripheral interface mapping

## Register ( slcr )MIO_PIN_19

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_19 | 0XFF18004C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_19_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_19_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus)
PSU_IOU_SLCR_MIO_PIN_19_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
PSU_IOU_SLCR_MIO_PIN_19_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_19@0XFF18004C | 31:0 | fe |  | 4 | Configures MIO Pin 19 peripheral interface mapping

## Register ( slcr )MIO_PIN_20

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_20 | 0XFF180050 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_20_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_20_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus)
PSU_IOU_SLCR_MIO_PIN_20_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
PSU_IOU_SLCR_MIO_PIN_20_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_20@0XFF180050 | 31:0 | fe |  | 4 | Configures MIO Pin 20 peripheral interface mapping

## Register ( slcr )MIO_PIN_21

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_21 | 0XFF180054 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_21_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_21_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus)
PSU_IOU_SLCR_MIO_PIN_21_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
PSU_IOU_SLCR_MIO_PIN_21_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_21@0XFF180054 | 31:0 | fe |  | 4 | Configures MIO Pin 21 peripheral interface mapping

## Register ( slcr )MIO_PIN_22

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_22 | 0XFF180058 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_22_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_22_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)
PSU_IOU_SLCR_MIO_PIN_22_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
PSU_IOU_SLCR_MIO_PIN_22_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_22@0XFF180058 | 31:0 | fe |  | 4 | Configures MIO Pin 22 peripheral interface mapping

## Register ( slcr )MIO_PIN_23

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_23 | 0XFF18005C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_23_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_23_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus)
PSU_IOU_SLCR_MIO_PIN_23_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
PSU_IOU_SLCR_MIO_PIN_23_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_23@0XFF18005C | 31:0 | fe |  | 4 | Configures MIO Pin 23 peripheral interface mapping

## Register ( slcr )MIO_PIN_24

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_24 | 0XFF180060 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_24_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_24_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus)
PSU_IOU_SLCR_MIO_PIN_24_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
PSU_IOU_SLCR_MIO_PIN_24_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_24@0XFF180060 | 31:0 | fe |  | 4 | Configures MIO Pin 24 peripheral interface mapping

## Register ( slcr )MIO_PIN_25

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_25 | 0XFF180064 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_25_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_25_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)
PSU_IOU_SLCR_MIO_PIN_25_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input, test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
PSU_IOU_SLCR_MIO_PIN_25_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_25@0XFF180064 | 31:0 | fe |  | 4 | Configures MIO Pin 25 peripheral interface mapping

## Register ( slcr )MIO_PIN_26

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_26 | 0XFF180068 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_26_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)
PSU_IOU_SLCR_MIO_PIN_26_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
PSU_IOU_SLCR_MIO_PIN_26_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
PSU_IOU_SLCR_MIO_PIN_26_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_26@0XFF180068 | 31:0 | fe |  | 4 | Configures MIO Pin 26 peripheral interface mapping

## Register ( slcr )MIO_PIN_27

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_27 | 0XFF18006C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_27_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)
PSU_IOU_SLCR_MIO_PIN_27_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
PSU_IOU_SLCR_MIO_PIN_27_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
PSU_IOU_SLCR_MIO_PIN_27_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_27@0XFF18006C | 31:0 | fe |  | 0 | Configures MIO Pin 27 peripheral interface mapping

## Register ( slcr )MIO_PIN_28

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_28 | 0XFF180070 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_28_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)
PSU_IOU_SLCR_MIO_PIN_28_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
PSU_IOU_SLCR_MIO_PIN_28_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
PSU_IOU_SLCR_MIO_PIN_28_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_28@0XFF180070 | 31:0 | fe |  | 0 | Configures MIO Pin 28 peripheral interface mapping

## Register ( slcr )MIO_PIN_29

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_29 | 0XFF180074 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_29_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)
PSU_IOU_SLCR_MIO_PIN_29_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
PSU_IOU_SLCR_MIO_PIN_29_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
PSU_IOU_SLCR_MIO_PIN_29_L3_SEL | 7:5 | e0 | 4 | 80 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_29@0XFF180074 | 31:0 | fe |  | 80 | Configures MIO Pin 29 peripheral interface mapping

## Register ( slcr )MIO_PIN_30

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_30 | 0XFF180078 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_30_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)
PSU_IOU_SLCR_MIO_PIN_30_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
PSU_IOU_SLCR_MIO_PIN_30_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
PSU_IOU_SLCR_MIO_PIN_30_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[8]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_30@0XFF180078 | 31:0 | fe |  | 0 | Configures MIO Pin 30 peripheral interface mapping

## Register ( slcr )MIO_PIN_31

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_31 | 0XFF18007C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_31_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)
PSU_IOU_SLCR_MIO_PIN_31_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
PSU_IOU_SLCR_MIO_PIN_31_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
PSU_IOU_SLCR_MIO_PIN_31_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[9]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_31@0XFF18007C | 31:0 | fe |  | 0 | Configures MIO Pin 31 peripheral interface mapping

## Register ( slcr )MIO_PIN_32

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_32 | 0XFF180080 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_32_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)
PSU_IOU_SLCR_MIO_PIN_32_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe)
PSU_IOU_SLCR_MIO_PIN_32_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
PSU_IOU_SLCR_MIO_PIN_32_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[10]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_32@0XFF180080 | 31:0 | fe |  | 4 | Configures MIO Pin 32 peripheral interface mapping

## Register ( slcr )MIO_PIN_33

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_33 | 0XFF180084 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_33_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)
PSU_IOU_SLCR_MIO_PIN_33_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
PSU_IOU_SLCR_MIO_PIN_33_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
PSU_IOU_SLCR_MIO_PIN_33_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_33@0XFF180084 | 31:0 | fe |  | 0 | Configures MIO Pin 33 peripheral interface mapping

## Register ( slcr )MIO_PIN_34

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_34 | 0XFF180088 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_34_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)
PSU_IOU_SLCR_MIO_PIN_34_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
PSU_IOU_SLCR_MIO_PIN_34_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test Scan Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
PSU_IOU_SLCR_MIO_PIN_34_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_34@0XFF180088 | 31:0 | fe |  | 0 | Configures MIO Pin 34 peripheral interface mapping

## Register ( slcr )MIO_PIN_35

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_35 | 0XFF18008C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_35_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)
PSU_IOU_SLCR_MIO_PIN_35_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
PSU_IOU_SLCR_MIO_PIN_35_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test Scan Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
PSU_IOU_SLCR_MIO_PIN_35_L3_SEL | 7:5 | e0 | 4 | 80 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_35@0XFF18008C | 31:0 | fe |  | 80 | Configures MIO Pin 35 peripheral interface mapping

## Register ( slcr )MIO_PIN_36

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_36 | 0XFF180090 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_36_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)
PSU_IOU_SLCR_MIO_PIN_36_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
PSU_IOU_SLCR_MIO_PIN_36_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test Scan Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
PSU_IOU_SLCR_MIO_PIN_36_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[14]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_36@0XFF180090 | 31:0 | fe |  | 0 | Configures MIO Pin 36 peripheral interface mapping

## Register ( slcr )MIO_PIN_37

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_37 | 0XFF180094 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_37_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )
PSU_IOU_SLCR_MIO_PIN_37_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
PSU_IOU_SLCR_MIO_PIN_37_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test Scan Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
PSU_IOU_SLCR_MIO_PIN_37_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[15]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_37@0XFF180094 | 31:0 | fe |  | 0 | Configures MIO Pin 37 peripheral interface mapping

## Register ( slcr )MIO_PIN_38

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_38 | 0XFF180098 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_38_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)
PSU_IOU_SLCR_MIO_PIN_38_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_38_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
PSU_IOU_SLCR_MIO_PIN_38_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- (Trace Port Clock)
PSU_IOU_SLCR_MIO_PIN_38@0XFF180098 | 31:0 | fe |  | 0 | Configures MIO Pin 38 peripheral interface mapping

## Register ( slcr )MIO_PIN_39

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_39 | 0XFF18009C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_39_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)
PSU_IOU_SLCR_MIO_PIN_39_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_39_L2_SEL | 4:3 | 18 | 2 | 10 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_39_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port Control Signal)
PSU_IOU_SLCR_MIO_PIN_39@0XFF18009C | 31:0 | fe |  | 10 | Configures MIO Pin 39 peripheral interface mapping

## Register ( slcr )MIO_PIN_40

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_40 | 0XFF1800A0 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_40_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)
PSU_IOU_SLCR_MIO_PIN_40_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_40_L2_SEL | 4:3 | 18 | 2 | 10 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_40_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_40@0XFF1800A0 | 31:0 | fe |  | 10 | Configures MIO Pin 40 peripheral interface mapping

## Register ( slcr )MIO_PIN_41

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_41 | 0XFF1800A4 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_41_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)
PSU_IOU_SLCR_MIO_PIN_41_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_41_L2_SEL | 4:3 | 18 | 2 | 10 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_41_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[1]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_41@0XFF1800A4 | 31:0 | fe |  | 10 | Configures MIO Pin 41 peripheral interface mapping

## Register ( slcr )MIO_PIN_42

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_42 | 0XFF1800A8 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_42_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)
PSU_IOU_SLCR_MIO_PIN_42_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_42_L2_SEL | 4:3 | 18 | 2 | 10 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_42_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[2]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_42@0XFF1800A8 | 31:0 | fe |  | 10 | Configures MIO Pin 42 peripheral interface mapping

## Register ( slcr )MIO_PIN_43

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_43 | 0XFF1800AC | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_43_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)
PSU_IOU_SLCR_MIO_PIN_43_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_43_L2_SEL | 4:3 | 18 | 2 | 10 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_43_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[3]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_43@0XFF1800AC | 31:0 | fe |  | 10 | Configures MIO Pin 43 peripheral interface mapping

## Register ( slcr )MIO_PIN_44

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_44 | 0XFF1800B0 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_44_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)
PSU_IOU_SLCR_MIO_PIN_44_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_44_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_44_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_44@0XFF1800B0 | 31:0 | fe |  | 0 | Configures MIO Pin 44 peripheral interface mapping

## Register ( slcr )MIO_PIN_45

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_45 | 0XFF1800B4 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_45_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)
PSU_IOU_SLCR_MIO_PIN_45_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_45_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_45_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_45@0XFF1800B4 | 31:0 | fe |  | 0 | Configures MIO Pin 45 peripheral interface mapping

## Register ( slcr )MIO_PIN_46

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_46 | 0XFF1800B8 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_46_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)
PSU_IOU_SLCR_MIO_PIN_46_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_46_L2_SEL | 4:3 | 18 | 2 | 10 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_46_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_46@0XFF1800B8 | 31:0 | fe |  | 10 | Configures MIO Pin 46 peripheral interface mapping

## Register ( slcr )MIO_PIN_47

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_47 | 0XFF1800BC | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_47_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)
PSU_IOU_SLCR_MIO_PIN_47_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_47_L2_SEL | 4:3 | 18 | 2 | 10 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_47_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_47@0XFF1800BC | 31:0 | fe |  | 10 | Configures MIO Pin 47 peripheral interface mapping

## Register ( slcr )MIO_PIN_48

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_48 | 0XFF1800C0 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_48_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)
PSU_IOU_SLCR_MIO_PIN_48_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_48_L2_SEL | 4:3 | 18 | 2 | 10 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_48_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_48@0XFF1800C0 | 31:0 | fe |  | 10 | Configures MIO Pin 48 peripheral interface mapping

## Register ( slcr )MIO_PIN_49

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_49 | 0XFF1800C4 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_49_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )
PSU_IOU_SLCR_MIO_PIN_49_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_49_L2_SEL | 4:3 | 18 | 2 | 10 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_49_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_49@0XFF1800C4 | 31:0 | fe |  | 10 | Configures MIO Pin 49 peripheral interface mapping

## Register ( slcr )MIO_PIN_50

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_50 | 0XFF1800C8 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_50_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
PSU_IOU_SLCR_MIO_PIN_50_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_50_L2_SEL | 4:3 | 18 | 2 | 10 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_50_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_50@0XFF1800C8 | 31:0 | fe |  | 10 | Configures MIO Pin 50 peripheral interface mapping

## Register ( slcr )MIO_PIN_51

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_51 | 0XFF1800CC | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_51_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
PSU_IOU_SLCR_MIO_PIN_51_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_51_L2_SEL | 4:3 | 18 | 2 | 10 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_51_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_51@0XFF1800CC | 31:0 | fe |  | 10 | Configures MIO Pin 51 peripheral interface mapping

## Register ( slcr )MIO_PIN_52

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_52 | 0XFF1800D0 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_52_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)
PSU_IOU_SLCR_MIO_PIN_52_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)
PSU_IOU_SLCR_MIO_PIN_52_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
PSU_IOU_SLCR_MIO_PIN_52_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_clk- (Trace Port Clock)
PSU_IOU_SLCR_MIO_PIN_52@0XFF1800D0 | 31:0 | fe |  | 4 | Configures MIO Pin 52 peripheral interface mapping

## Register ( slcr )MIO_PIN_53

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_53 | 0XFF1800D4 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_53_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)
PSU_IOU_SLCR_MIO_PIN_53_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)
PSU_IOU_SLCR_MIO_PIN_53_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
PSU_IOU_SLCR_MIO_PIN_53_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control Signal)
PSU_IOU_SLCR_MIO_PIN_53@0XFF1800D4 | 31:0 | fe |  | 4 | Configures MIO Pin 53 peripheral interface mapping

## Register ( slcr )MIO_PIN_54

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_54 | 0XFF1800D8 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_54_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)
PSU_IOU_SLCR_MIO_PIN_54_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus)
PSU_IOU_SLCR_MIO_PIN_54_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
PSU_IOU_SLCR_MIO_PIN_54_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_54@0XFF1800D8 | 31:0 | fe |  | 4 | Configures MIO Pin 54 peripheral interface mapping

## Register ( slcr )MIO_PIN_55

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_55 | 0XFF1800DC | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_55_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)
PSU_IOU_SLCR_MIO_PIN_55_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)
PSU_IOU_SLCR_MIO_PIN_55_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
PSU_IOU_SLCR_MIO_PIN_55_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_55@0XFF1800DC | 31:0 | fe |  | 4 | Configures MIO Pin 55 peripheral interface mapping

## Register ( slcr )MIO_PIN_56

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_56 | 0XFF1800E0 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_56_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)
PSU_IOU_SLCR_MIO_PIN_56_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus)
PSU_IOU_SLCR_MIO_PIN_56_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
PSU_IOU_SLCR_MIO_PIN_56_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[2]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_56@0XFF1800E0 | 31:0 | fe |  | 4 | Configures MIO Pin 56 peripheral interface mapping

## Register ( slcr )MIO_PIN_57

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_57 | 0XFF1800E4 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_57_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)
PSU_IOU_SLCR_MIO_PIN_57_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus)
PSU_IOU_SLCR_MIO_PIN_57_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
PSU_IOU_SLCR_MIO_PIN_57_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[3]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_57@0XFF1800E4 | 31:0 | fe |  | 4 | Configures MIO Pin 57 peripheral interface mapping

## Register ( slcr )MIO_PIN_58

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_58 | 0XFF1800E8 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_58_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)
PSU_IOU_SLCR_MIO_PIN_58_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)
PSU_IOU_SLCR_MIO_PIN_58_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
PSU_IOU_SLCR_MIO_PIN_58_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_58@0XFF1800E8 | 31:0 | fe |  | 4 | Configures MIO Pin 58 peripheral interface mapping

## Register ( slcr )MIO_PIN_59

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_59 | 0XFF1800EC | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_59_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)
PSU_IOU_SLCR_MIO_PIN_59_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus)
PSU_IOU_SLCR_MIO_PIN_59_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
PSU_IOU_SLCR_MIO_PIN_59_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_59@0XFF1800EC | 31:0 | fe |  | 4 | Configures MIO Pin 59 peripheral interface mapping

## Register ( slcr )MIO_PIN_60

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_60 | 0XFF1800F0 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_60_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)
PSU_IOU_SLCR_MIO_PIN_60_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus)
PSU_IOU_SLCR_MIO_PIN_60_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
PSU_IOU_SLCR_MIO_PIN_60_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_60@0XFF1800F0 | 31:0 | fe |  | 4 | Configures MIO Pin 60 peripheral interface mapping

## Register ( slcr )MIO_PIN_61

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_61 | 0XFF1800F4 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_61_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)
PSU_IOU_SLCR_MIO_PIN_61_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus)
PSU_IOU_SLCR_MIO_PIN_61_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
PSU_IOU_SLCR_MIO_PIN_61_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_61@0XFF1800F4 | 31:0 | fe |  | 4 | Configures MIO Pin 61 peripheral interface mapping

## Register ( slcr )MIO_PIN_62

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_62 | 0XFF1800F8 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_62_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)
PSU_IOU_SLCR_MIO_PIN_62_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus)
PSU_IOU_SLCR_MIO_PIN_62_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
PSU_IOU_SLCR_MIO_PIN_62_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[8]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_62@0XFF1800F8 | 31:0 | fe |  | 4 | Configures MIO Pin 62 peripheral interface mapping

## Register ( slcr )MIO_PIN_63

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_63 | 0XFF1800FC | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_63_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )
PSU_IOU_SLCR_MIO_PIN_63_L1_SEL | 2:2 | 4 | 1 | 4 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus)
PSU_IOU_SLCR_MIO_PIN_63_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
PSU_IOU_SLCR_MIO_PIN_63_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[9]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_63@0XFF1800FC | 31:0 | fe |  | 4 | Configures MIO Pin 63 peripheral interface mapping

## Register ( slcr )MIO_PIN_64

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_64 | 0XFF180100 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_64_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)
PSU_IOU_SLCR_MIO_PIN_64_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)
PSU_IOU_SLCR_MIO_PIN_64_L2_SEL | 4:3 | 18 | 1 | 8 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
PSU_IOU_SLCR_MIO_PIN_64_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[10]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_64@0XFF180100 | 31:0 | fe |  | 8 | Configures MIO Pin 64 peripheral interface mapping

## Register ( slcr )MIO_PIN_65

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_65 | 0XFF180104 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_65_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)
PSU_IOU_SLCR_MIO_PIN_65_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)
PSU_IOU_SLCR_MIO_PIN_65_L2_SEL | 4:3 | 18 | 1 | 8 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used
PSU_IOU_SLCR_MIO_PIN_65_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_65@0XFF180104 | 31:0 | fe |  | 8 | Configures MIO Pin 65 peripheral interface mapping

## Register ( slcr )MIO_PIN_66

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_66 | 0XFF180108 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_66_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)
PSU_IOU_SLCR_MIO_PIN_66_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus)
PSU_IOU_SLCR_MIO_PIN_66_L2_SEL | 4:3 | 18 | 1 | 8 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not Used 3= Not Used
PSU_IOU_SLCR_MIO_PIN_66_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_66@0XFF180108 | 31:0 | fe |  | 8 | Configures MIO Pin 66 peripheral interface mapping

## Register ( slcr )MIO_PIN_67

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_67 | 0XFF18010C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_67_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)
PSU_IOU_SLCR_MIO_PIN_67_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)
PSU_IOU_SLCR_MIO_PIN_67_L2_SEL | 4:3 | 18 | 1 | 8 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= Not Used 3= Not Used
PSU_IOU_SLCR_MIO_PIN_67_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_67@0XFF18010C | 31:0 | fe |  | 8 | Configures MIO Pin 67 peripheral interface mapping

## Register ( slcr )MIO_PIN_68

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_68 | 0XFF180110 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_68_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)
PSU_IOU_SLCR_MIO_PIN_68_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus)
PSU_IOU_SLCR_MIO_PIN_68_L2_SEL | 4:3 | 18 | 1 | 8 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= Not Used 3= Not Used
PSU_IOU_SLCR_MIO_PIN_68_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[14]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_68@0XFF180110 | 31:0 | fe |  | 8 | Configures MIO Pin 68 peripheral interface mapping

## Register ( slcr )MIO_PIN_69

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_69 | 0XFF180114 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_69_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)
PSU_IOU_SLCR_MIO_PIN_69_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus)
PSU_IOU_SLCR_MIO_PIN_69_L2_SEL | 4:3 | 18 | 1 | 8 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_69_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[15]- (Trace Port Databus)
PSU_IOU_SLCR_MIO_PIN_69@0XFF180114 | 31:0 | fe |  | 8 | Configures MIO Pin 69 peripheral interface mapping

## Register ( slcr )MIO_PIN_70

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_70 | 0XFF180118 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_70_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)
PSU_IOU_SLCR_MIO_PIN_70_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)
PSU_IOU_SLCR_MIO_PIN_70_L2_SEL | 4:3 | 18 | 1 | 8 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_70_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_70@0XFF180118 | 31:0 | fe |  | 8 | Configures MIO Pin 70 peripheral interface mapping

## Register ( slcr )MIO_PIN_71

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_71 | 0XFF18011C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_71_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)
PSU_IOU_SLCR_MIO_PIN_71_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data bus)
PSU_IOU_SLCR_MIO_PIN_71_L2_SEL | 4:3 | 18 | 1 | 8 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_71_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_71@0XFF18011C | 31:0 | fe |  | 8 | Configures MIO Pin 71 peripheral interface mapping

## Register ( slcr )MIO_PIN_72

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_72 | 0XFF180120 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_72_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)
PSU_IOU_SLCR_MIO_PIN_72_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus)
PSU_IOU_SLCR_MIO_PIN_72_L2_SEL | 4:3 | 18 | 1 | 8 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_72_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_72@0XFF180120 | 31:0 | fe |  | 8 | Configures MIO Pin 72 peripheral interface mapping

## Register ( slcr )MIO_PIN_73

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_73 | 0XFF180124 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_73_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)
PSU_IOU_SLCR_MIO_PIN_73_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus)
PSU_IOU_SLCR_MIO_PIN_73_L2_SEL | 4:3 | 18 | 1 | 8 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_73_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_73@0XFF180124 | 31:0 | fe |  | 8 | Configures MIO Pin 73 peripheral interface mapping

## Register ( slcr )MIO_PIN_74

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_74 | 0XFF180128 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_74_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)
PSU_IOU_SLCR_MIO_PIN_74_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus)
PSU_IOU_SLCR_MIO_PIN_74_L2_SEL | 4:3 | 18 | 1 | 8 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_74_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_74@0XFF180128 | 31:0 | fe |  | 8 | Configures MIO Pin 74 peripheral interface mapping

## Register ( slcr )MIO_PIN_75

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_75 | 0XFF18012C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_75_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )
PSU_IOU_SLCR_MIO_PIN_75_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus)
PSU_IOU_SLCR_MIO_PIN_75_L2_SEL | 4:3 | 18 | 1 | 8 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_75_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_75@0XFF18012C | 31:0 | fe |  | 8 | Configures MIO Pin 75 peripheral interface mapping

## Register ( slcr )MIO_PIN_76

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_76 | 0XFF180130 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_76_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_76_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_76_L2_SEL | 4:3 | 18 | 1 | 8 | Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_76_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_76@0XFF180130 | 31:0 | fe |  | 8 | Configures MIO Pin 76 peripheral interface mapping

## Register ( slcr )MIO_PIN_77

Register Name | Address | Width | Type | Reset Value | Description
MIO_PIN_77 | 0XFF180134 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_PIN_77_L0_SEL | 1:1 | 2 | 0 | 0 | Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_77_L1_SEL | 2:2 | 4 | 0 | 0 | Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
PSU_IOU_SLCR_MIO_PIN_77_L2_SEL | 4:3 | 18 | 0 | 0 | Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
PSU_IOU_SLCR_MIO_PIN_77_L3_SEL | 7:5 | e0 | 0 | 0 | Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_out- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used
PSU_IOU_SLCR_MIO_PIN_77@0XFF180134 | 31:0 | fe |  | 0 | Configures MIO Pin 77 peripheral interface mapping

## Register ( slcr )MIO_MST_TRI0

Register Name | Address | Width | Type | Reset Value | Description
MIO_MST_TRI0 | 0XFF180204 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI | 0:0 | 1 | 0 | 0 | Master Tri-state Enable for pin 0, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI | 1:1 | 2 | 0 | 0 | Master Tri-state Enable for pin 1, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI | 2:2 | 4 | 0 | 0 | Master Tri-state Enable for pin 2, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI | 3:3 | 8 | 0 | 0 | Master Tri-state Enable for pin 3, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI | 4:4 | 10 | 0 | 0 | Master Tri-state Enable for pin 4, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI | 5:5 | 20 | 0 | 0 | Master Tri-state Enable for pin 5, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI | 6:6 | 40 | 0 | 0 | Master Tri-state Enable for pin 6, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI | 7:7 | 80 | 0 | 0 | Master Tri-state Enable for pin 7, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI | 8:8 | 100 | 0 | 0 | Master Tri-state Enable for pin 8, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI | 9:9 | 200 | 0 | 0 | Master Tri-state Enable for pin 9, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI | 10:10 | 400 | 1 | 400 | Master Tri-state Enable for pin 10, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI | 11:11 | 800 | 1 | 800 | Master Tri-state Enable for pin 11, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI | 12:12 | 1000 | 0 | 0 | Master Tri-state Enable for pin 12, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI | 13:13 | 2000 | 0 | 0 | Master Tri-state Enable for pin 13, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI | 14:14 | 4000 | 0 | 0 | Master Tri-state Enable for pin 14, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI | 15:15 | 8000 | 0 | 0 | Master Tri-state Enable for pin 15, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI | 16:16 | 10000 | 0 | 0 | Master Tri-state Enable for pin 16, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI | 17:17 | 20000 | 0 | 0 | Master Tri-state Enable for pin 17, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI | 18:18 | 40000 | 0 | 0 | Master Tri-state Enable for pin 18, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI | 19:19 | 80000 | 0 | 0 | Master Tri-state Enable for pin 19, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI | 20:20 | 100000 | 0 | 0 | Master Tri-state Enable for pin 20, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI | 21:21 | 200000 | 0 | 0 | Master Tri-state Enable for pin 21, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI | 22:22 | 400000 | 0 | 0 | Master Tri-state Enable for pin 22, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI | 23:23 | 800000 | 0 | 0 | Master Tri-state Enable for pin 23, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI | 24:24 | 1000000 | 0 | 0 | Master Tri-state Enable for pin 24, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI | 25:25 | 2000000 | 0 | 0 | Master Tri-state Enable for pin 25, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI | 26:26 | 4000000 | 0 | 0 | Master Tri-state Enable for pin 26, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI | 27:27 | 8000000 | 0 | 0 | Master Tri-state Enable for pin 27, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI | 28:28 | 10000000 | 0 | 0 | Master Tri-state Enable for pin 28, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI | 29:29 | 20000000 | 0 | 0 | Master Tri-state Enable for pin 29, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI | 30:30 | 40000000 | 0 | 0 | Master Tri-state Enable for pin 30, active high
PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI | 31:31 | 80000000 | 0 | 0 | Master Tri-state Enable for pin 31, active high
PSU_IOU_SLCR_MIO_MST_TRI0@0XFF180204 | 31:0 | ffffffff |  | c00 | MIO pin Tri-state Enables, 31:0

## Register ( slcr )MIO_MST_TRI1

Register Name | Address | Width | Type | Reset Value | Description
MIO_MST_TRI1 | 0XFF180208 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI | 0:0 | 1 | 0 | 0 | Master Tri-state Enable for pin 32, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI | 1:1 | 2 | 0 | 0 | Master Tri-state Enable for pin 33, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI | 2:2 | 4 | 0 | 0 | Master Tri-state Enable for pin 34, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI | 3:3 | 8 | 0 | 0 | Master Tri-state Enable for pin 35, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI | 4:4 | 10 | 0 | 0 | Master Tri-state Enable for pin 36, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI | 5:5 | 20 | 0 | 0 | Master Tri-state Enable for pin 37, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI | 6:6 | 40 | 0 | 0 | Master Tri-state Enable for pin 38, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI | 7:7 | 80 | 0 | 0 | Master Tri-state Enable for pin 39, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI | 8:8 | 100 | 0 | 0 | Master Tri-state Enable for pin 40, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI | 9:9 | 200 | 0 | 0 | Master Tri-state Enable for pin 41, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI | 10:10 | 400 | 0 | 0 | Master Tri-state Enable for pin 42, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI | 11:11 | 800 | 0 | 0 | Master Tri-state Enable for pin 43, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI | 12:12 | 1000 | 0 | 0 | Master Tri-state Enable for pin 44, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI | 13:13 | 2000 | 0 | 0 | Master Tri-state Enable for pin 45, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI | 14:14 | 4000 | 0 | 0 | Master Tri-state Enable for pin 46, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI | 15:15 | 8000 | 0 | 0 | Master Tri-state Enable for pin 47, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI | 16:16 | 10000 | 0 | 0 | Master Tri-state Enable for pin 48, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI | 17:17 | 20000 | 0 | 0 | Master Tri-state Enable for pin 49, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI | 18:18 | 40000 | 0 | 0 | Master Tri-state Enable for pin 50, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI | 19:19 | 80000 | 0 | 0 | Master Tri-state Enable for pin 51, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI | 20:20 | 100000 | 1 | 100000 | Master Tri-state Enable for pin 52, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI | 21:21 | 200000 | 1 | 200000 | Master Tri-state Enable for pin 53, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI | 22:22 | 400000 | 0 | 0 | Master Tri-state Enable for pin 54, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI | 23:23 | 800000 | 1 | 800000 | Master Tri-state Enable for pin 55, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI | 24:24 | 1000000 | 0 | 0 | Master Tri-state Enable for pin 56, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI | 25:25 | 2000000 | 0 | 0 | Master Tri-state Enable for pin 57, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI | 26:26 | 4000000 | 0 | 0 | Master Tri-state Enable for pin 58, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI | 27:27 | 8000000 | 0 | 0 | Master Tri-state Enable for pin 59, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI | 28:28 | 10000000 | 0 | 0 | Master Tri-state Enable for pin 60, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI | 29:29 | 20000000 | 0 | 0 | Master Tri-state Enable for pin 61, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI | 30:30 | 40000000 | 0 | 0 | Master Tri-state Enable for pin 62, active high
PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI | 31:31 | 80000000 | 0 | 0 | Master Tri-state Enable for pin 63, active high
PSU_IOU_SLCR_MIO_MST_TRI1@0XFF180208 | 31:0 | ffffffff |  | b00000 | MIO pin Tri-state Enables, 63:32

## Register ( slcr )MIO_MST_TRI2

Register Name | Address | Width | Type | Reset Value | Description
MIO_MST_TRI2 | 0XFF18020C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI | 0:0 | 1 | 0 | 0 | Master Tri-state Enable for pin 64, active high
PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI | 1:1 | 2 | 1 | 2 | Master Tri-state Enable for pin 65, active high
PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI | 2:2 | 4 | 0 | 0 | Master Tri-state Enable for pin 66, active high
PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI | 3:3 | 8 | 0 | 0 | Master Tri-state Enable for pin 67, active high
PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI | 4:4 | 10 | 0 | 0 | Master Tri-state Enable for pin 68, active high
PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI | 5:5 | 20 | 0 | 0 | Master Tri-state Enable for pin 69, active high
PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI | 6:6 | 40 | 0 | 0 | Master Tri-state Enable for pin 70, active high
PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI | 7:7 | 80 | 0 | 0 | Master Tri-state Enable for pin 71, active high
PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI | 8:8 | 100 | 0 | 0 | Master Tri-state Enable for pin 72, active high
PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI | 9:9 | 200 | 0 | 0 | Master Tri-state Enable for pin 73, active high
PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI | 10:10 | 400 | 0 | 0 | Master Tri-state Enable for pin 74, active high
PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI | 11:11 | 800 | 0 | 0 | Master Tri-state Enable for pin 75, active high
PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI | 12:12 | 1000 | 1 | 1000 | Master Tri-state Enable for pin 76, active high
PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI | 13:13 | 2000 | 0 | 0 | Master Tri-state Enable for pin 77, active high
PSU_IOU_SLCR_MIO_MST_TRI2@0XFF18020C | 31:0 | 3fff |  | 1002 | MIO pin Tri-state Enables, 77:64

# LOOPBACK

## Register ( slcr )MIO_LOOPBACK

Register Name | Address | Width | Type | Reset Value | Description
MIO_LOOPBACK | 0XFF180200 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1 | 3:3 | 8 | 0 | 0 | I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs.
PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1 | 2:2 | 4 | 0 | 0 | CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx.
PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1 | 1:1 | 2 | 0 | 0 | UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.
PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1 | 0:0 | 1 | 0 | 0 | SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.
PSU_IOU_SLCR_MIO_LOOPBACK@0XFF180200 | 31:0 | f |  | 0 | Loopback function within MIO

## psu_peripherals_init_data_3_0

Register Name | Address | Width | Type | Reset Value | Description
PSU_CRL_APB_RST_LPD_IOU0 | 0XFF5E0230 | 32 | RW | 0x000000 | Software controlled reset for the GEMs
PSU_CRL_APB_RST_LPD_IOU2 | 0XFF5E0238 | 32 | RW | 0x000000 | Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
PSU_CRL_APB_RST_LPD_IOU2 | 0XFF5E0238 | 32 | RW | 0x000000 | Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
PSU_CRL_APB_RST_LPD_TOP | 0XFF5E023C | 32 | RW | 0x000000 | Software control register for the LPD block.
PSU_CRL_APB_RST_LPD_IOU2 | 0XFF5E0238 | 32 | RW | 0x000000 | Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
PSU_IOU_SLCR_CTRL_REG_SD | 0XFF180310 | 32 | RW | 0x000000 | SD eMMC selection
PSU_IOU_SLCR_SD_CONFIG_REG2 | 0XFF180320 | 32 | RW | 0x000000 | SD Config Register 2
PSU_CRL_APB_RST_LPD_IOU2 | 0XFF5E0238 | 32 | RW | 0x000000 | Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
PSU_CRL_APB_RST_LPD_IOU2 | 0XFF5E0238 | 32 | RW | 0x000000 | Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
PSU_CRL_APB_RST_LPD_IOU2 | 0XFF5E0238 | 32 | RW | 0x000000 | Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
PSU_CRL_APB_RST_LPD_IOU2 | 0XFF5E0238 | 32 | RW | 0x000000 | Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
PSU_CRL_APB_RST_LPD_IOU2 | 0XFF5E0238 | 32 | RW | 0x000000 | Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
PSU_UART0_BAUD_RATE_DIVIDER_REG0 | 0XFF000034 | 32 | RW | 0x000000 | Baud Rate Divider Register
PSU_UART0_BAUD_RATE_GEN_REG0 | 0XFF000018 | 32 | RW | 0x000000 | Baud Rate Generator Register.
PSU_UART0_CONTROL_REG0 | 0XFF000000 | 32 | RW | 0x000000 | UART Control Register
PSU_UART0_MODE_REG0 | 0XFF000004 | 32 | RW | 0x000000 | UART Mode Register
PSU_UART1_BAUD_RATE_DIVIDER_REG0 | 0XFF010034 | 32 | RW | 0x000000 | Baud Rate Divider Register
PSU_UART1_BAUD_RATE_GEN_REG0 | 0XFF010018 | 32 | RW | 0x000000 | Baud Rate Generator Register.
PSU_UART1_CONTROL_REG0 | 0XFF010000 | 32 | RW | 0x000000 | UART Control Register
PSU_UART1_MODE_REG0 | 0XFF010004 | 32 | RW | 0x000000 | UART Mode Register
PSU_LPD_SLCR_SECURE_SLCR_ADMA | 0XFF4B0024 | 32 | RW | 0x000000 | RPU TrustZone settings
PSU_CSU_TAMPER_STATUS | 0XFFCA5000 | 32 | RW | 0x000000 | Tamper Response Status

## psu_peripherals_init_data_3_0

Register Name | Address | Width | Type | Reset Value | Description

# ENET

## Register ( slcr )RST_LPD_IOU0

Register Name | Address | Width | Type | Reset Value | Description
RST_LPD_IOU0 | 0XFF5E0230 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_RST_LPD_IOU0_GEM0_RESET | 0:0 | 1 | 0 | 0 | GEM 0 reset
PSU_CRL_APB_RST_LPD_IOU0_GEM1_RESET | 1:1 | 2 | 0 | 0 | GEM 1 reset
PSU_CRL_APB_RST_LPD_IOU0_GEM2_RESET | 2:2 | 4 | 0 | 0 | GEM 2 reset
PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET | 3:3 | 8 | 0 | 0 | GEM 3 reset
PSU_CRL_APB_RST_LPD_IOU0@0XFF5E0230 | 31:0 | f |  | 0 | Software controlled reset for the GEMs

# QSPI

## Register ( slcr )RST_LPD_IOU2

Register Name | Address | Width | Type | Reset Value | Description
RST_LPD_IOU2 | 0XFF5E0238 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET | 0:0 | 1 | 0 | 0 | Block level reset
PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238 | 31:0 | 1 |  | 0 | Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.

# NAND

## Register ( slcr )RST_LPD_IOU2

Register Name | Address | Width | Type | Reset Value | Description
RST_LPD_IOU2 | 0XFF5E0238 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_RST_LPD_IOU2_NAND_RESET | 16:16 | 10000 | 0 | 0 | Block level reset
PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238 | 31:0 | 10000 |  | 0 | Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.

# USB

## Register ( slcr )RST_LPD_TOP

Register Name | Address | Width | Type | Reset Value | Description
RST_LPD_TOP | 0XFF5E023C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET | 10:10 | 400 | 0 | 0 | USB 0 reset for control registers
PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET | 8:8 | 100 | 0 | 0 | USB 0 sleep circuit reset
PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET | 6:6 | 40 | 0 | 0 | USB 0 reset
PSU_CRL_APB_RST_LPD_TOP@0XFF5E023C | 31:0 | 540 |  | 0 | Software control register for the LPD block.

# SD

## Register ( slcr )RST_LPD_IOU2

Register Name | Address | Width | Type | Reset Value | Description
RST_LPD_IOU2 | 0XFF5E0238 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_RST_LPD_IOU2_SDIO0_RESET | 5:5 | 20 | 0 | 0 | Block level reset
PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET | 6:6 | 40 | 0 | 0 | Block level reset
PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238 | 31:0 | 60 |  | 0 | Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.

## Register ( slcr )CTRL_REG_SD

Register Name | Address | Width | Type | Reset Value | Description
CTRL_REG_SD | 0XFF180310 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_CTRL_REG_SD_SD0_EMMC_SEL | 0:0 | 1 | 0 | 0 | SD or eMMC selection on SDIO0 0: SD enabled 1: eMMC enabled
PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL | 15:15 | 8000 | 0 | 0 | SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled
PSU_IOU_SLCR_CTRL_REG_SD@0XFF180310 | 31:0 | 8001 |  | 0 | SD eMMC selection

## Register ( slcr )SD_CONFIG_REG2

Register Name | Address | Width | Type | Reset Value | Description
SD_CONFIG_REG2 | 0XFF180320 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_SLOTTYPE | 13:12 | 3000 | 0 | 0 | Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved
PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE | 29:28 | 30000000 | 0 | 0 | Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved
PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_1P8V | 9:9 | 200 | 1 | 200 | 1.8V Support 1: 1.8V supported 0: 1.8V not supported support
PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_3P0V | 8:8 | 100 | 0 | 0 | 3.0V Support 1: 3.0V supported 0: 3.0V not supported support
PSU_IOU_SLCR_SD_CONFIG_REG2_SD0_3P3V | 7:7 | 80 | 1 | 80 | 3.3V Support 1: 3.3V supported 0: 3.3V not supported support
PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V | 25:25 | 2000000 | 1 | 2000000 | 1.8V Support 1: 1.8V supported 0: 1.8V not supported support
PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V | 24:24 | 1000000 | 0 | 0 | 3.0V Support 1: 3.0V supported 0: 3.0V not supported support
PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V | 23:23 | 800000 | 1 | 800000 | 3.3V Support 1: 3.3V supported 0: 3.3V not supported support
PSU_IOU_SLCR_SD_CONFIG_REG2@0XFF180320 | 31:0 | 33803380 |  | 2800280 | SD Config Register 2

# CAN

## Register ( slcr )RST_LPD_IOU2

Register Name | Address | Width | Type | Reset Value | Description
RST_LPD_IOU2 | 0XFF5E0238 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_RST_LPD_IOU2_CAN0_RESET | 7:7 | 80 | 0 | 0 | Block level reset
PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET | 8:8 | 100 | 0 | 0 | Block level reset
PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238 | 31:0 | 180 |  | 0 | Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.

# I2C

## Register ( slcr )RST_LPD_IOU2

Register Name | Address | Width | Type | Reset Value | Description
RST_LPD_IOU2 | 0XFF5E0238 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET | 9:9 | 200 | 0 | 0 | Block level reset
PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET | 10:10 | 400 | 0 | 0 | Block level reset
PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238 | 31:0 | 600 |  | 0 | Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.

# SWDT

# SPI

## Register ( slcr )RST_LPD_IOU2

Register Name | Address | Width | Type | Reset Value | Description
RST_LPD_IOU2 | 0XFF5E0238 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_RST_LPD_IOU2_SPI0_RESET | 3:3 | 8 | 0 | 0 | Block level reset
PSU_CRL_APB_RST_LPD_IOU2_SPI1_RESET | 4:4 | 10 | 0 | 0 | Block level reset
PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238 | 31:0 | 18 |  | 0 | Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.

# TTC

## Register ( slcr )RST_LPD_IOU2

Register Name | Address | Width | Type | Reset Value | Description
RST_LPD_IOU2 | 0XFF5E0238 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET | 11:11 | 800 | 0 | 0 | Block level reset
PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET | 12:12 | 1000 | 0 | 0 | Block level reset
PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET | 13:13 | 2000 | 0 | 0 | Block level reset
PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET | 14:14 | 4000 | 0 | 0 | Block level reset
PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238 | 31:0 | 7800 |  | 0 | Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.

# UART

## Register ( slcr )RST_LPD_IOU2

Register Name | Address | Width | Type | Reset Value | Description
RST_LPD_IOU2 | 0XFF5E0238 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET | 1:1 | 2 | 0 | 0 | Block level reset
PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET | 2:2 | 4 | 0 | 0 | Block level reset
PSU_CRL_APB_RST_LPD_IOU2@0XFF5E0238 | 31:0 | 6 |  | 0 | Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.

## Register ( slcr )Baud_rate_divider_reg0

Register Name | Address | Width | Type | Reset Value | Description
Baud_rate_divider_reg0 | 0XFF000034 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV | 7:0 | ff | 0 | 0 | Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
PSU_UART0_BAUD_RATE_DIVIDER_REG0@0XFF000034 | 31:0 | ff |  | 0 | Baud Rate Divider Register

## Register ( slcr )Baud_rate_gen_reg0

Register Name | Address | Width | Type | Reset Value | Description
Baud_rate_gen_reg0 | 0XFF000018 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_UART0_BAUD_RATE_GEN_REG0_CD | 15:0 | ffff | 0 | 0 | Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
PSU_UART0_BAUD_RATE_GEN_REG0@0XFF000018 | 31:0 | ffff |  | 0 | Baud Rate Generator Register.

## Register ( slcr )Control_reg0

Register Name | Address | Width | Type | Reset Value | Description
Control_reg0 | 0XFF000000 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_UART0_CONTROL_REG0_STPBRK | 8:8 | 100 | 0 | 0 | Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK.
PSU_UART0_CONTROL_REG0_STTBRK | 7:7 | 80 | 0 | 0 | Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
PSU_UART0_CONTROL_REG0_RSTTO | 6:6 | 40 | 0 | 0 | Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed.
PSU_UART0_CONTROL_REG0_TXDIS | 5:5 | 20 | 0 | 0 | Transmit disable: 0: enable transmitter 1: disable transmitter
PSU_UART0_CONTROL_REG0_TXEN | 4:4 | 10 | 1 | 10 | Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
PSU_UART0_CONTROL_REG0_RXDIS | 3:3 | 8 | 0 | 0 | Receive disable: 0: enable 1: disable, regardless of the value of RXEN
PSU_UART0_CONTROL_REG0_RXEN | 2:2 | 4 | 1 | 4 | Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
PSU_UART0_CONTROL_REG0_TXRES | 1:1 | 2 | 1 | 2 | Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed.
PSU_UART0_CONTROL_REG0_RXRES | 0:0 | 1 | 1 | 1 | Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed.
PSU_UART0_CONTROL_REG0@0XFF000000 | 31:0 | 1ff |  | 17 | UART Control Register

## Register ( slcr )mode_reg0

Register Name | Address | Width | Type | Reset Value | Description
mode_reg0 | 0XFF000004 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_UART0_MODE_REG0_CHMODE | 9:8 | 300 | 0 | 0 | Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
PSU_UART0_MODE_REG0_NBSTOP | 7:6 | c0 | 0 | 0 | Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved
PSU_UART0_MODE_REG0_PAR | 5:3 | 38 | 4 | 20 | Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
PSU_UART0_MODE_REG0_CHRL | 2:1 | 6 | 0 | 0 | Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
PSU_UART0_MODE_REG0_CLKS | 0:0 | 1 | 0 | 0 | Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8
PSU_UART0_MODE_REG0@0XFF000004 | 31:0 | 3ff |  | 20 | UART Mode Register

## Register ( slcr )Baud_rate_divider_reg0

Register Name | Address | Width | Type | Reset Value | Description
Baud_rate_divider_reg0 | 0XFF010034 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV | 7:0 | ff | 0 | 0 | Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
PSU_UART1_BAUD_RATE_DIVIDER_REG0@0XFF010034 | 31:0 | ff |  | 0 | Baud Rate Divider Register

## Register ( slcr )Baud_rate_gen_reg0

Register Name | Address | Width | Type | Reset Value | Description
Baud_rate_gen_reg0 | 0XFF010018 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_UART1_BAUD_RATE_GEN_REG0_CD | 15:0 | ffff | 0 | 0 | Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
PSU_UART1_BAUD_RATE_GEN_REG0@0XFF010018 | 31:0 | ffff |  | 0 | Baud Rate Generator Register.

## Register ( slcr )Control_reg0

Register Name | Address | Width | Type | Reset Value | Description
Control_reg0 | 0XFF010000 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_UART1_CONTROL_REG0_STPBRK | 8:8 | 100 | 0 | 0 | Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK.
PSU_UART1_CONTROL_REG0_STTBRK | 7:7 | 80 | 0 | 0 | Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
PSU_UART1_CONTROL_REG0_RSTTO | 6:6 | 40 | 0 | 0 | Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed.
PSU_UART1_CONTROL_REG0_TXDIS | 5:5 | 20 | 0 | 0 | Transmit disable: 0: enable transmitter 1: disable transmitter
PSU_UART1_CONTROL_REG0_TXEN | 4:4 | 10 | 1 | 10 | Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
PSU_UART1_CONTROL_REG0_RXDIS | 3:3 | 8 | 0 | 0 | Receive disable: 0: enable 1: disable, regardless of the value of RXEN
PSU_UART1_CONTROL_REG0_RXEN | 2:2 | 4 | 1 | 4 | Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
PSU_UART1_CONTROL_REG0_TXRES | 1:1 | 2 | 1 | 2 | Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed.
PSU_UART1_CONTROL_REG0_RXRES | 0:0 | 1 | 1 | 1 | Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed.
PSU_UART1_CONTROL_REG0@0XFF010000 | 31:0 | 1ff |  | 17 | UART Control Register

## Register ( slcr )mode_reg0

Register Name | Address | Width | Type | Reset Value | Description
mode_reg0 | 0XFF010004 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_UART1_MODE_REG0_CHMODE | 9:8 | 300 | 0 | 0 | Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
PSU_UART1_MODE_REG0_NBSTOP | 7:6 | c0 | 0 | 0 | Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved
PSU_UART1_MODE_REG0_PAR | 5:3 | 38 | 4 | 20 | Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
PSU_UART1_MODE_REG0_CHRL | 2:1 | 6 | 0 | 0 | Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
PSU_UART1_MODE_REG0_CLKS | 0:0 | 1 | 0 | 0 | Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8
PSU_UART1_MODE_REG0@0XFF010004 | 31:0 | 3ff |  | 20 | UART Mode Register

# GPIO

# ADMA TZ

## Register ( slcr )slcr_adma

Register Name | Address | Width | Type | Reset Value | Description
slcr_adma | 0XFF4B0024 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ | 7:0 | ff | ff | ff | TrustZone Classification for ADMA
PSU_LPD_SLCR_SECURE_SLCR_ADMA@0XFF4B0024 | 31:0 | ff |  | ff | RPU TrustZone settings

# CSU TAMPERING

# CSU TAMPER STATUS

## Register ( slcr )tamper_status

Register Name | Address | Width | Type | Reset Value | Description
tamper_status | 0XFFCA5000 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_CSU_TAMPER_STATUS_TAMPER_0 | 0:0 | 1 | 0 | 0 | CSU regsiter
PSU_CSU_TAMPER_STATUS_TAMPER_1 | 1:1 | 2 | 0 | 0 | External MIO
PSU_CSU_TAMPER_STATUS_TAMPER_2 | 2:2 | 4 | 0 | 0 | JTAG toggle detect
PSU_CSU_TAMPER_STATUS_TAMPER_3 | 3:3 | 8 | 0 | 0 | PL SEU error
PSU_CSU_TAMPER_STATUS_TAMPER_4 | 4:4 | 10 | 0 | 0 | AMS over temperature alarm for LPD
PSU_CSU_TAMPER_STATUS_TAMPER_5 | 5:5 | 20 | 0 | 0 | AMS over temperature alarm for APU
PSU_CSU_TAMPER_STATUS_TAMPER_6 | 6:6 | 40 | 0 | 0 | AMS voltage alarm for VCCPINT_FPD
PSU_CSU_TAMPER_STATUS_TAMPER_7 | 7:7 | 80 | 0 | 0 | AMS voltage alarm for VCCPINT_LPD
PSU_CSU_TAMPER_STATUS_TAMPER_8 | 8:8 | 100 | 0 | 0 | AMS voltage alarm for VCCPAUX
PSU_CSU_TAMPER_STATUS_TAMPER_9 | 9:9 | 200 | 0 | 0 | AMS voltage alarm for DDRPHY
PSU_CSU_TAMPER_STATUS_TAMPER_10 | 10:10 | 400 | 0 | 0 | AMS voltage alarm for PSIO bank 0/1/2
PSU_CSU_TAMPER_STATUS_TAMPER_11 | 11:11 | 800 | 0 | 0 | AMS voltage alarm for PSIO bank 3 (dedicated pins)
PSU_CSU_TAMPER_STATUS_TAMPER_12 | 12:12 | 1000 | 0 | 0 | AMS voltaage alarm for GT
PSU_CSU_TAMPER_STATUS@0XFFCA5000 | 31:0 | 1fff |  | 0 | Tamper Response Status

# CSU TAMPER RESPONSE

## psu_post_config

Register Name | Address | Width | Type | Reset Value | Description

## psu_post_config

Register Name | Address | Width | Type | Reset Value | Description

## psu_peripherals_powerdwn_data_3_0

Register Name | Address | Width | Type | Reset Value | Description

## psu_peripherals_powerdwn_data_3_0

Register Name | Address | Width | Type | Reset Value | Description

# POWER DOWN REQUEST INTERRUPT ENABLE

# POWER DOWN TRIGGER

## psu_security_data_3_0

Register Name | Address | Width | Type | Reset Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID00 | 0XFF980100 | 32 | RW | 0x000000 | Master ID 00 Register
PSU_LPD_XPPU_CFG_MASTER_ID01 | 0XFF980104 | 32 | RW | 0x000000 | Master ID 01 Register
PSU_LPD_XPPU_CFG_MASTER_ID02 | 0XFF980108 | 32 | RW | 0x000000 | Master ID 02 Register
PSU_LPD_XPPU_CFG_MASTER_ID03 | 0XFF98010C | 32 | RW | 0x000000 | Master ID 03 Register
PSU_LPD_XPPU_CFG_MASTER_ID04 | 0XFF980110 | 32 | RW | 0x000000 | Master ID 04 Register
PSU_LPD_XPPU_CFG_MASTER_ID05 | 0XFF980114 | 32 | RW | 0x000000 | Master ID 05 Register
PSU_LPD_XPPU_CFG_MASTER_ID06 | 0XFF980118 | 32 | RW | 0x000000 | Master ID 06 Register
PSU_LPD_XPPU_CFG_MASTER_ID07 | 0XFF98011C | 32 | RW | 0x000000 | Master ID 07 Register
PSU_LPD_XPPU_CFG_MASTER_ID08 | 0XFF980120 | 32 | RW | 0x000000 | Master ID 08 Register
PSU_LPD_XPPU_CFG_MASTER_ID09 | 0XFF980124 | 32 | RW | 0x000000 | Master ID 09 Register
PSU_LPD_XPPU_CFG_MASTER_ID10 | 0XFF980128 | 32 | RW | 0x000000 | Master ID 10 Register
PSU_LPD_XPPU_CFG_MASTER_ID11 | 0XFF98012C | 32 | RW | 0x000000 | Master ID 11 Register
PSU_LPD_XPPU_CFG_MASTER_ID12 | 0XFF980130 | 32 | RW | 0x000000 | Master ID 12 Register
PSU_LPD_XPPU_CFG_MASTER_ID13 | 0XFF980134 | 32 | RW | 0x000000 | Master ID 13 Register
PSU_LPD_XPPU_CFG_MASTER_ID14 | 0XFF980138 | 32 | RW | 0x000000 | Master ID 14 Register
PSU_LPD_XPPU_CFG_MASTER_ID15 | 0XFF98013C | 32 | RW | 0x000000 | Master ID 15 Register
PSU_LPD_XPPU_CFG_MASTER_ID16 | 0XFF980140 | 32 | RW | 0x000000 | Master ID 16 Register
PSU_LPD_XPPU_CFG_MASTER_ID17 | 0XFF980144 | 32 | RW | 0x000000 | Master ID 17 Register
PSU_LPD_XPPU_CFG_MASTER_ID18 | 0XFF980148 | 32 | RW | 0x000000 | Master ID 18 Register
PSU_LPD_XPPU_CFG_MASTER_ID19 | 0XFF98014C | 32 | RW | 0x000000 | Master ID 19 Register

## psu_security_data_3_0

Register Name | Address | Width | Type | Reset Value | Description

# DDR XMPU0

# DDR XMPU1

# DDR XMPU2

# DDR XMPU3

# DDR XMPU4

# DDR XMPU5

# FPD XMPU

# OCM XMPU

# XPPU

# MASTER ID LIST

## Register ( slcr )MASTER_ID00

Register Name | Address | Width | Type | Reset Value | Description
MASTER_ID00 | 0XFF980100 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID00_MIDP | 31:31 | 80000000 | 0 | 0 | Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
PSU_LPD_XPPU_CFG_MASTER_ID00_MIDR | 30:30 | 40000000 | 0 | 0 | If set, only read transactions are allowed for the masters matching this register
PSU_LPD_XPPU_CFG_MASTER_ID00_MIDM | 25:16 | 3ff0000 | 0 | 0 | Mask to be applied before comparing
PSU_LPD_XPPU_CFG_MASTER_ID00_MID | 9:0 | 3ff | 0 | 0 | Predefined Master ID for PMU
PSU_LPD_XPPU_CFG_MASTER_ID00@0XFF980100 | 31:0 | c3ff03ff |  | 0 | Master ID 00 Register

## Register ( slcr )MASTER_ID01

Register Name | Address | Width | Type | Reset Value | Description
MASTER_ID01 | 0XFF980104 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID01_MIDP | 31:31 | 80000000 | 0 | 0 | Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
PSU_LPD_XPPU_CFG_MASTER_ID01_MIDR | 30:30 | 40000000 | 0 | 0 | If set, only read transactions are allowed for the masters matching this register
PSU_LPD_XPPU_CFG_MASTER_ID01_MIDM | 25:16 | 3ff0000 | 0 | 0 | Mask to be applied before comparing
PSU_LPD_XPPU_CFG_MASTER_ID01_MID | 9:0 | 3ff | 0 | 0 | Predefined Master ID for RPU0
PSU_LPD_XPPU_CFG_MASTER_ID01@0XFF980104 | 31:0 | c3ff03ff |  | 0 | Master ID 01 Register

## Register ( slcr )MASTER_ID02

Register Name | Address | Width | Type | Reset Value | Description
MASTER_ID02 | 0XFF980108 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID02_MIDP | 31:31 | 80000000 | 0 | 0 | Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
PSU_LPD_XPPU_CFG_MASTER_ID02_MIDR | 30:30 | 40000000 | 0 | 0 | If set, only read transactions are allowed for the masters matching this register
PSU_LPD_XPPU_CFG_MASTER_ID02_MIDM | 25:16 | 3ff0000 | 0 | 0 | Mask to be applied before comparing
PSU_LPD_XPPU_CFG_MASTER_ID02_MID | 9:0 | 3ff | 0 | 0 | Predefined Master ID for RPU1
PSU_LPD_XPPU_CFG_MASTER_ID02@0XFF980108 | 31:0 | c3ff03ff |  | 0 | Master ID 02 Register

## Register ( slcr )MASTER_ID03

Register Name | Address | Width | Type | Reset Value | Description
MASTER_ID03 | 0XFF98010C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID03_MIDP | 31:31 | 80000000 | 0 | 0 | Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
PSU_LPD_XPPU_CFG_MASTER_ID03_MIDR | 30:30 | 40000000 | 0 | 0 | If set, only read transactions are allowed for the masters matching this register
PSU_LPD_XPPU_CFG_MASTER_ID03_MIDM | 25:16 | 3ff0000 | 0 | 0 | Mask to be applied before comparing
PSU_LPD_XPPU_CFG_MASTER_ID03_MID | 9:0 | 3ff | 0 | 0 | Predefined Master ID for APU
PSU_LPD_XPPU_CFG_MASTER_ID03@0XFF98010C | 31:0 | c3ff03ff |  | 0 | Master ID 03 Register

## Register ( slcr )MASTER_ID04

Register Name | Address | Width | Type | Reset Value | Description
MASTER_ID04 | 0XFF980110 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID04_MIDP | 31:31 | 80000000 | 0 | 0 | Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
PSU_LPD_XPPU_CFG_MASTER_ID04_MIDR | 30:30 | 40000000 | 0 | 0 | If set, only read transactions are allowed for the masters matching this register
PSU_LPD_XPPU_CFG_MASTER_ID04_MIDM | 25:16 | 3ff0000 | 0 | 0 | Mask to be applied before comparing
PSU_LPD_XPPU_CFG_MASTER_ID04_MID | 9:0 | 3ff | 0 | 0 | Predefined Master ID for A53 Core 0
PSU_LPD_XPPU_CFG_MASTER_ID04@0XFF980110 | 31:0 | c3ff03ff |  | 0 | Master ID 04 Register

## Register ( slcr )MASTER_ID05

Register Name | Address | Width | Type | Reset Value | Description
MASTER_ID05 | 0XFF980114 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID05_MIDP | 31:31 | 80000000 | 0 | 0 | Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
PSU_LPD_XPPU_CFG_MASTER_ID05_MIDR | 30:30 | 40000000 | 0 | 0 | If set, only read transactions are allowed for the masters matching this register
PSU_LPD_XPPU_CFG_MASTER_ID05_MIDM | 25:16 | 3ff0000 | 0 | 0 | Mask to be applied before comparing
PSU_LPD_XPPU_CFG_MASTER_ID05_MID | 9:0 | 3ff | 0 | 0 | Predefined Master ID for A53 Core 1
PSU_LPD_XPPU_CFG_MASTER_ID05@0XFF980114 | 31:0 | c3ff03ff |  | 0 | Master ID 05 Register

## Register ( slcr )MASTER_ID06

Register Name | Address | Width | Type | Reset Value | Description
MASTER_ID06 | 0XFF980118 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID06_MIDP | 31:31 | 80000000 | 0 | 0 | Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
PSU_LPD_XPPU_CFG_MASTER_ID06_MIDR | 30:30 | 40000000 | 0 | 0 | If set, only read transactions are allowed for the masters matching this register
PSU_LPD_XPPU_CFG_MASTER_ID06_MIDM | 25:16 | 3ff0000 | 0 | 0 | Mask to be applied before comparing
PSU_LPD_XPPU_CFG_MASTER_ID06_MID | 9:0 | 3ff | 0 | 0 | Predefined Master ID for A53 Core 2
PSU_LPD_XPPU_CFG_MASTER_ID06@0XFF980118 | 31:0 | c3ff03ff |  | 0 | Master ID 06 Register

## Register ( slcr )MASTER_ID07

Register Name | Address | Width | Type | Reset Value | Description
MASTER_ID07 | 0XFF98011C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID07_MIDP | 31:31 | 80000000 | 0 | 0 | Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
PSU_LPD_XPPU_CFG_MASTER_ID07_MIDR | 30:30 | 40000000 | 0 | 0 | If set, only read transactions are allowed for the masters matching this register
PSU_LPD_XPPU_CFG_MASTER_ID07_MIDM | 25:16 | 3ff0000 | 0 | 0 | Mask to be applied before comparing
PSU_LPD_XPPU_CFG_MASTER_ID07_MID | 9:0 | 3ff | 0 | 0 | Predefined Master ID for A53 Core 3
PSU_LPD_XPPU_CFG_MASTER_ID07@0XFF98011C | 31:0 | c3ff03ff |  | 0 | Master ID 07 Register

## Register ( slcr )MASTER_ID08

Register Name | Address | Width | Type | Reset Value | Description
MASTER_ID08 | 0XFF980120 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID08_MIDP | 31:31 | 80000000 | 0 | 0 | Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
PSU_LPD_XPPU_CFG_MASTER_ID08_MIDR | 30:30 | 40000000 | 0 | 0 | If set, only read transactions are allowed for the masters matching this register
PSU_LPD_XPPU_CFG_MASTER_ID08_MIDM | 25:16 | 3ff0000 | 0 | 0 | Mask to be applied before comparing
PSU_LPD_XPPU_CFG_MASTER_ID08_MID | 9:0 | 3ff | 0 | 0 | Programmable Master ID
PSU_LPD_XPPU_CFG_MASTER_ID08@0XFF980120 | 31:0 | c3ff03ff |  | 0 | Master ID 08 Register

## Register ( slcr )MASTER_ID09

Register Name | Address | Width | Type | Reset Value | Description
MASTER_ID09 | 0XFF980124 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID09_MIDP | 31:31 | 80000000 | 0 | 0 | Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
PSU_LPD_XPPU_CFG_MASTER_ID09_MIDR | 30:30 | 40000000 | 0 | 0 | If set, only read transactions are allowed for the masters matching this register
PSU_LPD_XPPU_CFG_MASTER_ID09_MIDM | 25:16 | 3ff0000 | 0 | 0 | Mask to be applied before comparing
PSU_LPD_XPPU_CFG_MASTER_ID09_MID | 9:0 | 3ff | 0 | 0 | Programmable Master ID
PSU_LPD_XPPU_CFG_MASTER_ID09@0XFF980124 | 31:0 | c3ff03ff |  | 0 | Master ID 09 Register

## Register ( slcr )MASTER_ID10

Register Name | Address | Width | Type | Reset Value | Description
MASTER_ID10 | 0XFF980128 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID10_MIDP | 31:31 | 80000000 | 0 | 0 | Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
PSU_LPD_XPPU_CFG_MASTER_ID10_MIDR | 30:30 | 40000000 | 0 | 0 | If set, only read transactions are allowed for the masters matching this register
PSU_LPD_XPPU_CFG_MASTER_ID10_MIDM | 25:16 | 3ff0000 | 0 | 0 | Mask to be applied before comparing
PSU_LPD_XPPU_CFG_MASTER_ID10_MID | 9:0 | 3ff | 0 | 0 | Programmable Master ID
PSU_LPD_XPPU_CFG_MASTER_ID10@0XFF980128 | 31:0 | c3ff03ff |  | 0 | Master ID 10 Register

## Register ( slcr )MASTER_ID11

Register Name | Address | Width | Type | Reset Value | Description
MASTER_ID11 | 0XFF98012C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID11_MIDP | 31:31 | 80000000 | 0 | 0 | Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
PSU_LPD_XPPU_CFG_MASTER_ID11_MIDR | 30:30 | 40000000 | 0 | 0 | If set, only read transactions are allowed for the masters matching this register
PSU_LPD_XPPU_CFG_MASTER_ID11_MIDM | 25:16 | 3ff0000 | 0 | 0 | Mask to be applied before comparing
PSU_LPD_XPPU_CFG_MASTER_ID11_MID | 9:0 | 3ff | 0 | 0 | Programmable Master ID
PSU_LPD_XPPU_CFG_MASTER_ID11@0XFF98012C | 31:0 | c3ff03ff |  | 0 | Master ID 11 Register

## Register ( slcr )MASTER_ID12

Register Name | Address | Width | Type | Reset Value | Description
MASTER_ID12 | 0XFF980130 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID12_MIDP | 31:31 | 80000000 | 0 | 0 | Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
PSU_LPD_XPPU_CFG_MASTER_ID12_MIDR | 30:30 | 40000000 | 0 | 0 | If set, only read transactions are allowed for the masters matching this register
PSU_LPD_XPPU_CFG_MASTER_ID12_MIDM | 25:16 | 3ff0000 | 0 | 0 | Mask to be applied before comparing
PSU_LPD_XPPU_CFG_MASTER_ID12_MID | 9:0 | 3ff | 0 | 0 | Programmable Master ID
PSU_LPD_XPPU_CFG_MASTER_ID12@0XFF980130 | 31:0 | c3ff03ff |  | 0 | Master ID 12 Register

## Register ( slcr )MASTER_ID13

Register Name | Address | Width | Type | Reset Value | Description
MASTER_ID13 | 0XFF980134 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID13_MIDP | 31:31 | 80000000 | 0 | 0 | Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
PSU_LPD_XPPU_CFG_MASTER_ID13_MIDR | 30:30 | 40000000 | 0 | 0 | If set, only read transactions are allowed for the masters matching this register
PSU_LPD_XPPU_CFG_MASTER_ID13_MIDM | 25:16 | 3ff0000 | 0 | 0 | Mask to be applied before comparing
PSU_LPD_XPPU_CFG_MASTER_ID13_MID | 9:0 | 3ff | 0 | 0 | Programmable Master ID
PSU_LPD_XPPU_CFG_MASTER_ID13@0XFF980134 | 31:0 | c3ff03ff |  | 0 | Master ID 13 Register

## Register ( slcr )MASTER_ID14

Register Name | Address | Width | Type | Reset Value | Description
MASTER_ID14 | 0XFF980138 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID14_MIDP | 31:31 | 80000000 | 0 | 0 | Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
PSU_LPD_XPPU_CFG_MASTER_ID14_MIDR | 30:30 | 40000000 | 0 | 0 | If set, only read transactions are allowed for the masters matching this register
PSU_LPD_XPPU_CFG_MASTER_ID14_MIDM | 25:16 | 3ff0000 | 0 | 0 | Mask to be applied before comparing
PSU_LPD_XPPU_CFG_MASTER_ID14_MID | 9:0 | 3ff | 0 | 0 | Programmable Master ID
PSU_LPD_XPPU_CFG_MASTER_ID14@0XFF980138 | 31:0 | c3ff03ff |  | 0 | Master ID 14 Register

## Register ( slcr )MASTER_ID15

Register Name | Address | Width | Type | Reset Value | Description
MASTER_ID15 | 0XFF98013C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID15_MIDP | 31:31 | 80000000 | 0 | 0 | Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
PSU_LPD_XPPU_CFG_MASTER_ID15_MIDR | 30:30 | 40000000 | 0 | 0 | If set, only read transactions are allowed for the masters matching this register
PSU_LPD_XPPU_CFG_MASTER_ID15_MIDM | 25:16 | 3ff0000 | 0 | 0 | Mask to be applied before comparing
PSU_LPD_XPPU_CFG_MASTER_ID15_MID | 9:0 | 3ff | 0 | 0 | Programmable Master ID
PSU_LPD_XPPU_CFG_MASTER_ID15@0XFF98013C | 31:0 | c3ff03ff |  | 0 | Master ID 15 Register

## Register ( slcr )MASTER_ID16

Register Name | Address | Width | Type | Reset Value | Description
MASTER_ID16 | 0XFF980140 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID16_MIDP | 31:31 | 80000000 | 0 | 0 | Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
PSU_LPD_XPPU_CFG_MASTER_ID16_MIDR | 30:30 | 40000000 | 0 | 0 | If set, only read transactions are allowed for the masters matching this register
PSU_LPD_XPPU_CFG_MASTER_ID16_MIDM | 25:16 | 3ff0000 | 0 | 0 | Mask to be applied before comparing
PSU_LPD_XPPU_CFG_MASTER_ID16_MID | 9:0 | 3ff | 0 | 0 | Programmable Master ID
PSU_LPD_XPPU_CFG_MASTER_ID16@0XFF980140 | 31:0 | c3ff03ff |  | 0 | Master ID 16 Register

## Register ( slcr )MASTER_ID17

Register Name | Address | Width | Type | Reset Value | Description
MASTER_ID17 | 0XFF980144 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID17_MIDP | 31:31 | 80000000 | 0 | 0 | Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
PSU_LPD_XPPU_CFG_MASTER_ID17_MIDR | 30:30 | 40000000 | 0 | 0 | If set, only read transactions are allowed for the masters matching this register
PSU_LPD_XPPU_CFG_MASTER_ID17_MIDM | 25:16 | 3ff0000 | 0 | 0 | Mask to be applied before comparing
PSU_LPD_XPPU_CFG_MASTER_ID17_MID | 9:0 | 3ff | 0 | 0 | Programmable Master ID
PSU_LPD_XPPU_CFG_MASTER_ID17@0XFF980144 | 31:0 | c3ff03ff |  | 0 | Master ID 17 Register

## Register ( slcr )MASTER_ID18

Register Name | Address | Width | Type | Reset Value | Description
MASTER_ID18 | 0XFF980148 | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID18_MIDP | 31:31 | 80000000 | 0 | 0 | Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
PSU_LPD_XPPU_CFG_MASTER_ID18_MIDR | 30:30 | 40000000 | 0 | 0 | If set, only read transactions are allowed for the masters matching this register
PSU_LPD_XPPU_CFG_MASTER_ID18_MIDM | 25:16 | 3ff0000 | 0 | 0 | Mask to be applied before comparing
PSU_LPD_XPPU_CFG_MASTER_ID18_MID | 9:0 | 3ff | 0 | 0 | Programmable Master ID
PSU_LPD_XPPU_CFG_MASTER_ID18@0XFF980148 | 31:0 | c3ff03ff |  | 0 | Master ID 18 Register

## Register ( slcr )MASTER_ID19

Register Name | Address | Width | Type | Reset Value | Description
MASTER_ID19 | 0XFF98014C | 32 | rw | 0x00000000 | --

Field Name | Bits | Mask | Value | Shifted Value | Description
PSU_LPD_XPPU_CFG_MASTER_ID19_MIDP | 31:31 | 80000000 | 0 | 0 | Parity of all non-reserved fields (i.e. MIDR, MIDM, MID)
PSU_LPD_XPPU_CFG_MASTER_ID19_MIDR | 30:30 | 40000000 | 0 | 0 | If set, only read transactions are allowed for the masters matching this register
PSU_LPD_XPPU_CFG_MASTER_ID19_MIDM | 25:16 | 3ff0000 | 0 | 0 | Mask to be applied before comparing
PSU_LPD_XPPU_CFG_MASTER_ID19_MID | 9:0 | 3ff | 0 | 0 | Programmable Master ID
PSU_LPD_XPPU_CFG_MASTER_ID19@0XFF98014C | 31:0 | c3ff03ff |  | 0 | Master ID 19 Register

# APERTURE PERMISIION LIST