# Release Notes for STM32H7xx CMSIS

Copyright © 2017 STMicroelectronics

# License

This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:
https://opensource.org/licenses/BSD-3-Clause

# Update History

V1.5.0 / 05-April-2019

## Main Changes

- General updates to align Bit and registers definition with the STM32H7 reference manual
- Updates to aligned with STM32H7xx rev.V devices
- Add support of stm32h745xx, stm32h747xx, stm32h755xx, stm32h757xx Dual Core devices and STM32H742xx (new single core device):
  - Add “stm32h745xx.h” , “stm32h747xx.h”, “stm32h755xx.h”, “stm32h757xx.h” and “stm32h742xx.h” files
  - Add startup files “startup_stm32h745xx.s”, “startup_stm32h747xx.s”, “startup_stm32h755xx.s”, “startup_stm32h757xx.s” and “startup_stm32h742xx.s” for EWARM , MDK-ARM and SW4STM32 toolchains
  - Add part numbers list to stm32h7xx.h header file:
    - STM32H742xx: STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI
    - STM32H743xx: STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI
    - STM32H753xx: STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI
    - STM32H750xx: STM32H750V, STM32H750I, STM32H750X
    - STM32H747xx: STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI
    - STM32H757xx: STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI
    - STM32H745xx: STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI

    - STM32H755xx: STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI

    - Add system_stm32h7xx_singlecore.c : system initialization template source file for single core lines (STM32H743xx, STM32H753xx, STM32H750xx and STM32H742xx)
    - Add system initialization template source file for dual core lines:
      - system_stm32h7xx_dualcore_boot_cm4_cm7.c: template for the boot case where Cortex-M7 and Cortex-M4 are boot at once
      - system_stm32h7xx_dualcore_bootcm7_cm4gated.c: template for the boot case where Cortex-M7 is booting and Cortex-M4 is gated using FLASH Option Bytes
      - system_stm32h7xx_dualcore_bootcm4_cm7gated.c: template for the boot case where Cortex-M4 is booting and Cortex-M7 is gated using FLASH Option Bytes
    - Add EWARM, MDK-ARM and SW4STM32 Dual Core devices linker files

    - Add EWARM STM32H742xx devices linker files

- Registers and bit field definitions updates:
  - Update SYSCFG_TypeDef structure to add
    - Add CFGR register: allowing to control connection between double ECC RAMs/Flash errors, PVD errors and CortexM7/M4 lockup to TIM1/8/15/16/17 and HRTIMER Break inputs
    - Add definitions of SYSCFG_CFGR register bit fields
    - PWRCR registers: allowing to control the PWR overdrive enable/disable for Voltage Scaling zero
    - Add SYSCFG_PWRCR register bit fields
  - Update RCC_TypeDef structure according to STM32H7xx Rev.V devices:
    - ICSCR: renamed to HSICFGR, HSI Clock Calibration Register
    - Rename also RCC_ICSCR_XXX bit definitions RCC_HSICFGR_XXX according to the new register HSICFGR
    - CSICFGR: New registers (on Rev.V devices), CSI Clock Calibration Register
    - Add dedicated RCC_CSICFGR_XXX bit definitions
  - Keep RCC_Core_TypeDef structure used for Dual Core lines devices only: allowing RCC clock enabling/allocation for each Core(Cortex-M7/M4)
    - RCC_Core_TypeDef structure and RCC_C1_BASE/RCC_C1 definition removed from STM32H743xx/53xx and STM32H750xx lines
  - Add CRYP_CR_NPBLB bit field definition: upon refresh of the CRYP peripheral on the STM32H7 Rev.V devices
  - Update ADC_CR_BOOST bot field definition for STM32H7 Rev.V devices: 2 bits instead of 1
  - Remove useless I2C_CR1_SWRST definition: alignment with the reference manual
  - Add SAI_xCR1_NODIV bit field definition upon SAI peripheral update for STM32H7 Rev.V devices
  - Rename SPI_TXCRC_RXCRC to SPI_RXCRC_RXCRC: typo fix and alignment with the reference manual
  - Fix QUADSPI_SR_FLEVEL bit field definition: Mask on 6 bits (0x3F mask) instead of 5 bits(0x1F mask) and add definition of QUADSPI_SR_FLEVEL_6
  - Add definition of SYSCFG_EXTICR3_EXTI8_PK, SYSCFG_EXTICR3_EXTI9_PK, SYSCFG_EXTICR3_EXTI10_PK, SYSCFG_EXTICR3_EXTI11_PK and SYSCFG_EXTICR4_EXTI13_PK
  - Add definition of FLASH_LATENCY_DEFAULT: default safe FLASH latency

V1.3.1 / 31-January-2019

## Main Changes

- Patch Release on top of V1.3.0
- Add Definition of UID_BASE ( Unique device ID register base address) to the STM32H7xx include files:
  - stm32h743xx.h, stm32h750xx.h and stm32h753xx.h

V1.4.0 / 30-November-2018

## Main Changes

- STM32H7xx include files:
  - General updates to align Bit and registers definition with the STM32H7 reference manual
  - Update "_Mask" bits definition using UL suffix for Misra-C 2012 compliance
  - Add definition of RAMECC_MonitorTypeDef and RAMECC_TypeDef structure
  - Add definition of RAMECC peripheral base addresses
  - Add RAMECC peripheral registers bit definitions
  - Add IS_RAMECC_MONITOR_ALL_INSTANCE macro
  - Add EXTI SWIER3 bit definitions
  - Update FLASH sector number to 8 instead of 16 (8 sectors for each bank)
  - Remove extra bit definition : FLASH_CR_SNB_3 to FLASH_CR_SNB_7
  - Update FLASH user option bytes bit definition
  - Fix FLASH_BANK_SIZE definition: add parenthesis
  - Remove PWR extra bit definition PWR_CR1_RLPSN
  - Add PWR bit definition PWR_WKUPEPR_WKUPEN
  - Fix typo in SDMMC bit definition: SDMMC_MASK_SDIOITIE_Pos, SDMMC_MASK_SDIOITIE_Msk and SDMMC_MASK_SDIOITIE
  - Add SDMMC instance check macro: IS_SDMMC_ALL_INSTANCE
  - Fix typo in SYSCFG bit definition: SYSCFG_PMCR_EPIS_SEL_Pos, SYSCFG_PMCR_EPIS_SEL_Msk, SYSCFG_PMCR_EPIS_SEL and SYSCFG_PMCR_EPIS_SEL_0 to SYSCFG_PMCR_EPIS_SEL_2
  - Fix SYSCFG bit definitions: SYSCFG_EXTICR1_EXTI0_Msk, to SYSCFG_EXTICR1_EXTI3_Msk, 4 bits instead of 3
  - Fix SYSCFG bit definitions: SYSCFG_EXTICR2_EXTI0_Msk, to SYSCFG_EXTICR2_EXTI3_Msk, 4 bits instead of 3
  - Fix SYSCFG bit definitions: SYSCFG_EXTICR3_EXTI0_Msk, to SYSCFG_EXTICR3_EXTI3_Msk, 4 bits instead of 3
  - Fix SYSCFG bit definitions: SYSCFG_EXTICR4_EXTI0_Msk, to SYSCFG_EXTICR3_EXTI4_Msk, 4 bits instead of 3
  - Fix IS_ADC_COMMON_INSTANCE macro : add parenthesis
  - Fix HSEM_CR_COREID_CURRENT and HSEM_CR_COREID_CURRENT: add parenthesis
  - Update USART and SMARTCARD bits definition
  - Update GPIO registers and bit definition (BSRR register)
  - Add IS_GPIO_AF_INSTANCE macro
  - Update DAC bits definition
  - Update FDCAN bits definition
  - Update USB bits definition (OTEPSPRM register)
  - Fix CEC bit definition (RXDR register)
  - Update TIM registers and bits definition naming
  - Fix IS_TIM_CCX_INSTANCE macro : add TIM_CHANNEL_4 to TIM_CHANNEL_6
  - Update SPI and I2S bits definition
  - Update BDMA bits definition
  - Update FMC bits definition

V1.3.0 / 29-June-2018

## Main Changes

- Add support for stm32h750xx value line devices:
  - Add “stm32h750xx.h” file
  - Add startup files startup_stm32h750xx.s for EWARM, MDK-ARM and SW4STM32

V1.2.0 / 29-December-2017

## Main Changes

- Update FDCAN bit definition
- Update SystemCoreClockUpdate() function in system_stm32h7xx.c file to use direct register access

V1.1.0 / 31-August-2017

## Main Changes

- Update USB OTG bit definition
- Adjust PLL fractional computation

V1.0.0 / 21-April-2017

## Main Changes

- First official release for STM32H743xx/753xx devices