forked from len0rd/rockbox
56340f4cd0
This is needed on the jz4760b because if some data is loaded to DRAM, then it
is cached and a disaster lurks if dcaches/icache are not flushed. Targets that
needs this must define CONFIG_FLUSH_CACHES in target-config.h and implement
target_flush_caches(). Currently MIPS has some generic code for mips32r1 that
requires to define {D,I}CACHE_SIZE and {D,I}CACHE_LINE_SIZE in target-config.h
Change-Id: I5a3fc085de9445d8c8a2eb61ae4e2dc9bb6b4e8e
17 lines
481 B
C
17 lines
481 B
C
#define CONFIG_JZ4760B
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#define TCSM0_ORIG 0xf4000000
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#define TCSM0_SIZE 0x4000
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#define CPU_MIPS
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#define STACK_SIZE 0x300
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#define DCACHE_SIZE 0x4000 /* 16 kB */
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#define DCACHE_LINE_SIZE 0x20 /* 32 B */
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#define ICACHE_SIZE 0x4000 /* 16 kB */
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#define ICACHE_LINE_SIZE 0x20 /* 32 B */
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/* we need to flush caches before executing */
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#define CONFIG_FLUSH_CACHES
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/* something provides define
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* #define mips 1
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* which breaks paths badly
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*/
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#undef mips
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