Solomon Peachy e0bb30a1bd xduoox3: Set PLL0 to 480MHz, not 492. ... PLL0 Needs to be a multiple of 48MHz for sane USB operation! (Indeed, "typical" clock for this part is 528, but that seems a waste of power) Also fixes a minor bugaboo in the jz4670 usb divisor calculation that won't matter until we enable reclocking Change-Id: I40b1fd1ae48871e50885981ccc8b01feb711b9a5		2020-08-07 03:44:01 +00:00
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arm	FS#9295: Detect external power supply for ipod 1st & 2nd gen (Mark Fawcus)	2020-08-06 09:28:28 -04:00
coldfire	Coldfire: Don't clobber alwarm wakeup signal in dualboot mode	2019-01-01 23:30:44 -05:00
hosted	[4/4] Remove HAVE_LCD_BITMAP, as it's now the only choice.	2020-07-24 21:20:13 +00:00
mips	xduoox3: Set PLL0 to 480MHz, not 492.	2020-08-07 03:44:01 +00:00