forked from len0rd/rockbox
e61e9c61d0
* SOUND_x enum can be generated by audiohw_settings.h along with settings entries and sound_val2phys. * VOLUME_MIN and VOLUME_MAX are no longer necessary within sound.c. If you need them, they are for target-defined purposes. * Fix up SDL volume implementation in sdl.c. Move sim volume calculation code to pcm-sdl.c. * Min trigger tresholds were based upon VOLUME_MIN for some reason. These setting have nothing to do with playback volume. Since it is no longer present, set these at -89dB which is the minimum peak meter sensitivity setting. * Fix an oversight in wm8758.c. I forgot to add the dB->register conversion to audiohw_set_volume. Change-Id: Ie1df33f1793eee75e6793f16bc7bddd16edb7f75
542 lines
22 KiB
C
542 lines
22 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 by Michael Sevakis
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*
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* Header file for WM8978 codec
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef _WM8978_H
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#define _WM8978_H
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#if 0
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#define AUDIOHW_CAPS (EQ_CAP | PRESCALER_CAP | DEPTH_3D_CAP | \
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LIN_GAIN_CAP | MIC_GAIN_CAP)
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#else
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#define AUDIOHW_CAPS (EQ_CAP | PRESCALER_CAP | DEPTH_3D_CAP | \
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LIN_GAIN_CAP)
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#endif
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/* Filter bitmask */
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#define AUDIOHW_EQ_BAND_CAPS ((EQ_CAP << 0) | (EQ_CAP << 1) | \
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(EQ_CAP << 2) | (EQ_CAP << 3) | \
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(EQ_CAP << 4))
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/* Filters that can adjust cutoff and center frequency */
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#define AUDIOHW_EQ_FREQUENCY_CAPS ((EQ_CAP << 0) | (EQ_CAP << 1) | \
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(EQ_CAP << 2) | (EQ_CAP << 3) | \
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(EQ_CAP << 4))
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/* Filters that can adjust band width */
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#define AUDIOHW_EQ_WIDTH_CAPS ((EQ_CAP << 1) | (EQ_CAP << 2) | \
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(EQ_CAP << 3))
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AUDIOHW_SETTING(VOLUME, "dB", 0, 1, -90, 6, -25)
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AUDIOHW_SETTING(EQ_BAND1_GAIN, "dB", 0, 1, -12, 12, 0)
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AUDIOHW_SETTING(EQ_BAND2_GAIN, "dB", 0, 1, -12, 12, 0)
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AUDIOHW_SETTING(EQ_BAND3_GAIN, "dB", 0, 1, -12, 12, 0)
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AUDIOHW_SETTING(EQ_BAND4_GAIN, "dB", 0, 1, -12, 12, 0)
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AUDIOHW_SETTING(EQ_BAND5_GAIN, "dB", 0, 1, -12, 12, 0)
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AUDIOHW_SETTING(EQ_BAND1_FREQUENCY, "", 0, 1, 0, 3, 0)
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AUDIOHW_SETTING(EQ_BAND2_FREQUENCY, "", 0, 1, 0, 3, 0)
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AUDIOHW_SETTING(EQ_BAND3_FREQUENCY, "", 0, 1, 0, 3, 0)
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AUDIOHW_SETTING(EQ_BAND4_FREQUENCY, "", 0, 1, 0, 3, 0)
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AUDIOHW_SETTING(EQ_BAND5_FREQUENCY, "", 0, 1, 0, 3, 0)
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AUDIOHW_SETTING(EQ_BAND2_WIDTH, "", 0, 1, 0, 1, 0)
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AUDIOHW_SETTING(EQ_BAND3_WIDTH, "", 0, 1, 0, 1, 0)
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AUDIOHW_SETTING(EQ_BAND4_WIDTH, "", 0, 1, 0, 1, 0)
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AUDIOHW_SETTING(DEPTH_3D, "%", 0, 1, 0, 15, 0, (100*val + 8) / 15)
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#ifdef HAVE_RECORDING
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/* Digital: -119.0dB to +8.0dB in 0.5dB increments
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* Analog: Relegated to volume control
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* Circumstances unfortunately do not allow a great deal of positive
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* gain. */
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AUDIOHW_SETTING(LEFT_GAIN, "dB", 1, 1,-238, 16, 0, val * 5)
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AUDIOHW_SETTING(RIGHT_GAIN, "dB", 1, 1,-238, 16, 0, val * 5)
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#if 0 /* whenever it's needed - none on GBS */
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AUDIOHW_SETTING(MIC_GAIN, "dB", 1, 1,-238, 16, 0, val * 5)
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#endif /* 0 */
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#endif /* HAVE_RECORDING */
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void audiohw_set_recsrc(int source, bool recording);
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void wmc_set(unsigned int reg, unsigned int bits);
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void wmc_clear(unsigned int reg, unsigned int bits);
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#define WMC_I2C_ADDR 0x34
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/* Registers */
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#define WMC_SOFTWARE_RESET 0x00
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#define WMC_POWER_MANAGEMENT1 0x01
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#define WMC_POWER_MANAGEMENT2 0x02
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#define WMC_POWER_MANAGEMENT3 0x03
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#define WMC_AUDIO_INTERFACE 0x04
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#define WMC_COMPANDING_CTRL 0x05
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#define WMC_CLOCK_GEN_CTRL 0x06
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#define WMC_ADDITIONAL_CTRL 0x07
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#define WMC_GPIO 0x08
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#define WMC_JACK_DETECT_CONTROL1 0x09
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#define WMC_DAC_CONTROL 0x0a
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#define WMC_LEFT_DAC_DIGITAL_VOL 0x0b
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#define WMC_RIGHT_DAC_DIGITAL_VOL 0x0c
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#define WMC_JACK_DETECT_CONTROL2 0x0d
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#define WMC_ADC_CONTROL 0x0e
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#define WMC_LEFT_ADC_DIGITAL_VOL 0x0f
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#define WMC_RIGHT_ADC_DIGITAL_VOL 0x10
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#define WMC_EQ1_LOW_SHELF 0x12
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#define WMC_EQ2_PEAK1 0x13
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#define WMC_EQ3_PEAK2 0x14
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#define WMC_EQ4_PEAK3 0x15
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#define WMC_EQ5_HIGH_SHELF 0x16
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#define WMC_DAC_LIMITER1 0x18
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#define WMC_DAC_LIMITER2 0x19
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#define WMC_NOTCH_FILTER1 0x1b
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#define WMC_NOTCH_FILTER2 0x1c
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#define WMC_NOTCH_FILTER3 0x1d
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#define WMC_NOTCH_FILTER4 0x1e
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#define WMC_ALC_CONTROL1 0x20
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#define WMC_ALC_CONTROL2 0x21
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#define WMC_ALC_CONTROL3 0x22
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#define WMC_NOISE_GATE 0x23
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#define WMC_PLL_N 0x24
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#define WMC_PLL_K1 0x25
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#define WMC_PLL_K2 0x26
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#define WMC_PLL_K3 0x27
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#define WMC_3D_CONTROL 0x29
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#define WMC_BEEP_CONTROL 0x2b
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#define WMC_INPUT_CTRL 0x2c
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#define WMC_LEFT_INP_PGA_GAIN_CTRL 0x2d
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#define WMC_RIGHT_INP_PGA_GAIN_CTRL 0x2e
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#define WMC_LEFT_ADC_BOOST_CTRL 0x2f
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#define WMC_RIGHT_ADC_BOOST_CTRL 0x30
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#define WMC_OUTPUT_CTRL 0x31
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#define WMC_LEFT_MIXER_CTRL 0x32
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#define WMC_RIGHT_MIXER_CTRL 0x33
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#define WMC_LOUT1_HP_VOLUME_CTRL 0x34
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#define WMC_ROUT1_HP_VOLUME_CTRL 0x35
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#define WMC_LOUT2_SPK_VOLUME_CTRL 0x36
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#define WMC_ROUT2_SPK_VOLUME_CTRL 0x37
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#define WMC_OUT3_MIXER_CTRL 0x38
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#define WMC_OUT4_MONO_MIXER_CTRL 0x39
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#define WMC_NUM_REGISTERS 0x3a
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/* Register bitmasks */
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/* Volume update bit for volume registers */
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#define WMC_VU (1 << 8)
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/* Zero-crossing bit for volume registers */
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#define WMC_ZC (1 << 7)
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/* Mute bit for volume registers */
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#define WMC_MUTE (1 << 6)
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/* Volume masks and macros for digital volumes */
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#define WMC_DVOL 0xff
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/* Volums masks and macros for analogue volumes */
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#define WMC_AVOL 0x3f
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/* WMC_SOFTWARE_RESET (0x00) */
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#define WMC_RESET
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/* Write any value */
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/* WMC_POWER_MANAGEMENT1 (0x01) */
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#define WMC_BUFDCOMPEN (1 << 8)
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#define WMC_OUT4MIXEN (1 << 7)
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#define WMC_OUT3MIXEN (1 << 6)
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#define WMC_PLLEN (1 << 5)
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#define WMC_MICBEN (1 << 4)
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#define WMC_BIASEN (1 << 3)
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#define WMC_BUFIOEN (1 << 2)
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#define WMC_VMIDSEL (3 << 0)
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#define WMC_VMIDSEL_OFF (0 << 0)
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#define WMC_VMIDSEL_75K (1 << 0)
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#define WMC_VMIDSEL_300K (2 << 0)
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#define WMC_VMIDSEL_5K (3 << 0)
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/* WMC_POWER_MANAGEMENT2 (0x02) */
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#define WMC_ROUT1EN (1 << 8)
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#define WMC_LOUT1EN (1 << 7)
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#define WMC_SLEEP (1 << 6)
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#define WMC_BOOSTENR (1 << 5)
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#define WMC_BOOSTENL (1 << 4)
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#define WMC_INPPGAENR (1 << 3)
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#define WMC_INPPGAENL (1 << 2)
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#define WMC_ADCENR (1 << 1)
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#define WMC_ADCENL (1 << 0)
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/* WMC_POWER_MANAGEMENT3 (0x03) */
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#define WMC_OUT4EN (1 << 8)
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#define WMC_OUT3EN (1 << 7)
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#define WMC_LOUT2EN (1 << 6)
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#define WMC_ROUT2EN (1 << 5)
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#define WMC_RMIXEN (1 << 3)
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#define WMC_LMIXEN (1 << 2)
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#define WMC_DACENR (1 << 1)
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#define WMC_DACENL (1 << 0)
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/* WMC_AUDIO_INTERFACE (0x04) */
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#define WMC_BCP (1 << 8)
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#define WMC_LRP (1 << 7)
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#define WMC_WL (3 << 5)
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#define WMC_WL_16 (0 << 5)
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#define WMC_WL_20 (1 << 5)
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#define WMC_WL_24 (2 << 5)
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#define WMC_WL_32 (3 << 5)
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#define WMC_FMT (3 << 3)
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#define WMC_FMT_RJUST (0 << 3)
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#define WMC_FMT_LJUST (1 << 3)
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#define WMC_FMT_I2S (2 << 3)
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#define WMC_FMT_DSP_PCM (3 << 3)
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#define WMC_DACLRSWAP (1 << 2)
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#define WMC_ADCLRSWAP (1 << 1)
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#define WMC_MONO (1 << 0)
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/* WMC_COMPANDING_CTRL (0x05) */
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#define WMC_WL8 (1 << 5)
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#define WMC_DAC_COMP (3 << 3)
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#define WMC_DAC_COMP_OFF (0 << 3)
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#define WMC_DAC_COMP_U_LAW (2 << 3)
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#define WMC_DAC_COMP_A_LAW (3 << 3)
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#define WMC_ADC_COMP (3 << 1)
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#define WMC_ADC_COMP_OFF (0 << 1)
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#define WMC_ADC_COMP_U_LAW (2 << 1)
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#define WMC_ADC_COMP_A_LAW (3 << 1)
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#define WMC_LOOPBACK (1 << 0)
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/* WMC_CLOCK_GEN_CTRL (0x06) */
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#define WMC_CLKSEL (1 << 8)
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#define WMC_MCLKDIV (7 << 5)
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#define WMC_MCLKDIV_1 (0 << 5)
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#define WMC_MCLKDIV_1_5 (1 << 5)
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#define WMC_MCLKDIV_2 (2 << 5)
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#define WMC_MCLKDIV_3 (3 << 5)
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#define WMC_MCLKDIV_4 (4 << 5)
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#define WMC_MCLKDIV_6 (5 << 5)
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#define WMC_MCLKDIV_8 (6 << 5)
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#define WMC_MCLKDIV_12 (7 << 5)
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#define WMC_BCLKDIV (7 << 2)
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#define WMC_BCLKDIV_1 (0 << 2)
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#define WMC_BCLKDIV_2 (1 << 2)
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#define WMC_BCLKDIV_4 (2 << 2)
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#define WMC_BCLKDIV_8 (3 << 2)
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#define WMC_BCLKDIV_16 (4 << 2)
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#define WMC_BCLKDIV_32 (5 << 2)
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#define WMC_MS (1 << 0)
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/* WMC_ADDITIONAL_CTRL (0x07) */
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/* This configure the digital filter coefficients - pick the closest
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* to what's really being used (greater than or equal). */
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#define WMC_SR (7 << 1)
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#define WMC_SR_48KHZ (0 << 1)
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#define WMC_SR_32KHZ (1 << 1)
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#define WMC_SR_24KHZ (2 << 1)
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#define WMC_SR_16KHZ (3 << 1)
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#define WMC_SR_12KHZ (4 << 1)
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#define WMC_SR_8KHZ (5 << 1)
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/* 110-111=reserved */
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#define WMC_SLOWCLKEN (1 << 0)
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/* WMC_GPIO (0x08) */
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#define WMC_OPCLKDIV (3 << 4)
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#define WMC_OPCLKDIV_1 (0 << 4)
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#define WMC_OPCLKDIV_2 (1 << 4)
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#define WMC_OPCLKDIV_3 (2 << 4)
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#define WMC_OPCLKDIV_4 (3 << 4)
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#define WMC_GPIO1POL (1 << 3)
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#define WMC_GPIO1SEL (7 << 0)
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#define WMC_GPIO1SEL_TEMP_OK (2 << 0)
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#define WMC_GPIO1SEL_AMUTE_ACTIVE (3 << 0)
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#define WMC_GPIO1SEL_PLL_CLK_OP (4 << 0)
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#define WMC_GPIO1SEL_PLL_LOCK (5 << 0)
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#define WMC_GPIO1SEL_LOGIC_1 (6 << 0)
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#define WMC_GPIO1SEL_LOGIC_0 (7 << 0)
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/* WMC_JACK_DETECT_CONTROL1 (0x09) */
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#define WMC_JD_VMID (3 << 7)
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#define WMC_JD_VMID_EN_0 (1 << 7)
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#define WMC_JD_VMID_EN_1 (2 << 7)
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#define WMC_JD_EN (1 << 6)
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#define WMC_JD_SEL (3 << 4)
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#define WMC_JD_SEL_GPIO1 (0 << 4)
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#define WMC_JD_SEL_GPIO2 (1 << 4)
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#define WMC_JD_SEL_GPIO3 (2 << 4)
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/* WMC_DAC_CONTROL (0x0a) */
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#define WMC_SOFT_MUTE (1 << 6)
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#define WMC_DACOSR_128 (1 << 3)
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#define WMC_AMUTE (1 << 2)
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#define WMC_DACPOLR (1 << 1)
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#define WMC_DACPOLL (1 << 0)
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/* WMC_LEFT_DAC_DIGITAL_VOL (0x0b) */
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/* WMC_RIGHT_DAC_DIGITAL_VOL (0x0c) */
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/* 00000000=mute, 00000001=-127dB...(0.5dB steps)...11111111=0dB */
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/* Use WMC_DVOL* macros */
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/* WMC_JACK_DETECT_CONTROL2 (0x0d) */
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#define WMC_JD_EN1 (0xf << 4)
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#define WMC_OUT1_EN1 (1 << 4)
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#define WMC_OUT2_EN1 (2 << 4)
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#define WMC_OUT3_EN1 (4 << 4)
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#define WMC_OUT4_EN1 (8 << 4)
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#define WMC_JD_EN0 (0xf << 0)
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#define WMC_OUT1_EN0 (1 << 0)
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#define WMC_OUT2_EN0 (2 << 0)
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#define WMC_OUT3_EN0 (4 << 0)
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#define WMC_OUT4_EN0 (8 << 0)
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/* WMC_ADC_CONTROL (0x0e) */
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#define WMC_HPFEN (1 << 8)
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#define WMC_HPFAPP (1 << 7)
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#define WMC_HPFCUT (7 << 4)
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#define WMC_ADCOSR (1 << 3)
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#define WMC_ADCRPOL (1 << 1)
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#define WMC_ADCLPOL (1 << 0)
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/* WMC_LEFT_ADC_DIGITAL_VOL (0x0f) */
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/* WMC_RIGHT_ADC_DITIGAL_VOL (0x10) */
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/* 0.5dB steps: Mute:0x00, -127dB:0x01...0dB:0xff */
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/*Use WMC_DVOL* macros */
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/* Gain */
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#define WMC_EQG (0x1f << 0)
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/* Cutoff/Center */
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#define WMC_EQC (0x3 << 5)
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#define WMC_EQC_POS (5)
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/* Bandwidth */
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#define WMC_EQBW (1 << 8)
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/* WMC_EQ1_LOW_SHELF (0x12) */
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#define WMC_EQ3DMODE (1 << 8)
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#define WMC_EQ1C_80HZ (0 << 5) /* 80Hz */
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#define WMC_EQ1C_105HZ (1 << 5) /* 105Hz */
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#define WMC_EQ1C_135HZ (2 << 5) /* 135Hz */
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#define WMC_EQ1C_175HZ (3 << 5) /* 175Hz */
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/* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB, 11001-11111=reserved */
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/* WMC_EQ2_PEAK1 (0x13) */
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#define WMC_EQ2C_230HZ (0 << 5) /* 230Hz */
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#define WMC_EQ2C_300HZ (1 << 5) /* 300Hz */
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#define WMC_EQ2C_385HZ (2 << 5) /* 385Hz */
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#define WMC_EQ2C_500HZ (3 << 5) /* 500Hz */
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/* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB,
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11001-11111=reserved */
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/* WMC_EQ3_PEAK2 (0x14) */
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#define WMC_EQ3C_650HZ (0 << 5) /* 650Hz */
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#define WMC_EQ3C_850HZ (1 << 5) /* 850Hz */
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#define WMC_EQ3C_1_1KHZ (2 << 5) /* 1.1kHz */
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#define WMC_EQ3C_1_4KHZ (3 << 5) /* 1.4kHz */
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/* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB,
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11001-11111=reserved */
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/* WMC_EQ4_PEAK3 (0x15) */
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#define WMC_EQ4C_1_8KHZ (0 << 5) /* 1.8kHz */
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#define WMC_EQ4C_2_4KHZ (1 << 5) /* 2.4kHz */
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#define WMC_EQ4C_3_2KHZ (2 << 5) /* 3.2kHz */
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#define WMC_EQ4C_4_1KHZ (3 << 5) /* 4.1kHz */
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/* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB,
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11001-11111=reserved */
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/* WMC_EQ5_HIGH_SHELF (0x16) */
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#define WMC_EQ5C_5_3KHZ (0 << 5) /* 5.3kHz */
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#define WMC_EQ5C_6_9KHZ (1 << 5) /* 6.9kHz */
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#define WMC_EQ5C_9KHZ (2 << 5) /* 9.0kHz */
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#define WMC_EQ5C_11_7KHZ (3 << 5) /* 11.7kHz */
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/* 00000=+12dB, 00001=+11dB...(-1dB steps)...11000=-12dB,
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11001-11111=reserved */
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/* WMC_DAC_LIMITER1 (0x18) */
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#define WMC_LIMEN (1 << 8)
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/* 0000=750uS, 0001=1.5mS...(x2 each step)...1010-1111=768mS */
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#define WMC_LIMDCY (0xf << 4)
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#define WMC_LIMDCY_POS (4)
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/* 0000=94uS, 0001=188uS...(x2 each step)...1011-1111=192mS */
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#define WMC_LIMATK (0xf << 0)
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/* WMC_DAC_LIMITER2 (0x19) */
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/* 000=-1dB, 001=-2dB...(-1dB steps)...101-111:-6dB */
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#define WMC_LIMLVL (7 << 4)
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#define WMC_LIMLVL_POS (4)
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/* 0000=0dB, 0001=+1dB...1100=+12dB, 1101-1111=reserved */
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#define WMC_LIMBOOST (0xf << 0)
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/* Generic notch filter bits and macros */
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#define WMC_NFU (1 << 8)
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#define WMC_NFA (0x7f << 0)
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/* WMC_NOTCH_FILTER1 (0x1b) */
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#define WMC_NFEN (1 << 7)
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/* WMC_NOTCH_FILTER2 (0x1c) */
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/* WMC_NOTCH_FILTER3 (0x1d) */
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/* WMC_NOTCH_FILTER4 (0x1e) */
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/* WMC_ALC_CONTROL1 (0x20) */
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#define WMC_ALCSEL (3 << 7)
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#define WMC_ALCSEL_OFF (0 << 7)
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#define WMC_ALCSEL_RIGHT_ONLY (1 << 7)
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#define WMC_ALCSEL_LEFT_ONLY (2 << 7)
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#define WMC_ALCSEL_BOTH_ON (3 << 7)
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/* 000=-6.75dB, 001=-0.75dB...(6dB steps)...111=+35.25dB */
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#define WMC_ALCMAXGAIN (7 << 3)
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#define WMC_ALCMAXGAIN_POS (3)
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/* 000:-12dB...(6dB steps)...111:+30dB */
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#define WMC_ALCMINGAIN (7 << 0)
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/* WMC_ALC_CONTROL2 (0x21) */
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/* 0000=0ms, 0001=2.67ms, 0010=5.33ms...
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(2x with every step)...43.691s */
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#define WMC_ALCHLD (0xf << 4)
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#define WMC_ALCHLD_POS (4)
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/* 1111:-1.5dBFS, 1110:-1.5dBFS, 1101:-3dBFS, 1100:-4.5dBFS...
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(-1.5dB steps)...0001:-21dBFS, 0000:-22.5dBFS */
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#define WMC_ALCLVL (0xf << 0)
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/* WMC_ALC_CONTROL3 (0x22) */
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#define WMC_ALCMODE (1 << 8)
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#define WMC_ALCDCY (0xf << 4)
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#define WMC_ALCATK (0xf << 0)
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/* WMC_NOISE_GATE (0x23) */
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#define WMC_NGEN (1 << 3)
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/* 000=-39dB, 001=-45dB, 010=-51dB...(6dB steps)...111=-81dB */
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#define WMC_NGTH (7 << 0)
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/* WMC_PLL_N (0x24) */
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#define WMC_PLL_PRESCALE (1 << 4)
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#define WMC_PLLN (0xf << 0)
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/* WMC_PLL_K1 (0x25) */
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#define WMC_PLLK_23_18 (0x3f << 0)
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/* WMC_PLL_K2 (0x26) */
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#define WMC_PLLK_17_9 (0x1ff << 0)
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/* WMC_PLL_K3 (0x27) */
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#define WMC_PLLK_8_0 (0x1ff << 0)
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/* WMC_3D_CONTROL (0x29) */
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/* 0000: 0%, 0001: 6.67%...1110: 93.3%, 1111: 100% */
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#define WMC_DEPTH3D (0xf << 0)
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/* WMC_BEEP_CONTROL (0x2b) */
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#define WMC_MUTERPGA2INV (1 << 5)
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#define WMC_INVROUT2 (1 << 4)
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/* 000=-15dB, 001=-12dB...111=+6dB */
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#define WMC_BEEPVOL (7 << 1)
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#define WMC_BEEPVOL_POS (1)
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#define WMC_BEEPEN (1 << 0)
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/* WMC_INPUT_CTRL (0x2c) */
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#define WMC_MBVSEL (1 << 8)
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#define WMC_R2_2INPPGA (1 << 6)
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#define WMC_RIN2INPPGA (1 << 5)
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#define WMC_RIP2INPPGA (1 << 4)
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#define WMC_L2_2INPPGA (1 << 2)
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#define WMC_LIN2INPPGA (1 << 1)
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#define WMC_LIP2INPPGA (1 << 0)
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/* WMC_LEFT_INP_PGA_GAIN_CTRL (0x2d) */
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/* 000000=-12dB, 000001=-11.25dB...010000=0dB, 111111=+35.25dB */
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/* Uses WMC_AVOL* macros */
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/* WMC_RIGHT_INP_PGA_GAIN_CTRL (0x2e) */
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/* 000000=-12dB, 000001=-11.25dB...010000=0dB, 111111=+35.25dB */
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/* Uses WMC_AVOL* macros */
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/* WMC_LEFT_ADC_BOOST_CTRL (0x2f) */
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#define WMC_PGABOOSTL (1 << 8)
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/* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */
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#define WMC_L2_2BOOSTVOL (7 << 4)
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#define WMC_L2_2BOOSTVOL_POS (4)
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/* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */
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#define WMC_AUXL2BOOSTVOL (7 << 0)
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/* WMC_RIGHT_ADC_BOOST_CTRL (0x30) */
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#define WMC_PGABOOSTR (1 << 8)
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/* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */
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#define WMC_R2_2BOOSTVOL (7 << 4)
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#define WMC_R2_2BOOSTVOL_POS (4)
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/* 000=disabled, 001=-12dB, 010=-9dB...111=+6dB */
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#define WMC_AUXR2BOOSTVOL (7 << 0)
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/* WMC_OUTPUT_CTRL (0x31) */
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#define WMC_DACL2RMIX (1 << 6)
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#define WMC_DACR2LMIX (1 << 5)
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#define WMC_OUT4BOOST (1 << 4)
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#define WMC_OUT3BOOST (1 << 3)
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#define WMC_SPKBOOST (1 << 2)
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#define WMC_TSDEN (1 << 1)
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#define WMC_VROI (1 << 0)
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/* WMC_LEFT_MIXER_CTRL (0x32) */
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/* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */
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#define WMC_AUXLMIXVOL (7 << 6)
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#define WMC_AUXLMIXVOL_POS (6)
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#define WMC_AUXL2LMIX (1 << 5)
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/* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */
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#define WMC_BYPLMIXVOL (7 << 2)
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#define WMC_BYPLMIXVOL_POS (2)
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#define WMC_BYPL2LMIX (1 << 1)
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#define WMC_DACL2LMIX (1 << 0)
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/* WMC_RIGHT_MIXER_CTRL (0x33) */
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/* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */
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#define WMC_AUXRMIXVOL (7 << 6)
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#define WMC_AUXRMIXVOL_POS (6)
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#define WMC_AUXR2RMIX (1 << 5)
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/* 000=-15dB, 001=-12dB...101=0dB, 110=+3dB, 111=+6dB */
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#define WMC_BYPRMIXVOL (7 << 2)
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#define WMC_BYPRMIXVOL_POS (2)
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#define WMC_BYPR2RMIX (1 << 1)
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#define WMC_DACR2RMIX (1 << 0)
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/* WMC_LOUT1_HP_VOLUME_CTRL (0x34) */
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/* WMC_ROUT1_HP_VOLUME_CTRL (0x35) */
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/* WMC_LOUT2_SPK_VOLUME_CTRL (0x36) */
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/* WMC_ROUT2_SPK_VOLUME_CTRL (0x37) */
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/* 000000=-57dB...111001=0dB...111111=+6dB */
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/* Uses WMC_AVOL* macros */
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/* WMC_OUT3_MIXER_CTRL (0x38) */
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#define WMC_OUT42OUT3 (1 << 3)
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#define WMC_BYPL2OUT3 (1 << 2)
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#define WMC_LMIX2OUT3 (1 << 1)
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#define WMC_LDAC2OUT3 (1 << 0)
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/* WMC_OUT4_MONO_MIXER_CTRL (0x39) */
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#define WMC_HALFSIG (1 << 5)
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#define WMC_LMIX2OUT4 (1 << 4)
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#define WMC_LDAC2OUT4 (1 << 3)
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#define WMC_BYPR2OUT4 (1 << 2)
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#define WMC_RMIX2OUT4 (1 << 1)
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#define WMC_RDAC2OUT4 (1 << 0)
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/* For implementing samplerate conrol */
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struct wmc_srctrl_entry
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{
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uint32_t plln : 8;
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uint32_t pllk1 : 6;
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uint32_t pllk2 : 9;
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uint32_t pllk3 : 9;
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unsigned char mclkdiv;
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unsigned char filter;
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};
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#endif /* _WM8978_H */
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