forked from len0rd/rockbox
70 lines
2.9 KiB
C
70 lines
2.9 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 3.0.0
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* cortex_m7 version: 1.0
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* cortex_m7 authors: Aidan MacDonald
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*
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* Copyright (C) 2015 by the authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __ARM_CORTEX_M_NVIC_H__
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#define __ARM_CORTEX_M_NVIC_H__
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#include "macro.h"
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#define REG_NVIC_ISER(_n1) cm_reg(NVIC_ISER(_n1))
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#define CMA_NVIC_ISER(_n1) (0xe000e000 + 0x100 + (_n1) * 0x4)
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#define CMT_NVIC_ISER(_n1) CMIO_32_RW
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#define CMN_NVIC_ISER(_n1) NVIC_ISER
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#define REG_NVIC_ICER(_n1) cm_reg(NVIC_ICER(_n1))
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#define CMA_NVIC_ICER(_n1) (0xe000e000 + 0x180 + (_n1) * 0x4)
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#define CMT_NVIC_ICER(_n1) CMIO_32_RW
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#define CMN_NVIC_ICER(_n1) NVIC_ICER
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#define REG_NVIC_ISPR(_n1) cm_reg(NVIC_ISPR(_n1))
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#define CMA_NVIC_ISPR(_n1) (0xe000e000 + 0x200 + (_n1) * 0x4)
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#define CMT_NVIC_ISPR(_n1) CMIO_32_RW
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#define CMN_NVIC_ISPR(_n1) NVIC_ISPR
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#define REG_NVIC_ICPR(_n1) cm_reg(NVIC_ICPR(_n1))
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#define CMA_NVIC_ICPR(_n1) (0xe000e000 + 0x280 + (_n1) * 0x4)
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#define CMT_NVIC_ICPR(_n1) CMIO_32_RW
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#define CMN_NVIC_ICPR(_n1) NVIC_ICPR
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#define REG_NVIC_IABR(_n1) cm_reg(NVIC_IABR(_n1))
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#define CMA_NVIC_IABR(_n1) (0xe000e000 + 0x300 + (_n1) * 0x4)
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#define CMT_NVIC_IABR(_n1) CMIO_32_RW
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#define CMN_NVIC_IABR(_n1) NVIC_IABR
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#define REG_NVIC_IPR(_n1) cm_reg(NVIC_IPR(_n1))
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#define CMA_NVIC_IPR(_n1) (0xe000e000 + 0x400 + (_n1) * 0x4)
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#define CMT_NVIC_IPR(_n1) CMIO_32_RW
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#define CMN_NVIC_IPR(_n1) NVIC_IPR
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#define REG_NVIC_STIR cm_reg(NVIC_STIR)
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#define CMA_NVIC_STIR (0xe000e000 + 0xf00)
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#define CMT_NVIC_STIR CMIO_32_RW
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#define CMN_NVIC_STIR NVIC_STIR
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#define BP_NVIC_STIR_INTID 0
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#define BM_NVIC_STIR_INTID 0x1ff
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#define BF_NVIC_STIR_INTID(v) (((v) & 0x1ff) << 0)
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#define BFM_NVIC_STIR_INTID(v) BM_NVIC_STIR_INTID
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#define BF_NVIC_STIR_INTID_V(e) BF_NVIC_STIR_INTID(BV_NVIC_STIR_INTID__##e)
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#define BFM_NVIC_STIR_INTID_V(v) BM_NVIC_STIR_INTID
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#endif /* __ARM_CORTEX_M_NVIC_H__*/
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