forked from len0rd/rockbox
a07c034de7
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16243 a1c6a512-1295-4272-9138-f99709370657
515 lines
26 KiB
C
Executable file
515 lines
26 KiB
C
Executable file
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006 by James Espinoza
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/* Most(if not all) of these defines are copied from Nand-Boot v4 provided w/ the Imx31 Linux Bsp*/
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#define REG8_PTR_T volatile unsigned char *
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#define REG16_PTR_T volatile unsigned short *
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#define REG32_PTR_T volatile unsigned long *
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/* Place in the section with the framebuffer */
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#define TTB_BASE_ADDR (0x80100000 + 0x00100000 - TTB_SIZE)
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#define IRAM_BASE_ADDR 0x1fffc000
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#define L2CC_BASE_ADDR 0x30000000
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/*Frame Buffer and TTB defines from gigabeat f/x build*/
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#define FRAME ((short *)0x80100000) /* Framebuffer */
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#define LCD_BUFFER_SIZE ((320*240*2))
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#define TTB_SIZE (0x4000)
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#define TTB_BASE ((unsigned int *)TTB_BASE_ADDR)
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/*
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* AIPS 1
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*/
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#define AIPS1_BASE_ADDR 0x43F00000
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#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
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#define MAX_BASE_ADDR 0x43F04000
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#define EVTMON_BASE_ADDR 0x43F08000
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#define CLKCTL_BASE_ADDR 0x43F0C000
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#define ETB_SLOT4_BASE_ADDR 0x43F10000
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#define ETB_SLOT5_BASE_ADDR 0x43F14000
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#define ECT_CTIO_BASE_ADDR 0x43F18000
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#define I2C_BASE_ADDR 0x43F80000
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#define I2C3_BASE_ADDR 0x43F84000
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#define OTG_BASE_ADDR 0x43F88000
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#define ATA_BASE_ADDR 0x43F8C000
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#define UART1_BASE_ADDR 0x43F90000
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#define UART2_BASE_ADDR 0x43F94000
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#define I2C2_BASE_ADDR 0x43F98000
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#define OWIRE_BASE_ADDR 0x43F9C000
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#define SSI1_BASE_ADDR 0x43FA0000
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#define CSPI1_BASE_ADDR 0x43FA4000
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#define KPP_BASE_ADDR 0x43FA8000
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#define IOMUXC_BASE_ADDR 0x43FAC000
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#define UART4_BASE_ADDR 0x43FB0000
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#define UART5_BASE_ADDR 0x43FB4000
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#define ECT_IP1_BASE_ADDR 0x43FB8000
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#define ECT_IP2_BASE_ADDR 0x43FBC000
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/*
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* SPBA
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*/
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#define SPBA_BASE_ADDR 0x50000000
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#define MMC_SDHC1_BASE_ADDR 0x50004000
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#define MMC_SDHC2_BASE_ADDR 0x50008000
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#define UART3_BASE_ADDR 0x5000C000
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#define CSPI2_BASE_ADDR 0x50010000
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#define SSI2_BASE_ADDR 0x50014000
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#define SIM_BASE_ADDR 0x50018000
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#define IIM_BASE_ADDR 0x5001C000
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#define ATA_DMA_BASE_ADDR 0x50020000
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#define SPBA_CTRL_BASE_ADDR 0x5003C000
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/*
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* AIPS 2
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*/
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#define AIPS2_BASE_ADDR 0x53F00000
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#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
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#define CCM_BASE_ADDR 0x53F80000
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#define FIRI_BASE_ADDR 0x53F8C000
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#define GPT1_BASE_ADDR 0x53F90000
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#define EPIT1_BASE_ADDR 0x53F94000
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#define EPIT2_BASE_ADDR 0x53F98000
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#define GPIO3_BASE_ADDR 0x53FA4000
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#define SCC_BASE 0x53FAC000
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#define SCM_BASE 0x53FAE000
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#define SMN_BASE 0x53FAF000
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#define RNGA_BASE_ADDR 0x53FB0000
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#define IPU_CTRL_BASE_ADDR 0x53FC0000
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#define AUDMUX_BASE 0x53FC4000
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#define MPEG4_ENC_BASE 0x53FC8000
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#define GPIO1_BASE_ADDR 0x53FCC000
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#define GPIO2_BASE_ADDR 0x53FD0000
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#define SDMA_BASE_ADDR 0x53FD4000
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#define RTC_BASE_ADDR 0x53FD8000
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#define WDOG_BASE_ADDR 0x53FDC000
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#define PWM_BASE_ADDR 0x53FE0000
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#define RTIC_BASE_ADDR 0x53FEC000
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#define WDOG1_BASE_ADDR WDOG_BASE_ADDR
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#define CRM_MCU_BASE_ADDR CCM_BASE_ADDR
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/* IPU */
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#define IPU_CONF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x00))
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#define IPU_CHA_BUF0_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x04))
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#define IPU_CHA_BUF1_RDY (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x08))
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#define IPU_CHA_DB_MODE_SEL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x0C))
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#define IPU_CHA_CUR_BUF (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x10))
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#define IPU_FS_PROC_FLOW (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x14))
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#define IPU_FS_DISP_FLOW (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x18))
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#define IPU_TASKS_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x1C))
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#define IPU_IMA_ADDR (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x20))
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#define IPU_IMA_DATA (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x24))
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#define IPU_INT_CTRL_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x28))
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#define IPU_INT_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x2C))
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#define IPU_INT_CTRL_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x30))
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#define IPU_INT_CTRL_4 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x34))
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#define IPU_INT_CTRL_5 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x38))
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#define IPU_INT_STAT_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x3C))
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#define IPU_INT_STAT_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x40))
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#define IPU_INT_STAT_3 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x44))
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#define IPU_INT_STAT_4 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x48))
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#define IPU_INT_STAT_5 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x4C))
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#define IPU_BRK_CTRL_1 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x50))
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#define IPU_BRK_CTRL_2 (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x54))
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#define IPU_BRK_STAT (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x58))
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#define IPU_DIAGB_CTRL (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x60))
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/* ATA */
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#define TIME_OFF (*(REG8_PTR_T)0x43F8C000)
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#define TIME_ON (*(REG8_PTR_T)0x43F8C001)
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#define TIME_1 (*(REG8_PTR_T)0x43F8C002)
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#define TIME_2W (*(REG8_PTR_T)0x43F8C003)
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#define TIME_2R (*(REG8_PTR_T)0x43F8C004)
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#define TIME_AX (*(REG8_PTR_T)0x43F8C005)
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#define TIME_PIO_RDX (*(REG8_PTR_T)0x43F8C00F)
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#define TIME_4 (*(REG8_PTR_T)0x43F8C007)
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#define TIME_9 (*(REG8_PTR_T)0x43F8C008)
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/* Timers */
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#define EPITCR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x00))
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#define EPITSR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x04))
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#define EPITLR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x08))
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#define EPITCMPR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x0C))
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#define EPITCNT1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x10))
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#define EPITCR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x00))
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#define EPITSR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x04))
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#define EPITLR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x08))
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#define EPITCMPR2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x0C))
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#define EPITCNT2 (*(REG32_PTR_T)(EPIT2_BASE_ADDR+0x10))
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/* GPIO */
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#define GPIO1_DR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x00))
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#define GPIO1_GDIR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x04))
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#define GPIO1_PSR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x08))
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#define GPIO1_ICR1 (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x0C))
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#define GPIO1_ICR2 (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x10))
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#define GPIO1_IMR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x14))
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#define GPIO1_ISR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x18))
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#define GPIO2_DR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x00))
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#define GPIO2_GDIR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x04))
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#define GPIO2_PSR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x08))
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#define GPIO2_ICR1 (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x0C))
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#define GPIO2_ICR2 (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x10))
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#define GPIO2_IMR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x14))
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#define GPIO2_ISR (*(REG32_PTR_T)(GPIO2_BASE_ADDR+0x18))
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#define GPIO3_DR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x00))
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#define GPIO3_GDIR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x04))
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#define GPIO3_PSR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x08))
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#define GPIO3_ICR1 (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x0C))
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#define GPIO3_ICR2 (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x10))
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#define GPIO3_IMR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x14))
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#define GPIO3_ISR (*(REG32_PTR_T)(GPIO3_BASE_ADDR+0x18))
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/* SPI */
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#define CSPI_RXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x00))
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#define CSPI_TXDATA1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x04))
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#define CSPI_CONREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x08))
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#define CSPI_INTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x0C))
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#define CSPI_DMAREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x10))
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#define CSPI_STATREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x14))
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#define CSPI_PERIODREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x18))
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#define CSPI_TESTREG1 (*(REG32_PTR_T)(CSPI1_BASE_ADDR+0x1C0))
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#define CSPI_RXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x00))
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#define CSPI_TXDATA2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x04))
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#define CSPI_CONREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x08))
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#define CSPI_INTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x0C))
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#define CSPI_DMAREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x10))
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#define CSPI_STATREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x14))
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#define CSPI_PERIODREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x18))
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#define CSPI_TESTREG2 (*(REG32_PTR_T)(CSPI2_BASE_ADDR+0x1C0))
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/* RTC */
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#define RTC_HOURMIN (*(REG32_PTR_T)(RTC_BASE_ADDR+0x00))
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#define RTC_SECONDS (*(REG32_PTR_T)(RTC_BASE_ADDR+0x04))
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#define RTC_ALRM_HM (*(REG32_PTR_T)(RTC_BASE_ADDR+0x08))
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#define RTC_ALRM_SEC (*(REG32_PTR_T)(RTC_BASE_ADDR+0x0C))
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#define RTC_CTL (*(REG32_PTR_T)(RTC_BASE_ADDR+0x10))
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#define RTC_ISR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x14))
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#define RTC_IENR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x18))
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#define RTC_STPWCH (*(REG32_PTR_T)(RTC_BASE_ADDR+0x1C))
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#define RTC_DAYR (*(REG32_PTR_T)(RTC_BASE_ADDR+0x20))
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#define RTC_DAYALARM (*(REG32_PTR_T)(RTC_BASE_ADDR+0x24))
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/* Keypad */
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#define KPP_KPCR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x0))
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#define KPP_KPSR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x2))
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#define KPP_KDDR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x4))
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#define KPP_KPDR (*(REG16_PTR_T)(KPP_BASE_ADDR+0x6))
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/* ROMPATCH and AVIC */
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#define ROMPATCH_BASE_ADDR 0x60000000
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/* Since AVIC vector registers are NOT used, we reserve some for various
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* purposes. Copied from Linux source code. */
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#define CHIP_REV_1_0 0x10
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#define CHIP_REV_2_0 0x20
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#define SYSTEM_REV_ID_REG (AVIC_BASE_ADDR + AVIC_VEC_1)
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#define SYSTEM_REV_ID_MAG 0xF00C
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/*
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* NAND, SDRAM, WEIM, M3IF, EMI controllers
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*/
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#define EXT_MEM_CTRL_BASE 0xB8000000
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#define NFC_BASE EXT_MEM_CTRL_BASE
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#define ESDCTL_BASE 0xB8001000
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#define WEIM_BASE_ADDR 0xB8002000
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#define WEIM_CTRL_CS0 (WEIM_BASE_ADDR+0x00)
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#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR+0x10)
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#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR+0x20)
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#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR+0x30)
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#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR+0x40)
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#define M3IF_BASE 0xB8003000
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#define PCMCIA_CTL_BASE 0xB8004000
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/*
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* Memory regions and CS
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*/
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#define IPU_MEM_BASE_ADDR 0x70000000
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#define CSD0_BASE_ADDR 0x80000000
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#define CSD1_BASE_ADDR 0x90000000
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#define CS0_BASE_ADDR 0xA0000000
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#define CS1_BASE_ADDR 0xA8000000
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#define CS2_BASE_ADDR 0xB0000000
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#define CS3_BASE_ADDR 0xB2000000
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#define CS4_BASE_ADDR 0xB4000000
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#define CS4_BASE_PSRAM 0xB5000000
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#define CS5_BASE_ADDR 0xB6000000
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#define PCMCIA_MEM_BASE_ADDR 0xC0000000
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#define INTERNAL_ROM_VA 0xF0000000
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/*
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* SDRAM
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*/
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#define RAM_BANK0_BASE SDRAM_BASE_ADDR
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/*
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* IRQ Controller Register Definitions.
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*/
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#define AVIC_BASE_ADDR 0x68000000
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#define INTCNTL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x00))
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#define NIMASK (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x04))
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#define INTENNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x08))
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#define INTDISNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x0C))
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#define INTENABLEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x10))
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#define INTENABLEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x14))
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#define INTTYPEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x18))
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#define INTTYPEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x1C))
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#define NIPRIORITY(n) (((REG32_PTR_T)(AVIC_BASE_ADDR+0x20))[n])
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#define NIPRIORITY7 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x20))
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#define NIPRIORITY6 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x24))
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#define NIPRIORITY5 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x28))
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#define NIPRIORITY4 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x2C))
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#define NIPRIORITY3 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x30))
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#define NIPRIORITY2 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x34))
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#define NIPRIORITY1 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x38))
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#define NIPRIORITY0 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x3C))
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#define NIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x40))
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#define FIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x44))
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#define INTSRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x48))
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#define INTSRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x4C))
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#define INTFRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x50))
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#define INTFRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x54))
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#define NIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x58))
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#define NIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x5C))
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#define FIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x60))
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#define FIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x64))
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#define VECTOR_BASE_ADDR (AVIC_BASE_ADDR+0x100)
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#define VECTOR(n) (((REG32_PTR_T)VECTOR_BASE_ADDR)[n])
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/* The vectors go all the way up to 63. 4 bytes for each */
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#define INTCNTL_ABFLAG (1 << 25)
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#define INTCNTL_ABFEN (1 << 24)
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#define INTCNTL_NIDIS (1 << 22)
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#define INTCNTL_FIDIS (1 << 21)
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#define INTCNTL_NIAD (1 << 20)
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#define INTCNTL_FIAD (1 << 19)
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#define INTCNTL_NM (1 << 18)
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/* L210 */
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#define L2CC_BASE_ADDR 0x30000000
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#define L2_CACHE_LINE_SIZE 32
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#define L2_CACHE_CTL_REG 0x100
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#define L2_CACHE_AUX_CTL_REG 0x104
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#define L2_CACHE_SYNC_REG 0x730
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#define L2_CACHE_INV_LINE_REG 0x770
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#define L2_CACHE_INV_WAY_REG 0x77C
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#define L2_CACHE_CLEAN_LINE_REG 0x7B0
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#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
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#define L2CC_CACHE_SYNC (*(REG32_PTR_T)(L2CC_BASE_ADDR+L2_CACHE_SYNC_REG))
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/* CCM */
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#define CLKCTL_CCMR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00))
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#define CLKCTL_PDR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04))
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#define CLKCTL_PDR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08))
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#define CLKCTL_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64))
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#define CLKCTL_RCSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C))
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#define CLKCTL_MPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10))
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#define CLKCTL_UPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14))
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#define CLKCTL_SPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x18))
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#define CLKCTL_COSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x1C))
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#define CLKCTL_CGR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x20))
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#define CLKCTL_CGR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24))
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#define CLKCTL_CGR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28))
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#define CLKCTL_WIMR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C))
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#define CLKCTL_PMCR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C))
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#define PLL_REF_CLK 26000000
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/* WEIM - CS0 */
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#define CSCRU 0x00
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#define CSCRL 0x04
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#define CSCRA 0x08
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/* ESDCTL */
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#define ESDCTL_ESDCTL0 0x00
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#define ESDCTL_ESDCFG0 0x04
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#define ESDCTL_ESDCTL1 0x08
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#define ESDCTL_ESDCFG1 0x0C
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#define ESDCTL_ESDMISC 0x10
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/* More UART 1 Register defines */
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#define URXD1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x00))
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#define UTXD1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x40))
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#define UCR1_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x80))
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#define UCR2_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x84))
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#define UCR3_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x88))
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#define UCR4_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x8C))
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#define UFCR1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x90))
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#define USR1_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x94))
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#define USR2_1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0x98))
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#define UTS1 (*(REG32_PTR_T)(UART1_BASE_ADDR+0xB4))
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/*
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* UART Control Register 0 Bit Fields.
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*/
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#define EUartUCR1_ADEN (1 << 15) // Auto detect interrupt
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#define EUartUCR1_ADBR (1 << 14) // Auto detect baud rate
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#define EUartUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable
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#define EUartUCR1_IDEN (1 << 12) // Idle condition interrupt
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#define EUartUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable
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#define EUartUCR1_RDMAEN (1 << 8) // Recv ready DMA enable
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#define EUartUCR1_IREN (1 << 7) // Infrared interface enable
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#define EUartUCR1_TXMPTYEN (1 << 6) // Transimitter empt interrupt enable
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#define EUartUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable
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#define EUartUCR1_SNDBRK (1 << 4) // Send break
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#define EUartUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable
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#define EUartUCR1_DOZE (1 << 1) // Doze
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#define EUartUCR1_UARTEN (1 << 0) // UART enabled
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#define EUartUCR2_ESCI (1 << 15) // Escape seq interrupt enable
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#define EUartUCR2_IRTS (1 << 14) // Ignore RTS pin
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#define EUartUCR2_CTSC (1 << 13) // CTS pin control
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#define EUartUCR2_CTS (1 << 12) // Clear to send
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#define EUartUCR2_ESCEN (1 << 11) // Escape enable
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#define EUartUCR2_PREN (1 << 8) // Parity enable
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#define EUartUCR2_PROE (1 << 7) // Parity odd/even
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#define EUartUCR2_STPB (1 << 6) // Stop
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#define EUartUCR2_WS (1 << 5) // Word size
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#define EUartUCR2_RTSEN (1 << 4) // Request to send interrupt enable
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#define EUartUCR2_ATEN (1 << 3) // Aging timer enable
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#define EUartUCR2_TXEN (1 << 2) // Transmitter enabled
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#define EUartUCR2_RXEN (1 << 1) // Receiver enabled
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#define EUartUCR2_SRST_ (1 << 0) // SW reset
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#define EUartUCR3_PARERREN (1 << 12) // Parity enable
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#define EUartUCR3_FRAERREN (1 << 11) // Frame error interrupt enable
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#define EUartUCR3_ADNIMP (1 << 7) // Autobaud detection not improved
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#define EUartUCR3_RXDSEN (1 << 6) // Receive status interrupt enable
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#define EUartUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable
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#define EUartUCR3_AWAKEN (1 << 4) // Async wake interrupt enable
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#define EUartUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected
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#define EUartUCR3_INVT (1 << 1) // Inverted Infrared transmission
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#define EUartUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable
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#define EUartUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars)
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#define EUartUCR4_INVR (1 << 9) // Inverted infrared reception
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#define EUartUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable
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#define EUartUCR4_WKEN (1 << 7) // Wake interrupt enable
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#define EUartUCR4_IRSC (1 << 5) // IR special case
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#define EUartUCR4_LPBYP (1 << 4) // Low power bypass
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#define EUartUCR4_TCEN (1 << 3) // Transmit complete interrupt enable
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#define EUartUCR4_BKEN (1 << 2) // Break condition interrupt enable
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#define EUartUCR4_OREN (1 << 1) // Receiver overrun interrupt enable
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#define EUartUCR4_DREN (1 << 0) // Recv data ready interrupt enable
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#define EUartUFCR_RXTL_SHF 0 // Receiver trigger level shift
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#define EUartUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div> 1)
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#define EUartUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div> 2)
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#define EUartUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3)
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#define EUartUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4)
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#define EUartUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5)
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#define EUartUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6)
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#define EUartUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7)
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#define EUartUFCR_TXTL_SHF 10 // Transmitter trigger level shift
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#define EUartUSR1_PARITYERR (1 << 15) // Parity error interrupt flag
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#define EUartUSR1_RTSS (1 << 14) // RTS pin status
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#define EUartUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag
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#define EUartUSR1_RTSD (1 << 12) // RTS delta
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#define EUartUSR1_ESCF (1 << 11) // Escape seq interrupt flag
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#define EUartUSR1_FRAMERR (1 << 10) // Frame error interrupt flag
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#define EUartUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag
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#define EUartUSR1_AGTIM (1 << 8) // Aging timeout interrupt status
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#define EUartUSR1_RXDS (1 << 6) // Receiver idle interrupt flag
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#define EUartUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag
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#define EUartUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag
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#define EUartUSR2_ADET (1 << 15) // Auto baud rate detect complete
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|
#define EUartUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty
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|
#define EUartUSR2_IDLE (1 << 12) // Idle condition
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|
#define EUartUSR2_ACST (1 << 11) // Autobaud counter stopped
|
|
#define EUartUSR2_IRINT (1 << 8) // Serial infrared interrupt flag
|
|
#define EUartUSR2_WAKE (1 << 7) // Wake
|
|
#define EUartUSR2_RTSF (1 << 4) // RTS edge interrupt flag
|
|
#define EUartUSR2_TXDC (1 << 3) // Transmitter complete
|
|
#define EUartUSR2_BRCD (1 << 2) // Break condition
|
|
#define EUartUSR2_ORE (1 << 1) // Overrun error
|
|
#define EUartUSR2_RDR (1 << 0) // Recv data ready
|
|
#define EUartUTS_FRCPERR (1 << 13) // Force parity error
|
|
#define EUartUTS_LOOP (1 << 12) // Loop tx and rx
|
|
#define EUartUTS_TXEMPTY (1 << 6) // TxFIFO empty
|
|
#define EUartUTS_RXEMPTY (1 << 5) // RxFIFO empty
|
|
#define EUartUTS_TXFULL (1 << 4) // TxFIFO full
|
|
#define EUartUTS_RXFULL (1 << 3) // RxFIFO full
|
|
#define EUartUTS_SOFTRST (1 << 0) // Software reset
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|
|
|
#define DelayTimerPresVal 3
|
|
|
|
#define L2CC_ENABLED
|
|
|
|
/* Assuming 26MHz input clock */
|
|
/* PD MFD MFI MFN */
|
|
#define MPCTL_PARAM_208 ((1 << 26) + (0 << 16) + (8 << 10) + (0 << 0))
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|
#define MPCTL_PARAM_399 ((0 << 26) + (51 << 16) + (7 << 10) + (35 << 0))
|
|
#define MPCTL_PARAM_532 ((0 << 26) + (51 << 16) + (10 << 10) + (12 << 0))
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|
|
|
/* UPCTL PD MFD MFI MFN */
|
|
#define UPCTL_PARAM_288 (((1-1) << 26) + ((13-1) << 16) + (5 << 10) + (7 << 0))
|
|
#define UPCTL_PARAM_240 (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
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|
|
|
/* PDR0 */
|
|
#define PDR0_208_104_52 0xFF870D48 /* ARM=208MHz, HCLK=104MHz, IPG=52MHz */
|
|
#define PDR0_399_66_66 0xFF872B28 /* ARM=399MHz, HCLK=IPG=66.5MHz */
|
|
#define PDR0_399_133_66 0xFF871650 /* ARM=399MHz, HCLK=133MHz, IPG=66.5MHz */
|
|
#define PDR0_532_133_66 0xFF871E58 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
|
|
#define PDR0_665_83_66 0xFF873D78 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
|
|
#define PDR0_665_133_66 0xFF872660 /* ARM=532MHz, HCLK=133MHz, IPG=66MHz */
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|
|
|
#define PBC_BASE CS4_BASE_ADDR /* Peripheral Bus Controller */
|
|
|
|
#define PBC_BSTAT2 0x2
|
|
#define PBC_BCTRL1 0x4
|
|
#define PBC_BCTRL1_CLR 0x6
|
|
#define PBC_BCTRL2 0x8
|
|
#define PBC_BCTRL2_CLR 0xA
|
|
#define PBC_BCTRL3 0xC
|
|
#define PBC_BCTRL3_CLR 0xE
|
|
#define PBC_BCTRL4 0x10
|
|
#define PBC_BCTRL4_CLR 0x12
|
|
#define PBC_BSTAT1 0x14
|
|
#define MX31EVB_CS_LAN_BASE (CS4_BASE_ADDR + 0x00020000 + 0x300)
|
|
#define MX31EVB_CS_UART_BASE (CS4_BASE_ADDR + 0x00010000)
|
|
|
|
#define REDBOOT_IMAGE_SIZE 0x40000
|
|
|
|
#define SDRAM_WORKAROUND_FULL_PAGE
|
|
|
|
#define ARMHIPG_208_52_52 /* ARM: 208MHz, HCLK=IPG=52MHz*/
|
|
#define ARMHIPG_52_52_52 /* ARM: 52MHz, HCLK=IPG=52MHz*/
|
|
#define ARMHIPG_399_66_66
|
|
#define ARMHIPG_399_133_66
|
|
|
|
/* MX31 EVB SDRAM is from 0x80000000, 64M */
|
|
#define SDRAM_BASE_ADDR CSD0_BASE_ADDR
|
|
#define SDRAM_SIZE 0x04000000
|
|
|
|
#define UART_WIDTH_32 /* internal UART is 32bit access only */
|
|
#define EXT_UART_x16
|
|
|
|
#define UART_WIDTH_32 /* internal UART is 32bit access only */
|
|
|
|
#define FLASH_BURST_MODE_ENABLE 1
|
|
#define SDRAM_COMPARE_CONST1 0x55555555
|
|
#define SDRAM_COMPARE_CONST2 0xAAAAAAAA
|
|
#define UART_FIFO_CTRL 0x881
|
|
#define TIMEOUT 1000
|
|
#define writel(v,a) (*(REG32_PTR_T)(a) = (v))
|
|
#define readl(a) (*(REG32_PTR_T)(a))
|
|
#define writew(v,a) (*(REG16_PTR_T)(a) = (v))
|
|
#define readw(a) (*(REG16_PTR_T)(a))
|