forked from len0rd/rockbox
56340f4cd0
This is needed on the jz4760b because if some data is loaded to DRAM, then it
is cached and a disaster lurks if dcaches/icache are not flushed. Targets that
needs this must define CONFIG_FLUSH_CACHES in target-config.h and implement
target_flush_caches(). Currently MIPS has some generic code for mips32r1 that
requires to define {D,I}CACHE_SIZE and {D,I}CACHE_LINE_SIZE in target-config.h
Change-Id: I5a3fc085de9445d8c8a2eb61ae4e2dc9bb6b4e8e
52 lines
1.9 KiB
C
52 lines
1.9 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2013 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __TARGET_H__
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#define __TARGET_H__
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#include "protocol.h"
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/* do target specific init */
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void target_init(void);
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/* get descriptor, set buffer to NULL on error */
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void target_get_desc(int desc, void **buffer);
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/* pack all descriptors for config desc */
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void target_get_config_desc(void *buffer, int *size);
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/* Wait a very short time (us<=1000) */
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void target_udelay(int us);
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/* Wait for a short time (ms <= 1000) */
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void target_mdelay(int ms);
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/* Read a n-bit word atomically */
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uint8_t target_read8(const void *addr);
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uint16_t target_read16(const void *addr);
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uint32_t target_read32(const void *addr);
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/* Write a n-bit word atomically */
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void target_write8(void *addr, uint8_t val);
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void target_write16(void *addr, uint16_t val);
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void target_write32(void *addr, uint32_t val);
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#ifdef CONFIG_FLUSH_CACHES
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/* flush cache: commit dcache and invalidate icache */
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void target_flush_caches(void);
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#endif
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/* mandatory for all targets */
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extern struct hwstub_target_desc_t target_descriptor;
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#endif /* __TARGET_H__ */
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