forked from len0rd/rockbox
This is needed on the jz4760b because if some data is loaded to DRAM, then it
is cached and a disaster lurks if dcaches/icache are not flushed. Targets that
needs this must define CONFIG_FLUSH_CACHES in target-config.h and implement
target_flush_caches(). Currently MIPS has some generic code for mips32r1 that
requires to define {D,I}CACHE_SIZE and {D,I}CACHE_LINE_SIZE in target-config.h
Change-Id: I5a3fc085de9445d8c8a2eb61ae4e2dc9bb6b4e8e
|
||
|---|---|---|
| .. | ||
| crt0.S | ||
| hwstub.lds | ||
| jz4760b.h | ||
| Makefile | ||
| mips-archdefs.h | ||
| mips.h | ||
| target-config.h | ||
| target.c | ||
| usb_drv_jz4760b.c | ||