Aidan MacDonald 8cb4c18310 Really fix the MIPS cache bug this time ... In fixing the original bug I tried to optimize discard_dcache_range() to minimize writeback and inadvertently introduced a second bug, which typically ends in a TLB refill panic. It occurs only if the range fits within one cache line, and when both the start and end of the range are not aligned to a cache line. This causes ptr to be incremented and end to be decremented, so ptr > end, and the loop can't terminate. Change-Id: Ibaac072f1369268d3327d534ad08ef9dcee3db65		2021-03-03 23:57:08 +00:00
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arm	Disable UDMA 2 on iPod4G target	2021-02-27 14:38:49 +00:00
coldfire	h300, Others Bugfix Bootloader backlight_init()	2020-11-13 18:08:01 +00:00
hosted	erosq: Enable HAVE_SCROLLWHEEL for saner scroll wheel handling	2020-12-16 14:54:11 -05:00
mips	Really fix the MIPS cache bug this time	2021-03-03 23:57:08 +00:00