forked from len0rd/rockbox
c36d7768c5
Max allowed size: 120860 Old thumb build: 128494 New thumb build: 118514 (fits!) Disabled: Logo; alpha blending capabilities for bitmaps; Arm stack unwinder (backtrace); Related forum discussion: https://forums.rockbox.org/index.php/topic,54768.0.html Fixes FS#12380 Change-Id: I978720d795cb0ef5169103e467cf8386c21d8e93
367 lines
11 KiB
C
367 lines
11 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Alan Korr
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __SYSTEM_H__
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#define __SYSTEM_H__
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#include <stdbool.h>
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#include <stdint.h>
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#include "cpu.h"
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#include "gcc_extensions.h" /* for LIKELY/UNLIKELY */
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extern void system_reboot (void);
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/* Called from any UIE handler and panicf - wait for a key and return
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* to reboot system. */
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extern void system_exception_wait(void);
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#if NUM_CORES == 1
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extern void system_init(void) INIT_ATTR;
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#else
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/* TODO: probably safe to use INIT_ATTR on multicore but this needs checking */
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extern void system_init(void);
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#endif
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extern long cpu_frequency;
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struct flash_header {
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uint32_t magic;
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uint32_t length;
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char version[32];
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};
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bool detect_flashed_romimage(void);
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bool detect_flashed_ramimage(void);
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bool detect_original_firmware(void);
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#if defined(HAVE_ADJUSTABLE_CPU_FREQ) \
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&& defined(ROCKBOX_HAS_LOGF) && (NUM_CORES == 1)
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#define CPU_BOOST_LOGGING
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#endif
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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#define FREQ cpu_frequency
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void set_cpu_frequency(long frequency);
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#ifdef CPU_BOOST_LOGGING
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char * cpu_boost_log_getlog_first(void);
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char * cpu_boost_log_getlog_next(void);
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int cpu_boost_log_getcount(void);
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void cpu_boost_(bool on_off, char* location, int line);
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#else
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void cpu_boost(bool on_off);
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#endif
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void cpu_idle_mode(bool on_off);
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int get_cpu_boost_counter(void);
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#else /* ndef HAVE_ADJUSTABLE_CPU_FREQ */
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#ifndef FREQ
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#define FREQ CPU_FREQ
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#endif
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#define set_cpu_frequency(frequency)
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#define cpu_boost(on_off)
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#define cpu_boost_id(on_off, id)
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#define cpu_idle_mode(on_off)
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#define get_cpu_boost_counter()
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#define get_cpu_boost_tracker()
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#endif /* HAVE_ADJUSTABLE_CPU_FREQ */
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#ifdef CPU_BOOST_LOGGING
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#define cpu_boost(on_off) cpu_boost_(on_off,__FILE__, __LINE__)
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#endif
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#define BAUDRATE 9600
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/* wrap-safe macros for tick comparison */
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#define TIME_AFTER(a,b) ((long)(b) - (long)(a) < 0)
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#define TIME_BEFORE(a,b) TIME_AFTER(b,a)
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#ifndef NULL
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#define NULL ((void*)0)
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#endif
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#ifndef MIN
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#define MIN(a, b) (((a)<(b))?(a):(b))
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#endif
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#ifndef MAX
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#define MAX(a, b) (((a)>(b))?(a):(b))
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#endif
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#ifndef SGN
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#define SGN(a) \
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({ typeof (a) ___a = (a); (___a > 0) - (___a < 0); })
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#endif
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/* return number of elements in array a */
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#define ARRAYLEN(a) (sizeof(a)/sizeof((a)[0]))
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/* is the given pointer "p" inside the said bounds of array "a"? */
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#define PTR_IN_ARRAY(a, p, numelem) \
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((uintptr_t)(p) - (uintptr_t)(a) < (uintptr_t)(numelem)*sizeof ((a)[0]))
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/* return p incremented by specified number of bytes */
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#define SKIPBYTES(p, count) ((typeof (p))((char *)(p) + (count)))
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#define P2_M1(p2) ((1 << (p2))-1)
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/* align up or down to nearest 2^p2 */
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#define ALIGN_DOWN_P2(n, p2) ((n) & ~P2_M1(p2))
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#define ALIGN_UP_P2(n, p2) ALIGN_DOWN_P2((n) + P2_M1(p2),p2)
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/* align up or down to nearest integer multiple of a */
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#define ALIGN_DOWN(n, a) ((typeof(n))((uintptr_t)(n)/(a)*(a)))
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#define ALIGN_UP(n, a) ALIGN_DOWN((n)+((a)-1),a)
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/* align start and end of buffer to nearest integer multiple of a */
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#define ALIGN_BUFFER(ptr, size, align) \
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({ \
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size_t __sz = (size); \
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size_t __ali = (align); \
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uintptr_t __a1 = (uintptr_t)(ptr); \
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uintptr_t __a2 = __a1 + __sz; \
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__a1 = ALIGN_UP(__a1, __ali); \
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__a2 = ALIGN_DOWN(__a2, __ali); \
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(ptr) = (typeof (ptr))__a1; \
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(size) = __a2 > __a1 ? __a2 - __a1 : 0; \
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})
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#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0)
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#define PTR_ADD(ptr, x) ((typeof(ptr))((char*)(ptr) + (x)))
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#define PTR_SUB(ptr, x) ((typeof(ptr))((char*)(ptr) - (x)))
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#ifndef alignof
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#define alignof __alignof__
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#endif
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/* Get the byte offset of a type's member */
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#ifndef offsetof
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#define offsetof(type, member) __builtin_offsetof(type, member)
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#endif
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/* Get the containing item of *ptr in type */
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#ifndef container_of
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#define container_of(ptr, type, member) ({ \
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const typeof (((type *)0)->member) *__mptr = (ptr); \
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(type *)((void *)(__mptr) - offsetof(type, member)); })
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#endif
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/* returns index of first set bit or 32 if no bits are set */
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#if defined(CPU_ARM) && ARM_ARCH >= 5 && !defined(__thumb__)
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static inline int find_first_set_bit(uint32_t val)
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{ return LIKELY(val) ? __builtin_ctz(val) : 32; }
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#else
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int find_first_set_bit(uint32_t val);
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#endif
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static inline __attribute__((always_inline))
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uint32_t isolate_first_bit(uint32_t val)
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{ return val & -val; }
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/* Functions to set and clear register or variable bits atomically;
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* return value is the previous value of *addr */
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uint16_t bitmod16(volatile uint16_t *addr, uint16_t bits, uint16_t mask);
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uint16_t bitset16(volatile uint16_t *addr, uint16_t mask);
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uint16_t bitclr16(volatile uint16_t *addr, uint16_t mask);
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uint32_t bitmod32(volatile uint32_t *addr, uint32_t bits, uint32_t mask);
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uint32_t bitset32(volatile uint32_t *addr, uint32_t mask);
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uint32_t bitclr32(volatile uint32_t *addr, uint32_t mask);
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/* gcc 3.4 changed the format of the constraints */
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#if (__GNUC__ >= 3) && (__GNUC_MINOR__ > 3) || (__GNUC__ >= 4)
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#define I_CONSTRAINT "I08"
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#else
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#define I_CONSTRAINT "I"
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#endif
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/* Utilize the user break controller to catch invalid memory accesses. */
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int system_memory_guard(int newmode);
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enum {
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MEMGUARD_KEEP = -1, /* don't change the mode; for reading */
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MEMGUARD_NONE = 0, /* catch nothing */
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MEMGUARD_FLASH_WRITES, /* catch writes to area 02 (flash ROM) */
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MEMGUARD_ZERO_AREA, /* catch all accesses to areas 00 and 01 */
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MAXMEMGUARD
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};
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#if !defined(SIMULATOR) && !defined(__PCTOOL__)
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#include "system-target.h"
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#elif defined(HAVE_SDL) /* SDL build */
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#include "system-sdl.h"
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#ifdef SIMULATOR
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#include "system-sim.h"
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#endif
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#elif defined(__PCTOOL__)
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#include "system-hosted.h"
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#endif
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#include "bitswap.h"
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#include "rbendian.h"
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#ifndef ASSERT_CPU_MODE
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/* Very useful to have defined properly for your architecture */
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#define ASSERT_CPU_MODE(mode, rstatus...) \
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({ (void)(mode); rstatus; })
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#endif
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#ifndef CPU_MODE_THREAD_CONTEXT
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#define CPU_MODE_THREAD_CONTEXT 0
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#endif
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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#ifndef CPU_BOOST_LOCK_DEFINED
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#define CPU_BOOST_LOCK_DEFINED
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/* Compatibility defauls */
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static inline bool cpu_boost_lock(void)
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{ return true; }
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static inline void cpu_boost_unlock(void)
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{ }
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#endif /* CPU_BOOST_LOCK */
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#endif /* HAVE_ADJUSTABLE_CPU_FREQ */
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#ifndef BIT_N
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#define BIT_N(n) (1U << (n))
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#endif
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#ifndef MASK_N
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/* Make a mask of n contiguous bits, shifted left by 'shift' */
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#define MASK_N(type, n, shift) \
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((type)((((type)1 << (n)) - (type)1) << (shift)))
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#endif
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/* Declare this as HIGHEST_IRQ_LEVEL if they don't differ */
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#ifndef DISABLE_INTERRUPTS
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#define DISABLE_INTERRUPTS HIGHEST_IRQ_LEVEL
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#endif
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/* Define this, if the CPU may take advantage of cache aligment. Is enabled
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* for all ARM CPUs. */
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#ifdef CPU_ARM
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#define HAVE_CPU_CACHE_ALIGN
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#define MIN_STACK_ALIGN 8
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#endif
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#ifdef CPU_MIPS
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#define HAVE_CPU_CACHE_ALIGN
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#endif
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/* Define this if target has support for generating backtraces */
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#if defined(CPU_ARM) || \
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(defined(CPU_MIPS) && (CONFIG_PLATFORM & PLATFORM_NATIVE))
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#ifndef DISABLE_BACKTRACE
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#define HAVE_RB_BACKTRACE
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#endif
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#endif
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#ifndef MIN_STACK_ALIGN
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#define MIN_STACK_ALIGN (sizeof (uintptr_t))
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#endif
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/* Calculate CACHEALIGN_SIZE from CACHEALIGN_BITS */
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#ifdef CACHEALIGN_SIZE
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/* undefine, if defined. always calculate from CACHEALIGN_BITS */
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#undef CACHEALIGN_SIZE
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#endif
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#ifdef CACHEALIGN_BITS
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/* CACHEALIGN_SIZE = 2 ^ CACHEALIGN_BITS */
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#define CACHEALIGN_SIZE (1u << CACHEALIGN_BITS)
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#else
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/* FIXME: set to maximum known cache alignment of supported CPUs */
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#define CACHEALIGN_BITS 5
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#define CACHEALIGN_SIZE 32
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#endif
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#ifdef HAVE_CPU_CACHE_ALIGN
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/* Cache alignment attributes and sizes are enabled */
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#define CACHEALIGN_ATTR __attribute__((aligned(CACHEALIGN_SIZE)))
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/* Aligns x up to a CACHEALIGN_SIZE boundary */
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#define CACHEALIGN_UP(x) \
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((typeof (x))ALIGN_UP_P2((uintptr_t)(x), CACHEALIGN_BITS))
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/* Aligns x down to a CACHEALIGN_SIZE boundary */
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#define CACHEALIGN_DOWN(x) \
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((typeof (x))ALIGN_DOWN_P2((uintptr_t)(x), CACHEALIGN_BITS))
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/* Aligns at least to the greater of size x or CACHEALIGN_SIZE */
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#define CACHEALIGN_AT_LEAST_ATTR(x) \
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__attribute__((aligned(CACHEALIGN_UP(x))))
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/* Aligns a buffer pointer and size to proper boundaries */
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#define CACHEALIGN_BUFFER(start, size) \
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ALIGN_BUFFER((start), (size), CACHEALIGN_SIZE)
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#else
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/* Cache alignment attributes and sizes are not enabled */
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#define CACHEALIGN_ATTR
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#define CACHEALIGN_AT_LEAST_ATTR(x) __attribute__((aligned(x)))
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#define CACHEALIGN_UP(x) (x)
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#define CACHEALIGN_DOWN(x) (x)
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/* Make no adjustments */
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#define CACHEALIGN_BUFFER(start, size)
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#endif
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/* Define MEM_ALIGN_ATTR which may be used to align e.g. buffers for faster
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* access. */
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#if defined(HAVE_CPU_CACHE_ALIGN)
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/* Align to a cache line. */
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#define MEM_ALIGN_ATTR CACHEALIGN_ATTR
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#define MEM_ALIGN_SIZE CACHEALIGN_SIZE
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#elif defined(CPU_COLDFIRE)
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/* Use fixed alignment of 16 bytes. Speed up only for 'movem' in DRAM. */
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#define MEM_ALIGN_ATTR __attribute__((aligned(16)))
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#define MEM_ALIGN_SIZE 16
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#else
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/* Align pointer size */
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#define MEM_ALIGN_ATTR __attribute__((aligned(sizeof(intptr_t))))
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#define MEM_ALIGN_SIZE sizeof(intptr_t)
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#endif
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#define MEM_ALIGN_UP(x) \
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((typeof (x))ALIGN_UP((uintptr_t)(x), MEM_ALIGN_SIZE))
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#define MEM_ALIGN_DOWN(x) \
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((typeof (x))ALIGN_DOWN((uintptr_t)(x), MEM_ALIGN_SIZE))
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#ifdef STORAGE_WANTS_ALIGN
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#define STORAGE_ALIGN_ATTR __attribute__((aligned(CACHEALIGN_SIZE)))
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#define STORAGE_ALIGN_DOWN(x) \
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((typeof (x))ALIGN_DOWN_P2((uintptr_t)(x), CACHEALIGN_BITS))
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/* Pad a size so the buffer can be aligned later */
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#define STORAGE_PAD(x) ((x) + CACHEALIGN_SIZE - 1)
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/* Number of bytes in the last cacheline assuming buffer of size x is aligned */
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#define STORAGE_OVERLAP(x) ((x) & (CACHEALIGN_SIZE - 1))
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#define STORAGE_ALIGN_BUFFER(start, size) \
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ALIGN_BUFFER((start), (size), CACHEALIGN_SIZE)
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#else
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#define STORAGE_ALIGN_ATTR
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#define STORAGE_ALIGN_DOWN(x) (x)
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#define STORAGE_PAD(x) (x)
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#define STORAGE_OVERLAP(x) 0
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#define STORAGE_ALIGN_BUFFER(start, size)
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#endif
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/* Double-cast to avoid 'dereferencing type-punned pointer will
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* break strict aliasing rules' B.S. */
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#define PUN_PTR(type, p) ((type)(intptr_t)(p))
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#ifndef SIMULATOR
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bool dbg_ports(void);
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#endif
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#if (CONFIG_PLATFORM & PLATFORM_NATIVE) || defined(SONY_NWZ_LINUX) || defined(HIBY_LINUX) || defined(FIIO_M3K_LINUX)
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bool dbg_hw_info(void);
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#endif
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#endif /* __SYSTEM_H__ */
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