forked from len0rd/rockbox
7552542288
This test software setups timer T0 periodic interrupt. In ISR it changes backlight level. The interrupt handler does not support nesting and the whole ISR is run in interrupt context. Exceptions are not handled yet. Change-Id: Idc5d622991c7257b4577448d8be08ddd1c24c745
91 lines
1.8 KiB
ArmAsm
91 lines
1.8 KiB
ArmAsm
#include "mips.h"
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/* s0-s7 not saved as this are callee saved registers
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* CO_STATUS is not saved as nested interrupts are not supported
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*
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* Separate irqstack is used for context save and irq processing
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* k0 holds the address of the top of this stack and k1 is used
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* to hold original sp value. Since we do not support nesting
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* there is nothing to warry about
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*/
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.extern irqvector
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.global irq_handler
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.set mips32r2
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.set noreorder
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.set noat
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.section .irq_vector,"ax",%progbits
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irq_handler:
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move k1, sp
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move sp, k0
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addiu sp, sp, -84
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/* context save */
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sw AT, 0(sp)
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sw v0, 4(sp)
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sw v1, 8(sp)
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sw a0, 12(sp)
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sw a1, 16(sp)
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sw a2, 20(sp)
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sw a3, 24(sp)
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sw t0, 28(sp)
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sw t1, 32(sp)
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sw t2, 36(sp)
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sw t3, 40(sp)
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sw t4, 44(sp)
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sw t5, 48(sp)
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sw t6, 52(sp)
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sw t7, 56(sp)
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sw t8, 60(sp)
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sw t9, 64(sp)
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sw fp, 68(sp)
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sw ra, 72(sp)
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mfhi t0
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mflo t1
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sw t0, 76(sp)
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sw t1, 80(sp)
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/* handle interrupt */
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lui t0, 0xb002 /* INTC base */
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lw t1, 0(t0) /* INTC_PD */
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clz t1, t1
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sll t0, t1, 2 /* offset */
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la t1, irqvector
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addu t0, t1, t0 /* irq handler pointer address */
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lw t0, 0(t0)
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jalr t0 /* call handler function */
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nop
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/* context restore */
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lw t0, 76(sp)
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lw t1, 80(sp)
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mthi t0
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mtlo t1
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lw AT, 0(sp)
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lw v0, 4(sp)
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lw v1, 8(sp)
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lw a0, 12(sp)
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lw a1, 16(sp)
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lw a2, 20(sp)
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lw a3, 24(sp)
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lw t0, 28(sp)
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lw t1, 32(sp)
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lw t2, 36(sp)
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lw t3, 40(sp)
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lw t4, 44(sp)
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lw t5, 48(sp)
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lw t6, 52(sp)
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lw t7, 56(sp)
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lw t8, 60(sp)
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lw t9, 64(sp)
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lw fp, 68(sp)
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lw ra, 72(sp)
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addiu sp, sp, 88
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move sp, k1
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eret
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.set reorder
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.set at
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