forked from len0rd/rockbox
58b849c451
Some drivers set tm_wday just fine and do not need it coerced to be correct. Others set tm_yday, so don't overwrite what the driver sets; just zero it inside if it can't fill the field. Move calls to set_day_of_week() to the sorts of drivers that presumably required the hammer (FS#11814) in get_time() where the weekday isn't locked to the date. Change-Id: Idd0ded6bfc9d9f48fcc1a6074068164c42fcf24a
314 lines
8.1 KiB
C
314 lines
8.1 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* adopted for HD300 by Marcin Bukat
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* Copyright (C) 2009 by Bertrik Sikken
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* Copyright (C) 2008 by Robert Kukla
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "rtc.h"
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#include "i2c-coldfire.h"
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#include "timefuncs.h"
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/* Driver for the Seiko S35380A real-time clock chip with i2c interface
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This driver was derived from rtc_s3539a.c and adapted for the MPIO HD300
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*/
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#define RTC_ADDR 0x60
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#define STATUS_REG1 0
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#define STATUS_REG2 1
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#define REALTIME_DATA1 2
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#define REALTIME_DATA2 3
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#define INT1_REG 4
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#define INT2_REG 5
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#define CLOCK_CORR_REG 6
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#define FREE_REG 7
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/* STATUS_REG1 flags */
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#define STATUS_REG1_POC 0x80
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#define STATUS_REG1_BLD 0x40
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#define STATUS_REG1_INT2 0x20
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#define STATUS_REG1_INT1 0x10
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#define STATUS_REG1_SC1 0x08
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#define STATUS_REG1_SC0 0x04
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#define STATUS_REG1_H1224 0x02
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#define STATUS_REG1_RESET 0x01
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/* STATUS_REG2 flags */
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#define STATUS_REG2_TEST 0x80
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#define STATUS_REG2_INT2AE 0x40
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#define STATUS_REG2_INT2ME 0x20
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#define STATUS_REG2_INT2FE 0x10
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#define STATUS_REG2_32kE 0x08
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#define STATUS_REG2_INT1AE 0x04
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#define STATUS_REG2_INT1ME 0x02
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#define STATUS_REG2_INT1FE 0x01
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/* REALTIME_DATA register bytes */
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#define TIME_YEAR 0
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#define TIME_MONTH 1
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#define TIME_DAY 2
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#define TIME_WEEKDAY 3
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#define TIME_HOUR 4
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#define TIME_MINUTE 5
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#define TIME_SECOND 6
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#define TIME_REG_SIZE 7
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/* INT1, INT2 register bytes */
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#define ALARM_WEEKDAY 0
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#define ALARM_HOUR 1
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#define ALARM_MINUTE 2
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#define ALARM_REG_SIZE 3
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/* INT1, INT2 register bits */
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#define A1WE 0x80
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#define A1HE 0x80
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#define A1mE 0x80
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#define A2WE 0x80
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#define A2HE 0x80
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#define A2mE 0x80
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#define AMPM 0x40
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static bool int_flag;
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/* s35380a chip has reversed bits order in byte
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* This is little helper function to deal with
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*/
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static void reverse_bits(unsigned char* v, int size)
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{
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static const unsigned char flipnibble[] =
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{0x00, 0x08, 0x04, 0x0C, 0x02, 0x0A, 0x06, 0x0E,
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0x01, 0x09, 0x05, 0x0D, 0x03, 0x0B, 0x07, 0x0F};
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int i;
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for (i = 0; i < size; i++) {
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v[i] = (flipnibble[v[i] & 0x0F] << 4) |
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flipnibble[(v[i] >> 4) & 0x0F];
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}
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}
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/* Read 'size' bytes from RTC 'reg' and put data in 'buf'
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* bits are reversed in data bytes afterwards so they appear in regular order
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* return i2c transfer code
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*/
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static int rtc_read(unsigned char reg, unsigned char *buf, int size)
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{
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int rc;
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rc = i2c_read(I2C_IFACE_1, RTC_ADDR|(reg<<1), buf, size);
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reverse_bits(buf, size);
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return rc;
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}
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/* Write 'size' bytes to RTC 'reg' and put data in 'buf'
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* bits are reversed in data bytes prior to sending them to RTC
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* return i2c transfer code
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*/
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static int rtc_write(unsigned char reg, unsigned char *buf, int size)
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{
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int rc;
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reverse_bits(buf, size);
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rc = i2c_write(I2C_IFACE_1, RTC_ADDR|(reg<<1), buf, size);
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return rc;
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}
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/* Reset RTC by writing '1' to RESET bit in STATUS_REG1 */
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static inline void rtc_reset(void)
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{
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unsigned char reg = STATUS_REG1_RESET;
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rtc_write(STATUS_REG1, ®, 1);
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}
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/* Initialize RTC (according to scheme outlined in datasheet).
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* Configure chip to 24h time format.
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*/
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void rtc_init(void)
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{
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unsigned char reg;
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static bool initialized = false;
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if ( initialized )
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return;
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rtc_read(STATUS_REG1, ®, 1);
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/* cache INT1, INT2 flags as reading the register seem to clear
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* this bits (which is not described in datasheet)
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*/
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int_flag = ((reg & STATUS_REG1_INT1) || (reg & STATUS_REG1_INT2));
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/* test POC and BLD flags */
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if ( (reg & STATUS_REG1_POC) || (reg & STATUS_REG1_BLD))
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rtc_reset();
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rtc_read(STATUS_REG2, ®, 1);
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/* test TEST flag */
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if ( reg & STATUS_REG2_TEST )
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rtc_reset();
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/* setup 24h time format */
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reg = STATUS_REG1_H1224;
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rtc_write(STATUS_REG1, ®, 1);
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initialized = true;
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}
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/* Read realtime data register */
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int rtc_read_datetime(struct tm *tm)
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{
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unsigned char buf[TIME_REG_SIZE];
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unsigned int i;
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int ret;
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ret = rtc_read(REALTIME_DATA1, buf, sizeof(buf));
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buf[TIME_HOUR] &= 0x3f; /* mask out p.m. flag */
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for (i = 0; i < sizeof(buf); i++)
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buf[i] = BCD2DEC(buf[i]);
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tm->tm_sec = buf[TIME_SECOND];
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tm->tm_min = buf[TIME_MINUTE];
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tm->tm_hour = buf[TIME_HOUR];
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tm->tm_mday = buf[TIME_DAY];
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tm->tm_mon = buf[TIME_MONTH] - 1;
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tm->tm_year = buf[TIME_YEAR] + 100;
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tm->tm_yday = 0; /* Not implemented for now */
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set_day_of_week(tm);
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return ret;
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}
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/* Write to realtime data register */
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int rtc_write_datetime(const struct tm *tm)
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{
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unsigned char buf[TIME_REG_SIZE];
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unsigned int i;
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int ret;
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buf[TIME_SECOND] = tm->tm_sec;
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buf[TIME_MINUTE] = tm->tm_min;
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buf[TIME_HOUR] = tm->tm_hour;
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buf[TIME_WEEKDAY] = tm->tm_wday;
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buf[TIME_DAY] = tm->tm_mday;
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buf[TIME_MONTH] = tm->tm_mon + 1;
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buf[TIME_YEAR] = tm->tm_year - 100;
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for (i = 0; i < sizeof(buf); i++)
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buf[i] = DEC2BCD(buf[i]);
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ret = rtc_write(REALTIME_DATA1, buf, sizeof(buf));
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return ret;
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}
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#ifdef HAVE_RTC_ALARM
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/* Set alarm (INT1) data register */
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void rtc_set_alarm(int h, int m)
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{
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unsigned char buf[ALARM_REG_SIZE];
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/* INT1 register can be accessed only when IN1AE flag is set */
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rtc_enable_alarm(true);
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/* A1mE, A1HE - validity flags */
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buf[ALARM_MINUTE] = DEC2BCD(m) | A1mE;
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buf[ALARM_HOUR] = DEC2BCD(h) | A1HE;
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buf[ALARM_WEEKDAY] = 0;
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/* AM/PM flag has to be set properly regardles of
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* time format used (H1224 flag in STATUS_REG1)
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* this is not described in datasheet for s35380a
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* but is somehow described in datasheet for s35390a
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*/
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if ( h >= 12 )
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buf[ALARM_HOUR] |= AMPM;
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rtc_write(INT1_REG, buf, sizeof(buf));
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}
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/* Read alarm (INT1) data register */
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void rtc_get_alarm(int *h, int *m)
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{
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unsigned char buf[ALARM_REG_SIZE];
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/* INT1 alarm register can be accessed only when INT1AE is set */
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rtc_enable_alarm(true);
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/* read the content of INT1 register */
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rtc_read(INT1_REG, buf, sizeof(buf));
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*h = BCD2DEC(buf[ALARM_HOUR] & 0x3f); /* mask out A1HE and PM/AM bits */
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*m = BCD2DEC(buf[ALARM_MINUTE] & 0x7f); /* mask out A1mE bit */
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/* Disable alarm - this is not strictly needed in rockbox
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* as after rtc_get_alarm() rtc_set_alarm() or rtc_enable_alarm(false)
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* are called. I just found this weird that simple reading register
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* changes alarm settings.
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*/
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rtc_enable_alarm(false);
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}
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/* Check if we just triggered alarm.
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* We check both INT1 and INT2. Rockbox uses only INT1 but
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* OF in MPIO HD300 uses both
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*/
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bool rtc_check_alarm_flag(void)
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{
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unsigned char reg;
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rtc_read(STATUS_REG1, ®, 1);
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return ((reg & STATUS_REG1_INT1) || (reg & STATUS_REG1_INT2));
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}
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/* Enable/disable alarm function */
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void rtc_enable_alarm(bool enable)
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{
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unsigned char reg = 0;
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if (enable)
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reg = STATUS_REG2_INT1AE;
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rtc_write(STATUS_REG2, ®, 1);
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}
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/* Return true if wakeup is due to RTC alarm */
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bool rtc_check_alarm_started(bool release_alarm)
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{
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static bool run_before;
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bool rc;
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if (run_before)
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{
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rc = int_flag;
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int_flag &= ~release_alarm;
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}
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else
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{
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rc = int_flag;
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run_before = true;
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}
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return rc;
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}
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#endif
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