forked from len0rd/rockbox
4d3190f416
Cortex-M processors don't have an MMU, but can still have caches that need software management, so on those platforms we don't want to include the MMU related functions. While here, remove an outdated section of a comment referring to deprecated cache maintenance functions which no longer exist. Change-Id: I6f0fe694560bdee25ed7c69a846bf46e3e544cb1
73 lines
2.5 KiB
C
73 lines
2.5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by Greg White
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef SYSTEM_TARGET_H
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#define SYSTEM_TARGET_H
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#include "system-arm.h"
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#include "mmu-arm.h"
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#include "cpucache-arm.h"
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/* NB: These values must match the register settings in s3c2440/crt0.S */
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#ifdef GIGABEAT_F
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/* MPLLCON = 0x000C9042, 16.9344 MHz refclk, therefore:
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* MPLL = 294940800 = 2*(201 + 8)*16934400 / ((4 + 2) * 2^2) */
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#define CPUFREQ_DEFAULT 98313600
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#define CPUFREQ_NORMAL 98313600
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#define CPUFREQ_MAX 294940800
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/* Uses 1:3:6 */
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#define FCLK CPUFREQ_MAX
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#define HCLK (FCLK/3) /* = 98,313,600 */
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#define PCLK (HCLK/2) /* = 49,156,800 */
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#ifdef BOOTLOADER
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/* All addresses within rockbox are in IRAM in the bootloader so
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are therefore uncached */
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#define UNCACHED_ADDR(a) (a)
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#else /* !BOOTLOADER */
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#define UNCACHED_BASE_ADDR 0x30000000
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#define UNCACHED_ADDR(a) ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR ))
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#endif /* BOOTLOADER */
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#elif defined(MINI2440)
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/* Uses 1:4:8 */
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#define FCLK 406000000
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#define HCLK (FCLK/4) /* = 101,250,000 */
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#define PCLK (HCLK/2) /* = 50,625,000 */
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#define CPUFREQ_DEFAULT FCLK /* 406 MHz */
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#define CPUFREQ_NORMAL (FCLK/4)/* 101.25 MHz */
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#define CPUFREQ_MAX FCLK /* 406 MHz */
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#define UNCACHED_BASE_ADDR 0x30000000
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#define UNCACHED_ADDR(a) ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR ))
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#else
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#error Unknown target
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#endif
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void system_prepare_fw_start(void);
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void tick_stop(void);
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#endif /* SYSTEM_TARGET_H */
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