forked from len0rd/rockbox
4d3190f416
Cortex-M processors don't have an MMU, but can still have caches that need software management, so on those platforms we don't want to include the MMU related functions. While here, remove an outdated section of a comment referring to deprecated cache maintenance functions which no longer exist. Change-Id: I6f0fe694560bdee25ed7c69a846bf46e3e544cb1
34 lines
1.2 KiB
C
34 lines
1.2 KiB
C
/***************************************************************************
|
|
* __________ __ ___.
|
|
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
|
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
|
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
|
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
|
* \/ \/ \/ \/ \/
|
|
* $Id$
|
|
*
|
|
* Copyright (C) 2006,2007 by Greg White
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License
|
|
* as published by the Free Software Foundation; either version 2
|
|
* of the License, or (at your option) any later version.
|
|
*
|
|
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
|
* KIND, either express or implied.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#ifndef MMU_ARM_H
|
|
#define MMU_ARM_H
|
|
|
|
#define CACHE_ALL 0x0C
|
|
#define CACHE_NONE 0
|
|
#define BUFFERED 0x04
|
|
|
|
void memory_init(void);
|
|
void ttb_init(void);
|
|
void enable_mmu(void);
|
|
void map_section(unsigned int pa, unsigned int va, int mb, int flags);
|
|
|
|
#endif /* MMU_ARM_H */
|