William Wilgus 3a7a46d1c0 Hosted targets Fix timer cycle calculation overflow ... at 1 GHZ the intermediate calculation for cycles overflows 32 bits this makes timer fail even with sensible values solution divide both sides by 100 Change-Id: I18a4054c2d06fb72531d5496bba562f71b03984f		2020-10-23 15:35:11 +00:00
..
arm	Work around wonky inline asm issue with creativezenvm build.	2020-10-13 21:48:23 -04:00
coldfire	fix more yellow	2020-10-13 17:23:56 -04:00
hosted	Hosted targets Fix timer cycle calculation overflow	2020-10-23 15:35:11 +00:00
mips	xduoox3: Disable the DAC's digital de-emphasis filter.	2020-10-15 13:30:48 -04:00