forked from len0rd/rockbox
18bee1bafb
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31507 a1c6a512-1295-4272-9138-f99709370657
87 lines
3.2 KiB
C
87 lines
3.2 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright © 2009 Rafaël Carré
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __AS3525V2_H__
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#define __AS3525V2_H__
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#include "as3525.h"
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/* insert differences here */
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#define CACHEALIGN_BITS (5)
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#ifndef IRAM_SIZE /* protect in case the define name changes */
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# error IRAM_SIZE not defined !
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#endif
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#undef IRAM_SIZE
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#define IRAM_SIZE 0x100000
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#define CGU_SDSLOT (*(volatile unsigned long *)(CGU_BASE + 0x3C))
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#undef USB_NUM_ENDPOINTS
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#define USB_NUM_ENDPOINTS 6
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#define CCU_USB (*(volatile unsigned long *)(CCU_BASE + 0x20))
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#undef USB_DEVBSS_ATTR
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#define USB_DEVBSS_ATTR __attribute__((aligned(32)))
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#define USBPHY_REG(offset) (*(volatile uint32_t*)(OTGBASE + offset))
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/** User HW Config1 Register */
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#define GHWCFG1 USBPHY_REG(0x044)
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#define GHWCFG1_epdir_bitp(ep) (2 * (ep))
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#define GHWCFG1_epdir_bits 0x3
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#define GHWCFG1_EPDIR_BIDIR 0
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#define GHWCFG1_EPDIR_IN 1
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#define GHWCFG1_EPDIR_OUT 2
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/** User HW Config2 Register */
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#define GHWCFG2 USBPHY_REG(0x048)
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#define GHWCFG2_arch_bitp 3 /** Architecture */
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#define GHWCFG2_arch_bits 0x3
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#define GHWCFG2_hs_phy_type_bitp 6 /** High speed PHY type */
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#define GHWCFG2_hs_phy_type_bits 0x3
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#define GHWCFG2_fs_phy_type_bitp 8 /** Full speed PHY type */
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#define GHWCFG2_fs_phy_type_bits 0x3
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#define GHWCFG2_num_ep_bitp 10 /** Number of endpoints */
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#define GHWCFG2_num_ep_bits 0xf
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#define GHWCFG2_dyn_fifo (1 << 19) /** Dynamic FIFO */
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/* For GHWCFG2_HS_PHY_TYPE and GHWCFG2_FS_PHY_TYPE */
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#define GHWCFG2_PHY_TYPE_UNSUPPORTED 0
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#define GHWCFG2_PHY_TYPE_UTMI 1
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#define GHWCFG2_ARCH_INTERNAL_DMA 2
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/** User HW Config3 Register */
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#define GHWCFG3 USBPHY_REG(0x04C)
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#define GHWCFG3_dfifo_len_bitp 16 /** Total fifo size */
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#define GHWCFG3_dfifo_len_bits 0xffff
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/** User HW Config4 Register */
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#define GHWCFG4 USBPHY_REG(0x050)
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#define GHWCFG4_utmi_phy_data_width_bitp 14 /** UTMI+ data bus width */
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#define GHWCFG4_utmi_phy_data_width_bits 0x3
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#define GHWCFG4_ded_fifo_en (1 << 25) /** Dedicated Tx FIFOs */
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#define GHWCFG4_num_in_ep_bitp 26 /** Number of IN endpoints */
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#define GHWCFG4_num_in_ep_bits 0xf
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#endif /* __AS3525V2_H__ */
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