forked from len0rd/rockbox
67f7d399e5
I-cache must be flushed after copying code to IRAM... duh. Change-Id: I6eacc4b7c4385175724c947f6c53f7bbddcb6295
265 lines
5.9 KiB
ArmAsm
265 lines
5.9 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021-2022 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "mips.h"
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.text
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.extern main
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.extern system_early_init
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.extern _loadaddress
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.global _start
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.set push
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.set mips32
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.set noreorder
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.set noat
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.section .init.text
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_start:
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b _realstart
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nop
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/* Header entries are 4-byte string labels (not null terminated!) followed
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* by 4-byte values. Header should begin in the first 128 bytes and should
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* be no more than 256 bytes in length. */
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_header:
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.ascii "BEGINHDR" /* beginning of header */
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.ascii "LOAD"
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.word _loadaddress
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.ascii "ENDH" /* end of header structure */
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_realstart:
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/* Copy IRAM from BSS to low memory. */
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la a0, _iramcopy
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la a1, _iramstart
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la a2, _iramend
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bal _copy
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nop
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/* Copy TCSM from BSS */
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la a0, _tcsmcopy
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la a1, _tcsmstart
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la a2, _tcsmend
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bal _copy
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nop
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/* Clear the BSS segment (needed to zero-initialize C static values) */
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la a0, _bssbegin
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la a1, _bssend
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bal _clear
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move a2, $0
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/* Set stack pointer and clear the stack */
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la sp, stackend
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la a0, stackbegin
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li a2, 0xDEADBEEF
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bal _clear
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move a1, sp
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/* Clear the IRQ stack */
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la k0, _irqstackend
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la a0, _irqstackbegin
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bal _clear
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move a1, k0
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/* Write back D-cache and invalidate I-cache */
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li v0, 0x80000000
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ori v1, v0, (0x4000 - 32)
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mtc0 zero, C0_TAGLO
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mtc0 zero, C0_TAGHI
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1:
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cache DCIndexWBInv, 0(v0)
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cache ICIndexStTag, 0(v0)
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bne v0, v1, 1b
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addiu v0, v0, 32
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/* Invalidate BTB */
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mfc0 v0, C0_Config, 7
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nop
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ori v0, v0, 2
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mtc0 v0, C0_Config, 7
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nop
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/* Jump to C code */
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jal system_early_init
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nop
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j main
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nop
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/* copy(void* src, void* dst, void* dst_end) */
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_copy:
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beq a1, a2, 1f
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addiu a1, 4
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lw t0, 0(a0)
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addiu a0, 4
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b _copy
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sw t0, -4(a1)
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1:
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jr ra
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nop
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/* clear(void* dst, void* dst_end, int value) */
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_clear:
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beq a0, a1, 1f
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addiu a0, 4
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b _clear
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sw a2, -4(a0)
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1:
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jr ra
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nop
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/* Exception entry points */
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.section .vectors.1, "ax", %progbits
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j tlb_refill_handler
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nop
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.section .vectors.2, "ax", %progbits
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j real_exception_handler
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nop
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.section .vectors.3, "ax", %progbits
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j real_exception_handler
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nop
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.section .vectors.4, "ax", %progbits
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j real_exception_handler
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nop
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.section .vectors, "ax", %progbits
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real_exception_handler:
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move k0, sp
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la sp, _irqstackend
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addiu sp, -0x84
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sw k0, 0x80(sp)
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sw ra, 0x00(sp)
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sw fp, 0x04(sp)
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sw gp, 0x08(sp)
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sw t9, 0x0c(sp)
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sw t8, 0x10(sp)
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sw s7, 0x14(sp)
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sw s6, 0x18(sp)
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sw s5, 0x1c(sp)
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sw s4, 0x20(sp)
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sw s3, 0x24(sp)
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sw s2, 0x28(sp)
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sw s1, 0x2c(sp)
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sw s0, 0x30(sp)
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sw t7, 0x34(sp)
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sw t6, 0x38(sp)
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sw t5, 0x3c(sp)
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sw t4, 0x40(sp)
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sw t3, 0x44(sp)
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sw t2, 0x48(sp)
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sw t1, 0x4c(sp)
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sw t0, 0x50(sp)
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sw a3, 0x54(sp)
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sw a2, 0x58(sp)
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sw a1, 0x5c(sp)
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sw a0, 0x60(sp)
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sw v1, 0x64(sp)
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sw v0, 0x68(sp)
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sw $1, 0x6c(sp)
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mflo k0
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nop
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sw k0, 0x70(sp)
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mfhi k0
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nop
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sw k0, 0x74(sp)
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mfc0 k0, C0_STATUS
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nop
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nop
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nop
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sw k0, 0x78(sp)
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mfc0 k0, C0_EPC
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nop
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nop
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nop
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sw k0, 0x7c(sp)
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li k1, M_CauseExcCode
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mfc0 a0, C0_CAUSE
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and k0, a0, k1
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bnez k0, _exception
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nop
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jal intr_handler
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nop
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j _exception_return
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_exception:
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mfc0 a1, C0_EPC
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nop
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nop
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nop
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jal exception_handler
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move a2, sp
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_exception_return:
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lw ra, 0x00(sp)
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lw fp, 0x04(sp)
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lw gp, 0x08(sp)
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lw t9, 0x0c(sp)
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lw t8, 0x10(sp)
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lw s7, 0x14(sp)
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lw s6, 0x18(sp)
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lw s5, 0x1c(sp)
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lw s4, 0x20(sp)
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lw s3, 0x24(sp)
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lw s2, 0x28(sp)
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lw s1, 0x2c(sp)
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lw s0, 0x30(sp)
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lw t7, 0x34(sp)
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lw t6, 0x38(sp)
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lw t5, 0x3c(sp)
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lw t4, 0x40(sp)
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lw t3, 0x44(sp)
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lw t2, 0x48(sp)
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lw t1, 0x4c(sp)
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lw t0, 0x50(sp)
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lw a3, 0x54(sp)
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lw a2, 0x58(sp)
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lw a1, 0x5c(sp)
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lw a0, 0x60(sp)
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lw v1, 0x64(sp)
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lw v0, 0x68(sp)
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lw $1, 0x6c(sp)
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lw k0, 0x70(sp)
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mtlo k0
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nop
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lw k0, 0x74(sp)
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mthi k0
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nop
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lw k0, 0x78(sp)
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mtc0 k0, C0_STATUS
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nop
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nop
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nop
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lw k0, 0x7c(sp)
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mtc0 k0, C0_EPC
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nop
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nop
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nop
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lw sp, 0x80(sp)
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eret
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nop
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.set pop
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