forked from len0rd/rockbox
d22bb548b2
This information is available in the RDA5802N or RDA5807 datasheet. I suspect that register SYSCONFIG6 is not actually used by the tuner. Based on an obscure statement in the datasheet, I guess SYSCONFIG5 is a frequency in Khz called freq_direct that offsets the lower band frequency (56/67 MHz) but 1) it is not enabled (FREQ_MODE=0) and 2) it is not clear if this offset is really just to avoid interference (ie the RF and IF are simply shifted by this amount) or an actual offset. Change-Id: Ia469f5370aee7c8c3390324d0cef1193c64df755
375 lines
11 KiB
C
375 lines
11 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Tuner "middleware" for RDA5802 chip present in some Sansa Clip+ players
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*
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* Copyright (C) 2010 Bertrik Sikken
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* Copyright (C) 2008 Nils Wallménius (si4700 code that this was based on)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include <stdbool.h>
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#include <string.h>
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#include <stdlib.h>
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#include "kernel.h"
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#include "power.h"
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#include "tuner.h" /* tuner abstraction interface */
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#include "fmradio.h"
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#include "fmradio_i2c.h" /* physical interface driver */
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#include "audio.h"
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#include "backlight.h"
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#define SEEK_THRESHOLD 0x16
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#define I2C_ADR 0x20
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/* define RSSI range */
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#define RSSI_MIN 0
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#define RSSI_MAX 70
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/** Registers and bits **/
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#define CHIPID 0x0
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#define POWERCFG 0x2
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#define CHANNEL 0x3
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#define SYSCONFIG1 0x4
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#define SYSCONFIG2 0x5
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#define SYSCONFIG3 0x6
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#define SYSCONFIG4 0x7
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#define SYSCONFIG5 0x8
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#define SYSCONFIG6 0x9 /* suspected not to exists */
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#define READCHAN 0xA
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#define STATUSRSSI 0xB
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/* POWERCFG (0x2) */
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#define POWERCFG_DMUTE (0x1 << 14)
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#define POWERCFG_MONO (0x1 << 13)
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#define POWERCFG_SOFT_RESET (0x1 << 1)
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#define POWERCFG_ENABLE (0x1 << 0)
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/* CHANNEL (0x3) */
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#define CHANNEL_CHAN (0x3ff << 6)
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#define CHANNEL_CHANw(x) (((x) << 6) & CHANNEL_CHAN)
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#define CHANNEL_TUNE (0x1 << 4)
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#define CHANNEL_BAND (0x3 << 2)
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#define CHANNEL_BANDw(x) (((x) << 2) & CHANNEL_BAND)
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#define CHANNEL_BANDr(x) (((x) & CHANNEL_BAND) >> 2)
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#define CHANNEL_BAND_870_1080 (0x0) /* tenth-megahertz */
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#define CHANNEL_BAND_760_1080 (0x1)
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#define CHANNEL_BAND_760_900 (0x2)
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#define CHANNEL_BAND_650_760 (0x3)
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#define CHANNEL_SPACE (0x3 << 0)
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#define CHANNEL_SPACEw(x) (((x) << 0) & CHANNEL_SPACE)
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#define CHANNEL_SPACEr(x) (((x) & CHANNEL_SPACE) >> 0)
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#define CHANNEL_SPACE_100KHZ (0x0)
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#define CHANNEL_SPACE_200KHZ (0x1)
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#define CHANNEL_SPACE_50KHZ (0x2)
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/* SYSCONFIG1 (0x4) */
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#define SYSCONFIG1_DE (0x1 << 11)
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#define SYSCONFIG1_SOFTMUTE_EN (0x1 << 9)
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/* SYSCONFIG2 (0x5) */
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#define SYSCONFIG2_VOLUME (0xF << 0)
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/* READCHAN (0xA) */
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#define READCHAN_READCHAN (0x3ff << 0)
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#define READCHAN_READCHANr(x) (((x) & READCHAN_READCHAN) >> 0)
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#define READCHAN_STC (0x1 << 14)
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#define READCHAN_ST (0x1 << 10)
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/* STATUSRSSI (0xB) */
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#define STATUSRSSI_RSSI (0x7F << 9)
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#define STATUSRSSI_RSSIr(x) (((x) & STATUSRSSI_RSSI) >> 9)
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#define STATUSRSSI_FM_TRUE (0x1 << 8)
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static bool tuner_present = false;
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static uint16_t cache[16] = {
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[POWERCFG] = 0xC401, /* DHIZ, DMUTE, CLK_DIRECT_MODE, ENABLE */
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[CHANNEL] = 0x0000, /* - */
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[SYSCONFIG1] = 0x0200, /* SYSCONFIG1_SOFTMUTE_EN */
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[SYSCONFIG2] = 0x867F, /* INT_MODE (def), SEEKTH=1100b, LNA_PORT_SEL=LNAN,
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LNA_ICSEL=3.0mA, VOLUME=max */
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[SYSCONFIG3] = 0x8000, /* RSVD */
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[SYSCONFIG4] = 0x4712, /* TH_SOFRBLEND=34dB, 65M_50M MODE=65~76MHz, RSVD, SEEK_TH_OLD=4, SOFTBLEND_EN */
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[SYSCONFIG5] = 0x5EC6, /* FREQ_DIRECT=24262kHz (unused) */
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[SYSCONFIG6] = 0x0000 /* undocumented */
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};
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/* reads <len> registers from radio at offset 0x0A into cache */
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static void rda5802_read(int len)
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{
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int i;
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unsigned char buf[sizeof(cache)];
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unsigned char *ptr = buf;
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uint16_t data;
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fmradio_i2c_read(I2C_ADR, buf, len * 2);
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for (i = 0; i < len; i++) {
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data = ptr[0] << 8 | ptr[1];
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cache[READCHAN + i] = data;
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ptr += 2;
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}
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}
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/* writes <len> registers from cache to radio at offset 0x02 */
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static void rda5802_write(int len)
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{
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int i;
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unsigned char buf[sizeof(cache)];
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unsigned char *ptr = buf;
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uint16_t data;
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for (i = 0; i < len; i++) {
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data = cache[POWERCFG + i];
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*ptr++ = (data >> 8) & 0xFF;
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*ptr++ = data & 0xFF;
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}
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fmradio_i2c_write(I2C_ADR, buf, len * 2);
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}
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static uint16_t rda5802_read_reg(int reg)
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{
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rda5802_read((reg - READCHAN) + 1);
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return cache[reg];
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}
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static void rda5802_write_reg(int reg, uint16_t value)
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{
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cache[reg] = value;
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}
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static void rda5802_write_cache(void)
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{
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rda5802_write(5);
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}
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static void rda5802_write_masked(int reg, uint16_t bits, uint16_t mask)
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{
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rda5802_write_reg(reg, (cache[reg] & ~mask) | (bits & mask));
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}
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static void rda5802_write_clear(int reg, uint16_t mask)
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{
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rda5802_write_reg(reg, cache[reg] & ~mask);
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}
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static void rda5802_write_set(int reg, uint16_t mask)
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{
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rda5802_write_reg(reg, cache[reg] | mask);
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}
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static void rda5802_sleep(int snooze)
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{
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if (snooze) {
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rda5802_write_clear(POWERCFG, POWERCFG_ENABLE);
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}
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else {
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tuner_power(true);
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rda5802_write_set(POWERCFG, POWERCFG_ENABLE);
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}
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rda5802_write_cache();
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if(snooze)
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tuner_power(false);
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}
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bool rda5802_detect(void)
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{
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/* The RDA5802 has a weird wrap-around at 0x40. Upon initialisation, it will copy the Chip ID
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* to register 0xC but since this register is also used for RDS, we cannot rely on its content
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* until we softreset. But we cannot soft-reset until we confirm the tuner type... So we really
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* need to register 0, which means reading 0x40 registers.
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* NOTE: the datasheet says that it wraps around at 0x3A but this is wrong. */
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/* we want to read registers 0x00/0x01, aka 0x40/0x41 because of wrapping, tuner starts reading
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* at 0xA so we need to read 0x40 - 0xA + 2 registers, each register is two bytes. Thats
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* (0x40 - 0xA + 2) * 2 = 0x6e bytes */
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unsigned char buf[0x70];
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fmradio_i2c_read(I2C_ADR, buf, sizeof(buf));
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cache[CHIPID] = buf[0x6c] << 8 | buf[0x6d];
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cache[1] = buf[0x6e] << 8 | buf[0x6f]; /* unknown register, maybe firmware ID or related */
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return ((cache[CHIPID] & 0xFF00) == 0x5800);
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}
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void rda5802_init(void)
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{
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if (rda5802_detect()) {
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tuner_present = true;
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/* soft-reset */
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rda5802_write_set(POWERCFG, POWERCFG_SOFT_RESET);
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rda5802_write(1);
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rda5802_write_clear(POWERCFG, POWERCFG_SOFT_RESET);
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sleep(HZ * 10 / 1000);
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/* write initialisation values */
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rda5802_write(8);
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sleep(HZ * 70 / 1000);
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}
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}
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static void rda5802_set_frequency(int freq)
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{
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int i;
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uint16_t readchan;
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static const int spacings[] = {100000, 200000, 50000, 50000};
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static const int bandstart[] = {87000000, 76000000, 76000000, 65000000};
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/* calculate channel number */
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int start = bandstart[CHANNEL_BANDr(cache[CHANNEL])];
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int space = spacings[CHANNEL_SPACEr(cache[CHANNEL])];
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int chan = (freq - start) / space;
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for (i = 0; i < 5; i++) {
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/* tune and wait a bit */
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rda5802_write_masked(CHANNEL, CHANNEL_CHANw(chan) | CHANNEL_TUNE,
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CHANNEL_CHAN | CHANNEL_TUNE);
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rda5802_write_cache();
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sleep(HZ * 70 / 1000);
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rda5802_write_clear(CHANNEL, CHANNEL_TUNE);
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rda5802_write_cache();
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/* check if tuning was successful */
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readchan = rda5802_read_reg(READCHAN);
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if (readchan & READCHAN_STC) {
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if (READCHAN_READCHANr(readchan) == chan) {
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break;
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}
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}
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}
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}
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static int rda5802_tuned(void)
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{
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/* Primitive tuning check: sufficient level and AFC not railed */
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uint16_t status = rda5802_read_reg(STATUSRSSI);
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if (STATUSRSSI_RSSIr(status) >= SEEK_THRESHOLD &&
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(status & STATUSRSSI_FM_TRUE)) {
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return 1;
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}
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return 0;
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}
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static void rda5802_set_region(int region)
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{
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const struct fm_region_data *rd = &fm_region_data[region];
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int band = (rd->freq_min == 76000000) ?
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CHANNEL_BAND_760_900 : CHANNEL_BAND_870_1080;
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int deemphasis = (rd->deemphasis == 50) ? SYSCONFIG1_DE : 0;
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int space = (rd->freq_step == 50000) ?
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CHANNEL_SPACE_50KHZ : CHANNEL_SPACE_100KHZ;
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rda5802_write_masked(SYSCONFIG1, deemphasis, SYSCONFIG1_DE);
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rda5802_write_masked(CHANNEL, CHANNEL_BANDw(band), CHANNEL_BAND);
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rda5802_write_masked(CHANNEL, CHANNEL_SPACEw(space), CHANNEL_SPACE);
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rda5802_write_cache();
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}
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static bool rda5802_st(void)
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{
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return (rda5802_read_reg(READCHAN) & READCHAN_ST);
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}
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static int rda5802_rssi(void)
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{
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uint16_t status = rda5802_read_reg(STATUSRSSI);
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return STATUSRSSI_RSSIr(status);
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}
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/* tuner abstraction layer: set something to the tuner */
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int rda5802_set(int setting, int value)
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{
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switch (setting) {
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case RADIO_SLEEP:
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rda5802_sleep(value);
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break;
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case RADIO_FREQUENCY:
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rda5802_set_frequency(value);
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break;
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case RADIO_SCAN_FREQUENCY:
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rda5802_set_frequency(value);
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return rda5802_tuned();
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case RADIO_MUTE:
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rda5802_write_masked(POWERCFG, value ? 0 : POWERCFG_DMUTE,
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POWERCFG_DMUTE);
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rda5802_write_cache();
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break;
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case RADIO_REGION:
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rda5802_set_region(value);
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break;
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case RADIO_FORCE_MONO:
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rda5802_write_masked(POWERCFG, value ? POWERCFG_MONO : 0,
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POWERCFG_MONO);
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rda5802_write_cache();
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break;
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default:
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return -1;
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}
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return 1;
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}
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/* tuner abstraction layer: read something from the tuner */
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int rda5802_get(int setting)
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{
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int val = -1; /* default for unsupported query */
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switch (setting) {
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case RADIO_PRESENT:
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val = tuner_present ? 1 : 0;
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break;
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case RADIO_TUNED:
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val = ((audio_status() & AUDIO_STATUS_RECORD) || !is_backlight_on(true)) ? 1 : rda5802_tuned();
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break;
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case RADIO_STEREO:
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val = ((audio_status() & AUDIO_STATUS_RECORD) || !is_backlight_on(true)) ? 1 : rda5802_st();
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break;
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case RADIO_RSSI:
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val = ((audio_status() & AUDIO_STATUS_RECORD) || !is_backlight_on(true)) ? RSSI_MAX : rda5802_rssi();
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break;
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case RADIO_RSSI_MIN:
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val = RSSI_MIN;
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break;
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case RADIO_RSSI_MAX:
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val = RSSI_MAX;
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break;
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}
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return val;
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}
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void rda5802_dbg_info(struct rda5802_dbg_info *nfo)
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{
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rda5802_read(6);
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memcpy(nfo->regs, cache, sizeof (nfo->regs));
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}
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