forked from len0rd/rockbox
a3fe07ff12
Add HW volume control via ES9018K2M, and reorganize eros_qn_codec.c/.h, audiohw-erosqnative.c. This automatically detects the presence of the new DAC and uses its hardware volume scaling. If not present, use same SWVOL we have been using so far. Add debug menu readout of SWVOL/I2C result. Break out es9018k2m stuff into its own file so that maybe it can be useful to other ports. Note that we may need to get smarter about detecting the DAC type if/when another model emerges. Change-Id: I586a1cf7f150dd6b4e221157859825952840af56
134 lines
4.1 KiB
C
134 lines
4.1 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2016 by Roman Stolyarov
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "es9018.h"
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#include "config.h"
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#include "audio.h"
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#include "audiohw.h"
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/* NOTE: This implementation is specifically for the ES9018K2M, which has a different register
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* structure from the ES9018. */
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static uint8_t reg0 = 0x00; /* System settings. Default value of register 0 */
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static uint8_t reg1 = 0x80; /* Input settings. Manual input, I2S, 32-bit (?) */
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static uint8_t reg4 = 0x00; /* Automute time. Default = disabled */
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static uint8_t reg5 = 0x68; /* Automute level. Default is some level */
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static uint8_t reg6 = 0x4A; /* Deemphasis. Default = disabled */
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static uint8_t reg7 = 0x83; /* General settings. Default sharp fir, pcm iir and muted */
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static uint8_t reg8 = 0x10; /* GPIO configuration */
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static uint8_t reg10 = 0x05; /* Master Mode Control. Default value: master mode off */
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static uint8_t reg11 = 0x02; /* Channel Mapping. Default stereo is Ch1=left, Ch2=right */
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static uint8_t reg12 = 0x50; /* DPLL Settings. Default = 005 for I2S, OFF for DSD */
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static uint8_t reg13 = 0x40; /* THD Compensation */
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static uint8_t reg14 = 0x8A; /* Soft Start Settings */
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static uint8_t reg21 = 0x00; /* Oversampling filter. Default: oversampling ON */
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#define bitSet(value, bit) ((value) |= (1UL << (bit)))
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#define bitClear(value, bit) ((value) &= ~(1UL << (bit)))
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static int vol_tenthdb2hw(const int tdb)
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{
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if (tdb < ES9018_VOLUME_MIN) {
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return 0xff;
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} else if (tdb > ES9018_VOLUME_MAX) {
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return 0x00;
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} else {
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return (-tdb/5);
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}
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}
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void audiohw_set_volume(int vol_l, int vol_r)
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{
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es9018_write_reg(15, vol_tenthdb2hw(vol_l));
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es9018_write_reg(16, vol_tenthdb2hw(vol_r));
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}
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void audiohw_mute(void)
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{
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bitSet(reg7, 0); /* Mute Channel 1 */
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bitSet(reg7, 1); /* Mute Channel 2 */
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es9018_write_reg(0x07, reg7);
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}
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void audiohw_unmute(void)
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{
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bitClear(reg7, 0); /* Unmute Channel 1 */
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bitClear(reg7, 1); /* Unmute Channel 2 */
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es9018_write_reg(0x07, reg7);
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}
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void audiohw_init(void)
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{
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es9018_write_reg(0x00, reg0);
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es9018_write_reg(0x01, reg1);
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es9018_write_reg(0x04, reg4);
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es9018_write_reg(0x05, reg5);
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es9018_write_reg(0x06, reg6);
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es9018_write_reg(0x07, reg7);
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es9018_write_reg(0x08, reg8);
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es9018_write_reg(0x0A, reg10);
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es9018_write_reg(0x0B, reg11);
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es9018_write_reg(0x0C, reg12);
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es9018_write_reg(0x0D, reg13);
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es9018_write_reg(0x0E, reg14);
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es9018_write_reg(0x15, reg21);
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}
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void audiohw_preinit(void)
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{
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}
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void audiohw_set_frequency(int fsel)
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{
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(void)fsel;
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}
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void audiohw_set_filter_roll_off(int value)
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{
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/* 0 = Sharp (Default)
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1 = Slow
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2 = Short
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3 = Bypass */
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switch(value)
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{
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case 0:
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bitClear(reg7, 5);
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bitClear(reg7, 6);
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bitClear(reg21, 0);
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break;
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case 1:
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bitSet(reg7, 5);
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bitClear(reg7, 6);
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bitClear(reg21, 0);
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break;
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case 2:
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bitClear(reg7, 5);
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bitSet(reg7, 6);
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bitClear(reg21, 0);
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break;
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case 3:
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bitSet(reg21, 0);
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break;
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}
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es9018_write_reg(0x07, reg7);
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es9018_write_reg(0x15, reg21);
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}
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