4 commits

Author	SHA1	Message	Date
Solomon Peachy	caaea275eb	libspc: Temporarily disable problematic armv4 asm optimization ... asm volatile ( "mov %[t0], %[out], asr #11 \n" "mul %[out], %[t0], %[envx] \n" : [out]"+r"(output), [t0]"=&r"(t0) : [envx]"r"((int) voice->envx)); This is resulting in "Rd and Rm should be different in mul" error, because the compiler is putting [out] and [t0] into the same register. After some poking there doesn't appear to be a sane way to change the constraints, so just disable it for now. Change-Id: I7827713c8aadb27f0bf4a6f4a3e1d910c6193686	2025-09-21 15:39:35 -04:00
Michael Sevakis	30fe6eb66c	SPC Codec ARMv5: I didn't have fast gauss quite right. ... Fix wrapping hazard which did eventually manifest on the right file. Change-Id: I996a6efd3181b56fd172b5c3a526c7434f88bbbe	2013-05-26 00:33:30 -04:00
Michael Sevakis	33f3af2b8d	SPC Codec: Add ARMv5 optimized code. Easy peasy. ... Why? Why not? Cuts a few MHz. Change-Id: Ied5c70b1aedd255cbe5d42b7d3028bbe47aad01d	2013-05-23 03:15:12 -04:00
Michael Sevakis	87021f7c0a	SPC Codec: Refactor for CPU and clean up some things. ... CPU optimization gets its own files in which to fill-in optimizable routines. Some pointless #if 0's for profiling need removal. Those macros are empty if not profiling. Force some functions that are undesirable to be force-inlined by the compiler to be not inlined. Change-Id: Ia7b7e45380d7efb20c9b1a4d52e05db3ef6bbaab	2013-05-21 00:02:14 -04:00