PCLK doesn't use PLLA as a source but FCLK, so when changing FCLK with
CGU_PROC register, we must change PCLK as well with CGU_PERI register
Operate with 24MHz PCLK (and unboosted FCLK) for Clipv2/Clip+
Use 60MHz on Fuzev2 to keep the display fast enough (still slower than
Fuzev1 though)
µSD seems to function correctly now
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25475 a1c6a512-1295-4272-9138-f99709370657
We can write to DBOP_DOUT in 8 bits mode : bits 7..0 are mapped to the
LCD, not bits 15..12 and 3..0 like on Clipv1
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25455 a1c6a512-1295-4272-9138-f99709370657
1 more hour of battery life measured on Clip+ : 16h30 with mp3 @192kbps
Fuzev2 frequency isn't changed because the scrollwheel is less
responsive below 60MHz
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25448 a1c6a512-1295-4272-9138-f99709370657
Brightness changes on the Fuzev2 now work flawlessly
This might also explain why my Clip+ would sometimes "not boot", that
could have been because the backlight was not enabled at all.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25445 a1c6a512-1295-4272-9138-f99709370657
Move scrollwheel parsing function into separate file as it's reused.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25425 a1c6a512-1295-4272-9138-f99709370657
the arm926-ejs doesn't have synchronous/asynchronous/fastbus modes, so
just change CGU_PROC directly
Note: we could use a lower unboosted frequency now
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25417 a1c6a512-1295-4272-9138-f99709370657
Write the setting before enabling the PLL
Fix booting problem (black screen) with Clip+
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25415 a1c6a512-1295-4272-9138-f99709370657
Instead of modifying CGU_PROC to get 24MHz pclk, just switch to fastbus else Clip+ wouldn't boot
Tested on fuzev1/Clip+
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25413 a1c6a512-1295-4272-9138-f99709370657
They're all the same when charger is unplugged, but when it's plugged:
- BVDD is way too high
- RTCSUP oscillates between 2 values
- CHG_IN acts like RTCSUP on some models but seems to works fine on my Clip+
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25405 a1c6a512-1295-4272-9138-f99709370657
I have also made the CMD_CHECK_CRC_BIT unused for now since we do not check any response crc values yet.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25343 a1c6a512-1295-4272-9138-f99709370657
Introduce STORAGE_ALIGN_DOWN, STORAGE_PAD (using new CACHE_PAD) and
STORAGE_OVERLAP (using new CACHE_OVERLAP), make them useful only when
PROC_NEEDS_CACHEALIGN and STORAGE_NEEDS_ALIGN are defined
Modify PP and nano2g system-target.h accordingly
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25336 a1c6a512-1295-4272-9138-f99709370657
The internal card does not appear to be HS capable, at least not in 2GB clip+
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25316 a1c6a512-1295-4272-9138-f99709370657
The controller only needs to be reset if we had an error to clean up any leftover trash...
Move comment pertaining to retry variable so it's actually nearby.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25315 a1c6a512-1295-4272-9138-f99709370657
Adjust the initial MCI_MASK value to also mask the MCI_INT_RXDR and MCI_INT_TXDR bits as it seems we don't use them for dma transfers.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25314 a1c6a512-1295-4272-9138-f99709370657
Move CLKDIV macros into clock-target.h.
Only enable the necessary interfaces for the 3 clock registers used for SD.
Add MEMSTICK and SDSLOT registers to bottom of register display in View HW info debug page.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25309 a1c6a512-1295-4272-9138-f99709370657
The registers value does not change so we don't need to read them
This avoids dividing by 0
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25303 a1c6a512-1295-4272-9138-f99709370657
