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Use register defines

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18068 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Maurus Cuelenaere 2008-07-16 12:25:27 +00:00
parent dff382cb9c
commit ffddab1e66
2 changed files with 175 additions and 69 deletions
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105
firmware/export/r61509.h Normal file
View file

@ -0,0 +1,105 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id$
*
* Copyright (C) 2008 by Maurus Cuelenaere
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
/*
* Register definitions for the Renesas R61509 TFT Panel
*/
#ifndef __R61509_H
#define __R61509_H
/* Register list */
#define REG_DRIVER_OUTPUT 0x001
#define REG_LCD_DR_WAVE_CTRL 0x002
#define REG_ENTRY_MODE 0x003
#define REG_DISP_CTRL1 0x007
#define REG_DISP_CTRL2 0x008
#define REG_DISP_CTRL3 0x009
#define REG_LPCTRL 0x00B
#define REG_EXT_DISP_CTRL1 0x00C
#define REG_EXT_DISP_CTRL2 0x00F
#define REG_PAN_INTF_CTRL1 0x010
#define REG_PAN_INTF_CTRL2 0x011
#define REG_PAN_INTF_CTRL3 0x012
#define REG_PAN_INTF_CTRL4 0x020
#define REG_PAN_INTF_CTRL5 0x021
#define REG_PAN_INTF_CTRL6 0x022
#define REG_FRM_MRKR_CTRL 0x090
#define REG_PWR_CTRL1 0x100
#define REG_PWR_CTRL2 0x101
#define REG_PWR_CTRL3 0x102
#define REG_PWR_CTRL4 0x103
#define REG_PWR_CTRL5 0x107
#define REG_PWR_CTRL6 0x110
#define REG_PWR_CTRL7 0x112
#define REG_RAM_HADDR_SET 0x200
#define REG_RAM_VADDR_SET 0x201
#define REG_RW_GRAM 0x202
#define REG_RAM_HADDR_START 0x210
#define REG_RAM_HADDR_END 0x211
#define REG_RAM_VADDR_START 0x212
#define REG_RAM_VADDR_END 0x213
#define REG_RW_NVM 0x280
#define REG_VCOM_HVOLTAGE1 0x281
#define REG_VCOM_HVOLTAGE2 0x282
#define REG_GAMMA_CTRL1 0x300
#define REG_GAMMA_CTRL2 0x301
#define REG_GAMMA_CTRL3 0x302
#define REG_GAMMA_CTRL4 0x303
#define REG_GAMMA_CTRL5 0x304
#define REG_GAMMA_CTRL6 0x305
#define REG_GAMMA_CTRL7 0x306
#define REG_GAMMA_CTRL8 0x307
#define REG_GAMMA_CTRL9 0x308
#define REG_GAMMA_CTRL10 0x309
#define REG_GAMMA_CTRL11 0x30A
#define REG_GAMMA_CTRL12 0x30B
#define REG_GAMMA_CTRL13 0x30C
#define REG_GAMMA_CTRL14 0x30D
#define REG_BIMG_NR_LINE 0x400
#define REG_BIMG_DISP_CTRL 0x401
#define REG_BIMG_VSCROLL_CTRL 0x404
#define REG_PARTIMG1_POS 0x500
#define REG_PARTIMG1_RAM_START 0x501
#define REG_PARTIMG1_RAM_END 0x502
#define REG_PARTIMG2_POS 0x503
#define REG_PARTIMG2_RAM_START 0x504
#define REG_PARTIMG2_RAM_END 0x505
#define REG_SOFT_RESET 0x600
#define REG_ENDIAN_CTRL 0x606
#define REG_NVM_ACCESS_CTRL 0x6F0
/* Bits */
#define DRIVER_OUTPUT_SS_BIT (1 << 8)
#define DRIVER_OUTPUT_SM_BIT (1 << 10)
#define SOFT_RESET_EN (1 << 0)
#define SOFT_RESET_DIS (0 << 0)
#define ENDIAN_CTRL_BIG
#define ENDIAN_CTRL_LITTLE
#endif /* __R61509_H */

139
firmware/target/mips/ingenic_jz47xx/onda_vx747/lcd-onda_vx747.c
View file

@ -21,6 +21,7 @@
#include "config.h" #include "config.h"
#include "jz4740.h" #include "jz4740.h"
#include "r61509.h"
#include "lcd-target.h" #include "lcd-target.h"
#define PIN_CS_N (32*1+17) /* Chip select */ #define PIN_CS_N (32*1+17) /* Chip select */
@ -60,81 +61,81 @@ static void _display_on(void)
{ {
int i; int i;
SLCD_SEND_COMMAND(0x600, 1); SLCD_SEND_COMMAND(REG_SOFT_RESET, SOFT_RESET_EN);
SLEEP(700000); SLEEP(700000);
SLCD_SEND_COMMAND(0x600, 0); SLCD_SEND_COMMAND(REG_SOFT_RESET, SOFT_RESET_DIS);
SLEEP(700000); SLEEP(700000);
SLCD_SEND_COMMAND(0x606, 0); SLCD_SEND_COMMAND(REG_ENDIAN_CTRL, 0);
SLCD_SEND_COMMAND(1, 0x100); SLCD_SEND_COMMAND(REG_DRIVER_OUTPUT, 0x100);
SLCD_SEND_COMMAND(2, 0x100); SLCD_SEND_COMMAND(REG_LCD_DR_WAVE_CTRL, 0x100);
SLCD_SEND_COMMAND(3, 0x1028); SLCD_SEND_COMMAND(REG_ENTRY_MODE, 0x1028);
SLCD_SEND_COMMAND(8, 0x503); SLCD_SEND_COMMAND(REG_DISP_CTRL2, 0x503);
SLCD_SEND_COMMAND(9, 1); SLCD_SEND_COMMAND(REG_DISP_CTRL3, 1);
SLCD_SEND_COMMAND(0xB, 0x10); SLCD_SEND_COMMAND(REG_LPCTRL, 0x10);
SLCD_SEND_COMMAND(0xC, 0); SLCD_SEND_COMMAND(REG_EXT_DISP_CTRL1, 0);
SLCD_SEND_COMMAND(0xF, 0); SLCD_SEND_COMMAND(REG_EXT_DISP_CTRL2, 0);
SLCD_SEND_COMMAND(7, 1); SLCD_SEND_COMMAND(REG_DISP_CTRL1, 1);
SLCD_SEND_COMMAND(0x10, 0x12); SLCD_SEND_COMMAND(REG_PAN_INTF_CTRL1, 0x12);
SLCD_SEND_COMMAND(0x11, 0x202); SLCD_SEND_COMMAND(REG_PAN_INTF_CTRL2, 0x202);
SLCD_SEND_COMMAND(0x12, 0x300); SLCD_SEND_COMMAND(REG_PAN_INTF_CTRL3, 0x300);
SLCD_SEND_COMMAND(0x20, 0x21e); SLCD_SEND_COMMAND(REG_PAN_INTF_CTRL4, 0x21e);
SLCD_SEND_COMMAND(0x21, 0x202); SLCD_SEND_COMMAND(REG_PAN_INTF_CTRL5, 0x202);
SLCD_SEND_COMMAND(0x22, 0x100); SLCD_SEND_COMMAND(REG_PAN_INTF_CTRL6, 0x100);
SLCD_SEND_COMMAND(0x90, 0x8000); SLCD_SEND_COMMAND(REG_FRM_MRKR_CTRL, 0x8000);
SLCD_SEND_COMMAND(0x100, 0x16b0); SLCD_SEND_COMMAND(REG_PWR_CTRL1, 0x16b0);
SLCD_SEND_COMMAND(0x101, 0x147); SLCD_SEND_COMMAND(REG_PWR_CTRL2, 0x147);
SLCD_SEND_COMMAND(0x102, 0x1bd); SLCD_SEND_COMMAND(REG_PWR_CTRL3, 0x1bd);
SLCD_SEND_COMMAND(0x103, 0x2f00); SLCD_SEND_COMMAND(REG_PWR_CTRL4, 0x2f00);
SLCD_SEND_COMMAND(0x107, 0); SLCD_SEND_COMMAND(REG_PWR_CTRL5, 0);
SLCD_SEND_COMMAND(0x110, 1); SLCD_SEND_COMMAND(REG_PWR_CTRL6, 1);
SLCD_SEND_COMMAND(0x200, 0); /* set cursor at x_start */ SLCD_SEND_COMMAND(REG_RAM_HADDR_SET, 0); /* set cursor at x_start */
SLCD_SEND_COMMAND(0x201, 0); /* set cursor at y_start */ SLCD_SEND_COMMAND(REG_RAM_VADDR_SET, 0); /* set cursor at y_start */
SLCD_SEND_COMMAND(0x210, 0); /* y_start*/ SLCD_SEND_COMMAND(REG_RAM_HADDR_START, 0); /* y_start*/
SLCD_SEND_COMMAND(0x211, 239); /* y_end */ SLCD_SEND_COMMAND(REG_RAM_HADDR_END, 239); /* y_end */
SLCD_SEND_COMMAND(0x212, 0); /* x_start */ SLCD_SEND_COMMAND(REG_RAM_VADDR_START, 0); /* x_start */
SLCD_SEND_COMMAND(0x213, 399); /* x_end */ SLCD_SEND_COMMAND(REG_RAM_VADDR_END, 399); /* x_end */
SLCD_SEND_COMMAND(0x280, 0); SLCD_SEND_COMMAND(REG_RW_NVM, 0);
SLCD_SEND_COMMAND(0x281, 6); SLCD_SEND_COMMAND(REG_VCOM_HVOLTAGE1, 6);
SLCD_SEND_COMMAND(0x282, 0); SLCD_SEND_COMMAND(REG_VCOM_HVOLTAGE2, 0);
SLCD_SEND_COMMAND(0x300, 0x101); SLCD_SEND_COMMAND(REG_GAMMA_CTRL1, 0x101);
SLCD_SEND_COMMAND(0x301, 0xb27); SLCD_SEND_COMMAND(REG_GAMMA_CTRL2, 0xb27);
SLCD_SEND_COMMAND(0x302, 0x132a); SLCD_SEND_COMMAND(REG_GAMMA_CTRL3, 0x132a);
SLCD_SEND_COMMAND(0x303, 0x2a13); SLCD_SEND_COMMAND(REG_GAMMA_CTRL4, 0x2a13);
SLCD_SEND_COMMAND(0x304, 0x270b); SLCD_SEND_COMMAND(REG_GAMMA_CTRL5, 0x270b);
SLCD_SEND_COMMAND(0x305, 0x101); SLCD_SEND_COMMAND(REG_GAMMA_CTRL6, 0x101);
SLCD_SEND_COMMAND(0x306, 0x1205); SLCD_SEND_COMMAND(REG_GAMMA_CTRL7, 0x1205);
SLCD_SEND_COMMAND(0x307, 0x512); SLCD_SEND_COMMAND(REG_GAMMA_CTRL8, 0x512);
SLCD_SEND_COMMAND(0x308, 5); SLCD_SEND_COMMAND(REG_GAMMA_CTRL9, 5);
SLCD_SEND_COMMAND(0x309, 3); SLCD_SEND_COMMAND(REG_GAMMA_CTRL10, 3);
SLCD_SEND_COMMAND(0x30a, 0xf04); SLCD_SEND_COMMAND(REG_GAMMA_CTRL11, 0xf04);
SLCD_SEND_COMMAND(0x30b, 0xf00); SLCD_SEND_COMMAND(REG_GAMMA_CTRL12, 0xf00);
SLCD_SEND_COMMAND(0x30c, 0xf); SLCD_SEND_COMMAND(REG_GAMMA_CTRL13, 0xf);
SLCD_SEND_COMMAND(0x30d, 0x40f); SLCD_SEND_COMMAND(REG_GAMMA_CTRL14, 0x40f);
SLCD_SEND_COMMAND(0x30e, 0x300); SLCD_SEND_COMMAND(0x30e, 0x300);
SLCD_SEND_COMMAND(0x30f, 0x500); SLCD_SEND_COMMAND(0x30f, 0x500);
SLCD_SEND_COMMAND(0x400, 0x3100); SLCD_SEND_COMMAND(REG_BIMG_NR_LINE, 0x3100);
SLCD_SEND_COMMAND(0x401, 1); SLCD_SEND_COMMAND(REG_BIMG_DISP_CTRL, 1);
SLCD_SEND_COMMAND(0x404, 0); SLCD_SEND_COMMAND(REG_BIMG_VSCROLL_CTRL, 0);
SLCD_SEND_COMMAND(0x500, 0); SLCD_SEND_COMMAND(REG_PARTIMG1_POS, 0);
SLCD_SEND_COMMAND(0x501, 0); SLCD_SEND_COMMAND(REG_PARTIMG1_RAM_START, 0);
SLCD_SEND_COMMAND(0x502, 0); SLCD_SEND_COMMAND(REG_PARTIMG1_RAM_END, 0);
SLCD_SEND_COMMAND(0x503, 0); SLCD_SEND_COMMAND(REG_PARTIMG2_POS, 0);
SLCD_SEND_COMMAND(0x504, 0); SLCD_SEND_COMMAND(REG_PARTIMG2_RAM_START, 0);
SLCD_SEND_COMMAND(0x505, 0); SLCD_SEND_COMMAND(REG_PARTIMG2_RAM_END, 0);
SLCD_SEND_COMMAND(0x606, 0); SLCD_SEND_COMMAND(REG_ENDIAN_CTRL, 0);
SLCD_SEND_COMMAND(0x6f0, 0); SLCD_SEND_COMMAND(REG_NVM_ACCESS_CTRL, 0);
SLCD_SEND_COMMAND(0x7f0, 0x5420); SLCD_SEND_COMMAND(0x7f0, 0x5420);
SLCD_SEND_COMMAND(0x7f3, 0x288a); SLCD_SEND_COMMAND(0x7f3, 0x288a);
SLCD_SEND_COMMAND(0x7f4, 0x22); SLCD_SEND_COMMAND(0x7f4, 0x22);
SLCD_SEND_COMMAND(0x7f5, 1); SLCD_SEND_COMMAND(0x7f5, 1);
SLCD_SEND_COMMAND(0x7f0, 0); SLCD_SEND_COMMAND(0x7f0, 0);
SLCD_SEND_COMMAND(7, 0x173); SLCD_SEND_COMMAND(REG_DISP_CTRL1, 0x173);
SLEEP(3500000); SLEEP(3500000);
SLCD_SEND_COMMAND(7, 0x171); SLCD_SEND_COMMAND(REG_DISP_CTRL1, 0x171);
SLEEP(3500000); SLEEP(3500000);
SLCD_SEND_COMMAND(7, 0x173); SLCD_SEND_COMMAND(REG_DISP_CTRL1, 0x173);
SLEEP(3500000); SLEEP(3500000);
} }
@ -181,13 +182,13 @@ void lcd_init_controller(void)
void lcd_set_target(short x, short y, short width, short height) void lcd_set_target(short x, short y, short width, short height)
{ {
SLCD_SEND_COMMAND(0x210, y); /* y_start */ SLCD_SEND_COMMAND(REG_RAM_HADDR_START, y); /* y_start */
SLCD_SEND_COMMAND(0x211, y+height); /* y_end */ SLCD_SEND_COMMAND(REG_RAM_HADDR_END, y+height); /* y_end */
SLCD_SEND_COMMAND(0x212, x); /* x_start */ SLCD_SEND_COMMAND(REG_RAM_VADDR_START, x); /* x_start */
SLCD_SEND_COMMAND(0x213, x+width); /* x_end */ SLCD_SEND_COMMAND(REG_RAM_VADDR_END, x+width); /* x_end */
SLCD_SEND_COMMAND(0x200, x); /* set cursor at x_start */ SLCD_SEND_COMMAND(REG_RAM_HADDR_SET, x); /* set cursor at x_start */
SLCD_SEND_COMMAND(0x201, y); /* set cursor at y_start */ SLCD_SEND_COMMAND(REG_RAM_VADDR_SET, y); /* set cursor at y_start */
SLCD_SET_COMMAND(0x202); /* write data? */ SLCD_SET_COMMAND(REG_RW_GRAM); /* write data to GRAM */
} }
void lcd_on(void) void lcd_on(void)