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I2C clock settings and ATA timing for iRiver

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@6206 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Linus Nielsen Feltzing 2005-03-18 11:36:48 +00:00
parent c11aa538bd
commit fbf8e14b3c
1 changed files with 18 additions and 9 deletions
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27
firmware/system.c
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@ -483,7 +483,7 @@ void set_cpu_frequency(long frequency)
DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass
frequency */ frequency */
PLLCR &= ~1; /* Bypass mode */ PLLCR &= ~1; /* Bypass mode */
PLLCR = 0x11853005; PLLCR = 0x11c53005;
CSCR0 = 0x00000980; /* Flash: 2 wait state */ CSCR0 = 0x00000980; /* Flash: 2 wait state */
CSCR1 = 0x00002580; /* LCD: 9 wait states */ CSCR1 = 0x00002580; /* LCD: 9 wait states */
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@ -491,15 +491,18 @@ void set_cpu_frequency(long frequency)
DCR = (DCR & ~0x000001ff) | 28; /* Refresh timer */ DCR = (DCR & ~0x000001ff) | 28; /* Refresh timer */
cpu_frequency = CPUFREQ_MAX; cpu_frequency = CPUFREQ_MAX;
tick_start(1000/HZ); tick_start(1000/HZ);
IDECONFIG1 = (IDECONFIG1 & ~(7 << 10)) | (5 << 10); /* CS2Pre,Post */ IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
IDECONFIG2 = (IDECONFIG2 & ~0x0000ff00) | (1 << 8); /* CS2wait */ IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */
/* I2C Clock divisor = 1280 => 119.952 MHz / 1280 = 93,7 kHz */
MFDR = 0x19;
MFDR2 = 0x19;
break; break;
case CPUFREQ_NORMAL: case CPUFREQ_NORMAL:
DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass
frequency */ frequency */
PLLCR &= ~1; /* Bypass mode */ PLLCR &= ~1; /* Bypass mode */
PLLCR = 0x10c86801; PLLCR = 0x10c86001;
CSCR0 = 0x00000180; /* Flash: 0 wait states */ CSCR0 = 0x00000180; /* Flash: 0 wait states */
CSCR1 = 0x00000980; /* LCD: 2 wait states */ CSCR1 = 0x00000980; /* LCD: 2 wait states */
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
@ -507,19 +510,25 @@ void set_cpu_frequency(long frequency)
DCR = (DCR & ~0x000001ff) | 10; /* Refresh timer */ DCR = (DCR & ~0x000001ff) | 10; /* Refresh timer */
cpu_frequency = CPUFREQ_NORMAL; cpu_frequency = CPUFREQ_NORMAL;
tick_start(1000/HZ); tick_start(1000/HZ);
IDECONFIG1 = (IDECONFIG1 & ~(7 << 10)) | (5 << 10); /* CS2Pre,Post */ IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
IDECONFIG2 = (IDECONFIG2 & ~0x0000ff00) | (0 << 8); /* CS2wait */ IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
/* I2C Clock divisor = 480 => 47.9808 MHz / 480 = 99,9 kHz */
MFDR = 0x13;
MFDR2 = 0x13;
break; break;
default: default:
DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass DCR = (DCR & ~0x000001ff) | 1; /* Refresh timer for bypass
frequency */ frequency */
PLLCR &= ~1; /* Bypass mode */ PLLCR = 0x00400000; /* Bypass mode */
CSCR0 = 0x00000180; /* Flash: 0 wait states */ CSCR0 = 0x00000180; /* Flash: 0 wait states */
CSCR1 = 0x00000180; /* LCD: 0 wait states */ CSCR1 = 0x00000180; /* LCD: 0 wait states */
cpu_frequency = CPU_FREQ; cpu_frequency = CPU_FREQ;
tick_start(1000/HZ); tick_start(1000/HZ);
IDECONFIG1 = (IDECONFIG1 & ~(7 << 10)) | (1 << 10); /* CS2Pre,Post */ IDECONFIG1 = 0x106000 | (1 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
IDECONFIG2 = (IDECONFIG2 & ~0x0000ff00) | (0 << 8); /* CS2wait */ IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
/* I2C Clock divisor = 480 => 47.9808 MHz / 480 = 99,9 kHz */
MFDR = 0x13;
MFDR2 = 0x13;
break; break;
} }
} }