forked from len0rd/rockbox
Implement driver for internal codec in rk27xx (shCODlp-100.01-HD IP core from Dolphin)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30439 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Marcin Bukat
parent
2afc175a4e
commit
fa856468ab
2 changed files with 328 additions and 0 deletions
160
firmware/drivers/audio/rk27xx_codec.c
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160
firmware/drivers/audio/rk27xx_codec.c
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Driver for internal Rockchip rk27xx audio codec
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* (shCODlp-100.01-HD IP core from Dolphin)
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*
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* Copyright (c) 2011 Marcin Bukat
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "kernel.h"
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#include "audio.h"
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#include "audiohw.h"
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#include "system.h"
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#include "i2c-rk27xx.h"
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const struct sound_settings_info audiohw_settings[] = {
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[SOUND_VOLUME] = {"dB", 1, 5,-335, 45,-255},
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/* HAVE_SW_TONE_CONTROLS */
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[SOUND_BASS] = {"dB", 0, 1, -24, 24, 0},
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[SOUND_TREBLE] = {"dB", 0, 1, -24, 24, 0},
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[SOUND_BALANCE] = {"%", 0, 1,-100, 100, 0},
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[SOUND_CHANNELS] = {"", 0, 1, 0, 5, 0},
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[SOUND_STEREO_WIDTH] = {"%", 0, 5, 0, 250, 100},
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#ifdef HAVE_RECORDING /* disabled for now */
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[SOUND_LEFT_GAIN] = {"dB", 2, 75, -1725, 3000, 0},
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[SOUND_RIGHT_GAIN] = {"dB", 2, 75, -1725, 3000, 0},
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[SOUND_MIC_GAIN] = {"dB", 0, 1, 0, 20, 20},
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#endif
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};
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/* private functions to read/write codec registers */
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static int codec_write(uint8_t reg, uint8_t val)
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{
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return i2c_write(CODEC_I2C_ADDR, reg, 1, &val);
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}
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#if 0
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static int codec_read(uint8_t reg, uint8_t *val)
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{
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return i2c_read(CODEC_I2C_ADDR, reg, 1, val);
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}
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#endif
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static void audiohw_mute(bool mute)
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{
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if (mute)
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codec_write(CR1, SB_MICBIAS|DAC_MUTE|DACSEL);
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else
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codec_write(CR1, SB_MICBIAS|DACSEL);
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}
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/* public functions */
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int tenthdb2master(int tdb)
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{
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/* we lie here a bit and present 0.5dB gain steps
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* but codec has 'variable' gain steps (0.5, 1.0, 2.0)
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* depending on gain region.
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*/
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if (tdb < VOLUME_MIN)
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return 31;
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else if (tdb < -115)
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return -(((tdb + 115)/20) - 20); /* 2.0 dB steps */
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else if (tdb < 5)
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return -(((tdb + 5)/10) - 9); /* 1.0 dB steps */
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else
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return -((tdb - 45)/5); /* 0.5 dB steps */
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}
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void audiohw_preinit(void)
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{
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/* PD7 output low */
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GPIO_PDDR &= ~(1<<7);
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GPIO_PDCON |= (1<<7);
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codec_write(PMR2, SB_SLEEP|GIM|SB_MC);
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codec_write(AICR, DAC_SERIAL|ADC_SERIAL|DAC_I2S|ADC_I2S);
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codec_write(CR1, SB_MICBIAS|DAC_MUTE|DACSEL);
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codec_write(CR2, ADC_HPF);
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codec_write(CCR1, CRYSTAL_12M);
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codec_write(CCR2, (FREQ44100 << 4)|FREQ44100);
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codec_write(CRR, RATIO_8|KFAST_32|THRESHOLD_128);
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codec_write(TR1, NOSC);
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}
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void audiohw_postinit(void)
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{
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codec_write(PMR1, SB_OUT|SB_MIX|SB_ADC|SB_IN1|SB_IN2|SB_MIC|SB_IND);
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udelay(10000);
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codec_write(PMR2, GIM | SB_MC);
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udelay(10000);
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codec_write(PMR1, SB_OUT|SB_ADC|SB_IN1|SB_IN2|SB_MIC|SB_IND);
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udelay(10000);
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codec_write(PMR1, SB_ADC|SB_IN1|SB_IN2|SB_MIC|SB_IND);
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sleep(3*HZ);
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GPIO_PDDR |= (1<<7); /* PD7 high */
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sleep(HZ/10);
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audiohw_mute(false);
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}
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void audiohw_close(void)
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{
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/* stub */
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}
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void audiohw_set_frequency(int fsel)
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{
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static const unsigned char values_freq[HW_NUM_FREQ] =
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{
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HW_HAVE_8_([HW_FREQ_8] = (FREQ8000<<4)|FREQ8000,)
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HW_HAVE_11_([HW_FREQ_11] = (FREQ11025<<4)|FREQ11025,)
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HW_HAVE_12_([HW_FREQ_12] = (FREQ12000<<4)|FREQ12000,)
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HW_HAVE_16_([HW_FREQ_16] = (FREQ16000<<4)|FREQ16000,)
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HW_HAVE_22_([HW_FREQ_22] = (FREQ22050<<4)|FREQ22050,)
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HW_HAVE_24_([HW_FREQ_24] = (FREQ24000<<4)|FREQ24000,)
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HW_HAVE_32_([HW_FREQ_32] = (FREQ32000<<4)|FREQ32000,)
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HW_HAVE_44_([HW_FREQ_44] = (FREQ44100<<4)|FREQ44100,)
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HW_HAVE_48_([HW_FREQ_48] = (FREQ48000<<4)|FREQ48000,)
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HW_HAVE_96_([HW_FREQ_96] = (FREQ96000<<4)|FREQ96000,)
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};
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if ((unsigned)fsel >= HW_NUM_FREQ)
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fsel = HW_FREQ_DEFAULT;
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/* we setup the same sampling freq for DAC and ADC */
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codec_write(CCR2, values_freq[fsel]);
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}
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void audiohw_set_master_vol(int vol_l, int vol_r)
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{
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uint8_t val;
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val = (uint8_t)(vol_r & 0x1f);
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codec_write(CGR9, val);
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val = (uint8_t)(vol_l & 0x1f);
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codec_write(CGR8, val);
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}
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168
firmware/export/rk27xx_codec.h
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168
firmware/export/rk27xx_codec.h
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@ -0,0 +1,168 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Driver for internal Rockchip rk27xx audio codec
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* (shCODlp-100.01-HD IP core from Dolphin)
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*
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* Copyright (c) 2011 Marcin Bukat
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef _RK27XX_CODEC_H_
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#define _RK27XX_CODEC_H_
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#define VOLUME_MIN -335
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#define VOLUME_MAX 45
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#define AUDIOHW_CAPS (BASS_CAP | TREBLE_CAP)
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extern int tenthdb2master(int db);
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extern void audiohw_set_master_vol(int vol_l, int vol_r);
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#define CODEC_I2C_ADDR 0x4e
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/* registers */
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#define AICR 0x00 /* Audio Interface Control */
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#define DAC_SERIAL (1<<3)
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#define ADC_SERIAL (1<<2)
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#define DAC_I2S (1<<1)
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#define ADC_I2S (1<<0)
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#define CR1 0x02 /* Control Register 1 */
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#define SB_MICBIAS (1<<7)
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#define CR1_MONO (1<<6)
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#define DAC_MUTE (1<<5)
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#define HP_DIS (1<<4)
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#define DACSEL (1<<3)
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#define BYPASS1 (1<<2)
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#define BYPASS2 (1<<1)
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#define SIDETONE (1<<0)
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#define CR2 0x04 /* Control Register 2 */
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#define DAC_DEEMP (1<<7)
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#define ADC_HPF (1<<2)
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#define INSEL_MIX (3<<0)
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#define INSEL_MIC (2<<0)
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#define INSEL_LINE2 (1<<0)
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#define INSEL_LINE1 (0<<0)
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#define CCR1 0x06 /* Control Clock Register 1 */
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#define CRYSTAL_16M (1<<0)
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#define CRYSTAL_12M (0<<0)
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#define CCR2 0x08 /* Control Clock Register 2 */
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#define FREQ8000 0x0a
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#define FREQ9600 0x09
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#define FREQ11025 0x08
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#define FREQ12000 0x07
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#define FREQ16000 0x06
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#define FREQ22050 0x05
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#define FREQ24000 0x04
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#define FREQ32000 0x03
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#define FREQ44100 0x02
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#define FREQ48000 0x01
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#define FREQ96000 0x00
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#define PMR1 0x0a /* Power Mode Register 1 */
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#define SB_DAC (1<<7)
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#define SB_OUT (1<<6)
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#define SB_MIX (1<<5)
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#define SB_ADC (1<<4)
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#define SB_IN1 (1<<3)
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#define SB_IN2 (1<<2)
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#define SB_MIC (1<<1)
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#define SB_IND (1<<0)
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#define PMR2 0x0c /* Power Mode Register 1 */
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#define LRGI (1<<7)
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#define RLGI (1<<6)
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#define LRGOD (1<<5)
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#define RLGOD (1<<4)
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#define GIM (1<<3)
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#define SB_MC (1<<2)
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#define SB (1<<1)
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#define SB_SLEEP (1<<0)
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#define CRR 0x0e /* Control Ramp Register */
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#define RATIO_8 (3<<5)
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#define RATIO_4 (2<<5)
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#define RATIO_2 (1<<5)
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#define RATIO_1 (0<<5)
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#define KFAST_32 (5<<2)
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#define KFAST_16 (4<<2)
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#define KFAST_8 (3<<2)
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#define KFAST_4 (2<<2)
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#define KFAST_2 (1<<2)
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#define KFAST_1 (0<<2)
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#define THRESHOLD_128 (3<<0)
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#define THRESHOLD_64 (2<<0)
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#define THRESHOLD_32 (1<<0)
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#define THRESHOLD_0 (0<<0)
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#define ICR 0x10 /* Interrupt Control Register */
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#define IRQ_LOW_PULSE (3<<6)
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#define IRQ_HIGH_PULSE (2<<6)
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#define IRQ_LOW (1<<6)
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#define IRQ_HIGH (0<<6)
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#define JACK_MASK (1<<5)
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#define CCMC_MASK (1<<4)
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#define RUD_MASK (1<<3)
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#define RDD_MASK (1<<2)
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#define GUD_MASK (1<<1)
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#define GDD_MASK (1<<0)
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#define IFR 0x12 /* Interrupt Flag Register */
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#define JACK (1<<6)
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#define JACK_EVENT (1<<5)
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#define CCMC (1<<4)
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#define RAMP_UP_DONE (1<<3)
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#define RAMP_DOWN_DONE (1<<2)
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#define GAIN_UP_DONE (1<<1)
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#define GAIN_DOWN_DONE (1<<0)
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#define CGR1 0x14 /* Control Gain Register 1 (DAC mixing) */
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#define CGR2 0x16 /* Control Gain Register 2 (LINE1 mixing) */
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#define LRGOB1 (1<<7)
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#define RLGOB1 (1<<6)
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#define CGR3 0x18 /* Control Gain Register 3 (LINE1 mixing) */
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#define CGR4 0x1a /* Control Gain Register 4 (LINE2 mixing) */
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#define LRGOB2 (1<<7)
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#define RLGOB2 (1<<6)
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#define CGR5 0x1c /* Control Gain Register 5 (LINE2 mixing) */
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#define CGR6 0x1e /* Control Gain Register 6 (MIC mixing) */
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#define LRGOS (1<<7)
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#define RLGOS (1<<6)
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#define CGR7 0x20 /* Control Gain Register 7 (MIC mixing) */
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#define CGR8 0x22 /* Control Gain Register 8 (OUT STAGE gain) */
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#define LRGO (1<<7)
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#define RLGO (1<<6)
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#define CGR9 0x24 /* Control Gain Register 9 (OUT STAGE gain) */
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#define CGR10 0x26 /* Control Gain Register 10 (ADC input gain) */
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#define TR1 0x28 /* undocumented */
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#define NOSC (1<<1)
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#define TR2 0x2a /* undocumented */
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#endif /* _RK27XX_CODEC_H_ */
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