forked from len0rd/rockbox
Add codecs to librbcodec.
Change-Id: Id7f4717d51ed02d67cb9f9cb3c0ada4a81843f97 Reviewed-on: http://gerrit.rockbox.org/137 Reviewed-by: Nils Wallménius <nils@rockbox.org> Tested-by: Nils Wallménius <nils@rockbox.org>
This commit is contained in:
Sean Bartell
Nils Wallménius
parent
a0009907de
commit
f40bfc9267
757 changed files with 122 additions and 122 deletions
340
lib/rbcodec/codecs/libmad/synth_full_arm.S
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340
lib/rbcodec/codecs/libmad/synth_full_arm.S
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by Tomasz Malesinski
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "mad_iram.h"
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.section ICODE_SECTION_MPA_ARM,"ax",%progbits
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.global synth_full_odd_sbsample
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.global synth_full_even_sbsample
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/*
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;; r0 = pcm (pushed on the stack to free a register)
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;; r1 = fo
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;; r2 = fe
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;; r3 = D0ptr
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;; r4 = D1ptr
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;; r5 = loop counter
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;; r6,r7 accumulator1
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;; r8,r9 accumulator2
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*/
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synth_full_odd_sbsample:
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stmdb sp!, {r0, r4-r11, lr}
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ldr r4, [sp, #40]
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mov r5, #15
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add r2, r2, #32
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.l:
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/* ;; PROD_O and odd half of SB_SAMPLE*/
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add r3, r3, #128
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add r4, r4, #128
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ldr r7, [r3, #4]
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ldmia r1!, {r0, r10, r11, lr}
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ldr r9, [r4, #120]
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smull r6, r7, r0, r7
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ldr r12, [r3, #60]
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smull r8, r9, r0, r9
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ldr r0, [r3, #52]
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smlal r6, r7, r10, r12
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ldr r12, [r3, #44]
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smlal r6, r7, r11, r0
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ldr r0, [r4, #64]
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smlal r6, r7, lr, r12
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ldr r12, [r4, #72]
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smlal r8, r9, r10, r0
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ldr r0, [r4, #80]
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smlal r8, r9, r11, r12
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smlal r8, r9, lr, r0
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ldr r0, [r3, #36]
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ldmia r1!, {r10, r11, r12, lr}
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smlal r6, r7, r10, r0
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ldr r0, [r4, #88] /*;;1 cycle stall on arm9, but we free up r10*/
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smlal r8, r9, r10, r0
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ldr r0, [r3, #28]
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ldr r10, [r3, #20]
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smlal r6, r7, r11, r0
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ldr r0, [r3, #12]
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smlal r6, r7, r12, r10
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ldr r10, [r4, #96]
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smlal r6, r7, lr, r0
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ldr r0, [r4, #104]
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smlal r8, r9, r11, r10
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ldr r10, [r4, #112]
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smlal r8, r9, r12, r0
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smlal r8, r9, lr, r10
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rsbs r6, r6, #0
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rsc r7, r7, #0
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/* ;; PROD_A and even half of SB_SAMPLE*/
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ldr r0, [r3, #0]
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ldmia r2!, {r10, r11, r12, lr}
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smlal r6, r7, r10, r0
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ldr r0, [r4, #60] /*;;1 cycle stall on arm9, but we free up r10*/
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smlal r8, r9, r10, r0
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ldr r10, [r3, #56]
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ldr r0, [r3, #48]
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smlal r6, r7, r11, r10
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ldr r10, [r3, #40]
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smlal r6, r7, r12, r0
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ldr r0, [r4, #68]
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smlal r6, r7, lr, r10
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ldr r10, [r4, #76]
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smlal r8, r9, r11, r0
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ldr r0, [r4, #84]
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smlal r8, r9, r12, r10
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smlal r8, r9, lr, r0
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ldr r0, [r3, #32]
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ldmia r2!, {r10, r11, r12, lr}
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smlal r6, r7, r10, r0
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ldr r0, [r4, #92] /*;;1 cycle stall on arm9, but we free up r10*/
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smlal r8, r9, r10, r0
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ldr r0, [r3, #24]
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ldr r10, [r3, #16]
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smlal r6, r7, r11, r0
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ldr r0, [r3, #8]
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smlal r6, r7, r12, r10
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ldr r10, [r4, #100]
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smlal r6, r7, lr, r0
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ldr r0, [r4, #108]
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smlal r8, r9, r11, r10
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ldr r10, [r4, #116]
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smlal r8, r9, r12, r0
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smlal r8, r9, lr, r10
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ldr r0, [sp]
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movs r6, r6, lsr #16
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adc r6, r6, r7, lsl #16
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str r6, [r0, -r5, lsl #2]
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movs r8, r8, lsr #16
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adc r8, r8, r9, lsl #16
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str r8, [r0, r5, lsl #2]
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subs r5, r5, #1
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bne .l
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ldmpc regs="r0,r4-r11"
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synth_full_even_sbsample:
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stmdb sp!, {r0, r4-r11, lr}
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ldr r4, [sp, #40]
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mov r5, #15
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add r2, r2, #32
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.l2:
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/* ;; PROD_O and odd half of SB_SAMPLE*/
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add r3, r3, #128
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add r4, r4, #128
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ldr r7, [r3, #0]
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ldmia r1!, {r0, r10, r11, lr}
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ldr r9, [r4, #60]
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smull r6, r7, r0, r7
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ldr r12, [r3, #56]
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smull r8, r9, r0, r9
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ldr r0, [r3, #48]
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smlal r6, r7, r10, r12
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ldr r12, [r3, #40]
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smlal r6, r7, r11, r0
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ldr r0, [r4, #68]
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smlal r6, r7, lr, r12
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ldr r12, [r4, #76]
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smlal r8, r9, r10, r0
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ldr r0, [r4, #84]
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smlal r8, r9, r11, r12
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smlal r8, r9, lr, r0
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ldr r0, [r3, #32]
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ldmia r1!, {r10, r11, r12, lr}
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smlal r6, r7, r10, r0
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ldr r0, [r4, #92]
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smlal r8, r9, r10, r0
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ldr r0, [r3, #24]
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ldr r10, [r3, #16]
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smlal r6, r7, r11, r0
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ldr r0, [r3, #8]
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smlal r6, r7, r12, r10
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ldr r10, [r4, #100]
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smlal r6, r7, lr, r0
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ldr r0, [r4, #108]
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smlal r8, r9, r11, r10
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ldr r10, [r4, #116]
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smlal r8, r9, r12, r0
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smlal r8, r9, lr, r10
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rsbs r6, r6, #0
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rsc r7, r7, #0
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ldr r0, [r3, #4]
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ldmia r2!, {r10, r11, r12, lr}
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smlal r6, r7, r10, r0
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ldr r0, [r4, #120] /*;;1 cycle stall on arm9, but we free up r10*/
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smlal r8, r9, r10, r0
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ldr r0, [r3, #60]
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ldr r10, [r3, #52]
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smlal r6, r7, r11, r0
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ldr r0, [r3, #44]
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smlal r6, r7, r12, r10
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ldr r10, [r4, #64]
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smlal r6, r7, lr, r0
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ldr r0, [r4, #72]
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smlal r8, r9, r11, r10
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ldr r10, [r4, #80]
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smlal r8, r9, r12, r0
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smlal r8, r9, lr, r10
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ldr r0, [r3, #36]
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ldmia r2!, {r10, r11, r12, lr}
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smlal r6, r7, r10, r0
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ldr r0, [r4, #88] /*;;1 cycle stall on arm9, but we free up r10*/
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smlal r8, r9, r10, r0
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ldr r0, [r3, #28]
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ldr r10, [r3, #20]
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smlal r6, r7, r11, r0
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ldr r0, [r3, #12]
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smlal r6, r7, r12, r10
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ldr r10, [r4, #96]
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smlal r6, r7, lr, r0
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ldr r0, [r4, #104]
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smlal r8, r9, r11, r10
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ldr r10, [r4, #112]
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smlal r8, r9, r12, r0
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smlal r8, r9, lr, r10
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ldr r0, [sp]
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movs r6, r6, lsr #16
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adc r6, r6, r7, lsl #16
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str r6, [r0, -r5, lsl #2]
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movs r8, r8, lsr #16
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adc r8, r8, r9, lsl #16
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str r8, [r0, r5, lsl #2]
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subs r5, r5, #1
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bne .l2
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ldmpc regs="r0,r4-r11"
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.global III_aliasreduce
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III_aliasreduce:
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stmdb sp!, {r4-r11, lr}
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add r1, r0, r1, lsl #2
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add r0, r0, #72
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.arl1:
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mov r2, #8
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mov r3, r0 @ a
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mov r4, r0 @ b
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ldr r5, =csa @ cs/ca
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.arl2:
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ldmdb r3, {r6, r12}
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ldmia r4, {r7, lr}
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ldmia r5!, {r8, r9}
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smull r10, r11, r7, r8
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smlal r10, r11, r12, r9
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movs r10, r10, lsr #28
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adc r10, r10, r11, lsl #4
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rsb r7, r7, #0
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smull r11, r8, r12, r8
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smlal r11, r8, r7, r9
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movs r11, r11, lsr #28
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adc r11, r11, r8, lsl #4
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ldmia r5!, {r8, r9}
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smull r12, r7, lr, r8
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smlal r12, r7, r6, r9
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movs r12, r12, lsr #28
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adc r12, r12, r7, lsl #4
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stmia r4!, {r10, r12}
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rsb lr, lr, #0
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smull r7, r10, r6, r8
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smlal r7, r10, lr, r9
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movs r7, r7, lsr #28
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adc r7, r7, r10, lsl #4
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stmdb r3!, {r7, r11}
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subs r2, r2, #2
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bne .arl2
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add r0, r0, #72
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cmp r0, r1
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blo .arl1
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ldmpc regs=r4-r11
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csa:
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.word +0x0db84a81
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.word -0x083b5fe7
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.word +0x0e1b9d7f
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.word -0x078c36d2
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.word +0x0f31adcf
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.word -0x05039814
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.word +0x0fbba815
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.word -0x02e91dd1
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.word +0x0feda417
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.word -0x0183603a
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.word +0x0ffc8fc8
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.word -0x00a7cb87
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.word +0x0fff964c
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.word -0x003a2847
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.word +0x0ffff8d3
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.word -0x000f27b4
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.global III_overlap
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III_overlap:
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stmdb sp!, {r4-r7, lr}
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add r2, r2, r3, lsl #2
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mov r3, #6
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.ol:
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ldmia r0!, {r4, r5, r6}
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ldmia r1!, {r7, r12, lr}
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add r4, r4, r7
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add r5, r5, r12
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add r6, r6, lr
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str r4, [r2], #128
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str r5, [r2], #128
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str r6, [r2], #128
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subs r3, r3, #1
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bne .ol
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sub r1, r1, #72
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ldmia r0!, {r4, r5, r6, r7, r12, lr}
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stmia r1!, {r4, r5, r6, r7, r12, lr}
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ldmia r0!, {r4, r5, r6, r7, r12, lr}
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stmia r1!, {r4, r5, r6, r7, r12, lr}
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ldmia r0!, {r4, r5, r6, r7, r12, lr}
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stmia r1!, {r4, r5, r6, r7, r12, lr}
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ldmpc regs=r4-r7
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