forked from len0rd/rockbox
Added serial port bit definitions
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@157 a1c6a512-1295-4272-9138-f99709370657
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@ -291,4 +291,46 @@
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#define CASCR (*((volatile unsigned char*)CASCR_ADDR))
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/***************************************************************************
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* Register bit definitions
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**************************************************************************/
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/*
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* Serial mode register bits
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*/
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#define SYNC_MODE 0x80
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#define SEVEN_BIT_DATA 0x40
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#define PARITY_ON 0x20
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#define ODD_PARITY 0x10
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#define STOP_BITS_2 0x08
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#define ENABLE_MULTIP 0x04
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#define PHI_64 0x03
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#define PHI_16 0x02
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#define PHI_4 0x01
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/*
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* Serial control register bits
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*/
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#define SCI_TIE 0x80 /* Transmit interrupt enable */
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#define SCI_RIE 0x40 /* Receive interrupt enable */
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#define SCI_TE 0x20 /* Transmit enable */
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#define SCI_RE 0x10 /* Receive enable */
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#define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */
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#define SCI_TEIE 0x04 /* Transmit end interrupt enable */
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#define SCI_CKE1 0x02 /* Clock enable 1 */
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#define SCI_CKE0 0x01 /* Clock enable 0 */
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/*
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* Serial status register bits
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*/
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#define SCI_TDRE 0x80 /* Transmit data register empty */
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#define SCI_RDRF 0x40 /* Receive data register full */
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#define SCI_ORER 0x20 /* Overrun error */
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#define SCI_FER 0x10 /* Framing error */
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#define SCI_PER 0x08 /* Parity error */
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#define SCI_TEND 0x04 /* Transmit end */
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#define SCI_MPB 0x02 /* Multiprocessor bit */
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#define SCI_MPBT 0x01 /* Multiprocessor bit transfer */
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#endif
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