forked from len0rd/rockbox
Moved coldfire code in system.c and system.h into target tree.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11399 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis
parent
522da3a677
commit
f29cae0d26
5 changed files with 437 additions and 390 deletions
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@ -45,6 +45,7 @@ target/coldfire/memcpy-coldfire.S
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target/coldfire/memmove-coldfire.S
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target/coldfire/memset-coldfire.S
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target/coldfire/memset16-coldfire.S
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target/coldfire/system-coldfire.c
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#elif (CONFIG_CPU == SH7034)
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target/sh/memcpy-sh.S
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target/sh/memmove-sh.S
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@ -153,6 +153,11 @@ enum {
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MAXMEMGUARD
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};
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#ifndef SIMULATOR
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#ifdef CPU_COLDFIRE
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#include "system-target.h"
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#endif
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#endif
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#if CONFIG_CPU == SH7034
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#define or_b(mask, address) \
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@ -176,46 +181,7 @@ enum {
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: /* %0 */ I_CONSTRAINT((char)(mask)), \
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/* %1 */ "z"(address-GBR))
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#elif defined(CPU_COLDFIRE)
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#define or_l(mask, address) \
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asm \
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("or.l %0,(%1)" \
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: \
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: /* %0 */ "d"(mask), \
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/* %1 */ "a"(address))
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#define and_l(mask, address) \
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asm \
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("and.l %0,(%1)" \
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: \
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: /* %0 */ "d"(mask), \
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/* %1 */ "a"(address))
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#define eor_l(mask, address) \
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asm \
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("eor.l %0,(%1)" \
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: \
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: /* %0 */ "d"(mask), \
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/* %1 */ "a"(address))
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#define EMAC_ROUND 0x10
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#define EMAC_FRACTIONAL 0x20
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#define EMAC_SATURATE 0x80
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static inline void coldfire_set_macsr(unsigned long flags)
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{
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asm volatile ("move.l %0, %%macsr" : : "i,r" (flags));
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}
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static inline unsigned long coldfire_get_macsr(void)
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{
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unsigned long m;
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asm volatile ("move.l %%macsr, %0" : "=r" (m));
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return m;
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}
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#endif
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#endif /* CONFIG_CPU == SH7034 */
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#ifndef SIMULATOR
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@ -272,75 +238,6 @@ static inline unsigned long swap32(unsigned long value)
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#define invalidate_icache()
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#elif defined(CPU_COLDFIRE)
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#define HIGHEST_IRQ_LEVEL (7<<8)
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static inline int set_irq_level(int level)
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{
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int oldlevel;
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/* Read the old level and set the new one */
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asm volatile ("move.w %%sr,%0\n"
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"or.l #0x2000,%1\n"
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"move.w %1,%%sr\n" : "=d" (oldlevel), "+d" (level) : );
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return oldlevel;
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}
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static inline unsigned short swap16(unsigned short value)
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/*
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result[15..8] = value[ 7..0];
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result[ 7..0] = value[15..8];
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*/
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{
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return (value >> 8) | (value << 8);
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}
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static inline unsigned long SWAW32(unsigned long value)
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/*
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result[31..16] = value[15.. 0];
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result[15.. 0] = value[31..16];
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*/
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{
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asm ("swap %%0" : "+r"(value));
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return value;
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}
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static inline unsigned long swap32(unsigned long value)
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/*
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result[31..24] = value[ 7.. 0];
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result[23..16] = value[15.. 8];
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result[15.. 8] = value[23..16];
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result[ 7.. 0] = value[31..24];
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*/
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{
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unsigned long mask = 0x00FF00FF;
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asm ( /* val = ABCD */
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"and.l %[val],%[mask] \n" /* mask = .B.D */
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"eor.l %[mask],%[val] \n" /* val = A.C. */
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"lsl.l #8,%[mask] \n" /* mask = B.D. */
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"lsr.l #8,%[val] \n" /* val = .A.C */
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"or.l %[mask],%[val] \n" /* val = BADC */
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"swap %[val] \n" /* val = DCBA */
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: /* outputs */
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[val] "+d"(value),
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[mask]"+d"(mask)
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);
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return value;
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}
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static inline void invalidate_icache(void)
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{
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asm volatile ("move.l #0x01000000,%d0\n"
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"movec.l %d0,%cacr\n"
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"move.l #0x80000000,%d0\n"
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"movec.l %d0,%cacr");
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}
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#define CPUFREQ_DEFAULT_MULT 1
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#define CPUFREQ_DEFAULT (CPUFREQ_DEFAULT_MULT * CPU_FREQ)
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#define CPUFREQ_NORMAL_MULT 4
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#define CPUFREQ_NORMAL (CPUFREQ_NORMAL_MULT * CPU_FREQ)
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#define CPUFREQ_MAX_MULT 11
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#define CPUFREQ_MAX (CPUFREQ_MAX_MULT * CPU_FREQ)
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#elif defined(CPU_ARM)
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/* TODO: Implement set_irq_level and check CPU frequencies */
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@ -391,285 +391,7 @@ int system_memory_guard(int newmode)
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return 0;
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}
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#elif defined(CPU_COLDFIRE)
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#include "pcf50606.h"
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#define default_interrupt(name) \
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extern __attribute__((weak,alias("UIE"))) void name (void)
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static const char* const irqname[] = {
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"", "", "AccessErr","AddrErr","IllInstr", "", "","",
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"PrivVio","Trace","Line-A", "Line-F","Debug","","FormErr","Uninit",
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"","","","","","","","",
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"Spurious","Level1","Level2","Level3","Level4","Level5","Level6","Level7",
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"Trap0","Trap1","Trap2","Trap3","Trap4","Trap5","Trap6","Trap7",
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"Trap8","Trap9","Trap10","Trap11","Trap12","Trap13","Trap14","Trap15",
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"SWT","Timer0","Timer1","I2C","UART1","UART2","DMA0","DMA1",
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"DMA2","DMA3","QSPI","","","","","",
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"PDIR1FULL","PDIR2FULL","EBUTXEMPTY","IIS2TXEMPTY",
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"IIS1TXEMPTY","PDIR3FULL","PDIR3RESYN","UQ2CHANERR",
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"AUDIOTICK","PDIR2RESYN","PDIR2UNOV","PDIR1RESYN",
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"PDIR1UNOV","UQ1CHANERR","IEC2BUFATTEN","IEC2PARERR",
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"IEC2VALNOGOOD","IEC2CNEW","IEC1BUFATTEN","UCHANTXNF",
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"UCHANTXUNDER","UCHANTXEMPTY","PDIR3UNOV","IEC1PARERR",
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"IEC1VALNOGOOD","IEC1CNEW","EBUTXRESYN","EBUTXUNOV",
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"IIS2TXRESYN","IIS2TXUNOV","IIS1TXRESYN","IIS1TXUNOV",
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"GPI0","GPI1","GPI2","GPI3","GPI4","GPI5","GPI6","GPI7",
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"","","","","","","","SOFTINT0",
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"SOFTINT1","SOFTINT2","SOFTINT3","",
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"","CDROMCRCERR","CDROMNOSYNC","CDROMILSYNC",
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"CDROMNEWBLK","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","",""
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};
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default_interrupt (TRAP0); /* Trap #0 */
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default_interrupt (TRAP1); /* Trap #1 */
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default_interrupt (TRAP2); /* Trap #2 */
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default_interrupt (TRAP3); /* Trap #3 */
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default_interrupt (TRAP4); /* Trap #4 */
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default_interrupt (TRAP5); /* Trap #5 */
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default_interrupt (TRAP6); /* Trap #6 */
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default_interrupt (TRAP7); /* Trap #7 */
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default_interrupt (TRAP8); /* Trap #8 */
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default_interrupt (TRAP9); /* Trap #9 */
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default_interrupt (TRAP10); /* Trap #10 */
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default_interrupt (TRAP11); /* Trap #11 */
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default_interrupt (TRAP12); /* Trap #12 */
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default_interrupt (TRAP13); /* Trap #13 */
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default_interrupt (TRAP14); /* Trap #14 */
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default_interrupt (TRAP15); /* Trap #15 */
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default_interrupt (SWT); /* Software Watchdog Timer */
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default_interrupt (TIMER0); /* Timer 0 */
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default_interrupt (TIMER1); /* Timer 1 */
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default_interrupt (I2C); /* I2C */
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default_interrupt (UART1); /* UART 1 */
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default_interrupt (UART2); /* UART 2 */
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default_interrupt (DMA0); /* DMA 0 */
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default_interrupt (DMA1); /* DMA 1 */
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default_interrupt (DMA2); /* DMA 2 */
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default_interrupt (DMA3); /* DMA 3 */
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default_interrupt (QSPI); /* QSPI */
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default_interrupt (PDIR1FULL); /* Processor data in 1 full */
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default_interrupt (PDIR2FULL); /* Processor data in 2 full */
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default_interrupt (EBUTXEMPTY); /* EBU transmit FIFO empty */
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default_interrupt (IIS2TXEMPTY); /* IIS2 transmit FIFO empty */
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default_interrupt (IIS1TXEMPTY); /* IIS1 transmit FIFO empty */
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default_interrupt (PDIR3FULL); /* Processor data in 3 full */
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default_interrupt (PDIR3RESYN); /* Processor data in 3 resync */
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default_interrupt (UQ2CHANERR); /* IEC958-2 Rx U/Q channel error */
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default_interrupt (AUDIOTICK); /* "tick" interrupt */
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default_interrupt (PDIR2RESYN); /* Processor data in 2 resync */
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default_interrupt (PDIR2UNOV); /* Processor data in 2 under/overrun */
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default_interrupt (PDIR1RESYN); /* Processor data in 1 resync */
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default_interrupt (PDIR1UNOV); /* Processor data in 1 under/overrun */
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default_interrupt (UQ1CHANERR); /* IEC958-1 Rx U/Q channel error */
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default_interrupt (IEC2BUFATTEN);/* IEC958-2 channel buffer full */
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default_interrupt (IEC2PARERR); /* IEC958-2 Rx parity or symbol error */
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default_interrupt (IEC2VALNOGOOD);/* IEC958-2 flag not good */
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default_interrupt (IEC2CNEW); /* IEC958-2 New C-channel received */
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default_interrupt (IEC1BUFATTEN);/* IEC958-1 channel buffer full */
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default_interrupt (UCHANTXNF); /* U channel Tx reg next byte is first */
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default_interrupt (UCHANTXUNDER);/* U channel Tx reg underrun */
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default_interrupt (UCHANTXEMPTY);/* U channel Tx reg is empty */
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default_interrupt (PDIR3UNOV); /* Processor data in 3 under/overrun */
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default_interrupt (IEC1PARERR); /* IEC958-1 Rx parity or symbol error */
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default_interrupt (IEC1VALNOGOOD);/* IEC958-1 flag not good */
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default_interrupt (IEC1CNEW); /* IEC958-1 New C-channel received */
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default_interrupt (EBUTXRESYN); /* EBU Tx FIFO resync */
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default_interrupt (EBUTXUNOV); /* EBU Tx FIFO under/overrun */
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default_interrupt (IIS2TXRESYN); /* IIS2 Tx FIFO resync */
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default_interrupt (IIS2TXUNOV); /* IIS2 Tx FIFO under/overrun */
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default_interrupt (IIS1TXRESYN); /* IIS1 Tx FIFO resync */
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default_interrupt (IIS1TXUNOV); /* IIS1 Tx FIFO under/overrun */
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default_interrupt (GPI0); /* GPIO interrupt 0 */
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default_interrupt (GPI1); /* GPIO interrupt 1 */
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default_interrupt (GPI2); /* GPIO interrupt 2 */
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default_interrupt (GPI3); /* GPIO interrupt 3 */
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default_interrupt (GPI4); /* GPIO interrupt 4 */
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default_interrupt (GPI5); /* GPIO interrupt 5 */
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default_interrupt (GPI6); /* GPIO interrupt 6 */
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default_interrupt (GPI7); /* GPIO interrupt 7 */
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default_interrupt (SOFTINT0); /* Software interrupt 0 */
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default_interrupt (SOFTINT1); /* Software interrupt 1 */
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default_interrupt (SOFTINT2); /* Software interrupt 2 */
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default_interrupt (SOFTINT3); /* Software interrupt 3 */
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default_interrupt (CDROMCRCERR); /* CD-ROM CRC error */
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default_interrupt (CDROMNOSYNC); /* CD-ROM No sync */
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default_interrupt (CDROMILSYNC); /* CD-ROM Illegal sync */
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default_interrupt (CDROMNEWBLK); /* CD-ROM New block */
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void UIE (void) /* Unexpected Interrupt or Exception */
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{
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unsigned int format_vector, pc;
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int vector;
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char str[32];
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asm volatile ("move.l (52,%%sp),%0": "=r"(format_vector));
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asm volatile ("move.l (56,%%sp),%0": "=r"(pc));
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vector = (format_vector >> 18) & 0xff;
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/* clear screen */
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lcd_clear_display ();
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#ifdef HAVE_LCD_BITMAP
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lcd_setfont(FONT_SYSFIXED);
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#endif
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snprintf(str,sizeof(str),"I%02x:%s",vector,irqname[vector]);
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lcd_puts(0,0,str);
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snprintf(str,sizeof(str),"at %08x",pc);
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lcd_puts(0,1,str);
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lcd_update();
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/* set cpu frequency to 11mhz (to prevent overheating) */
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DCR = (DCR & ~0x01ff) | 1;
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PLLCR = 0x10800000;
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while (1)
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{
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/* check for the ON button (and !hold) */
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if ((GPIO1_READ & 0x22) == 0)
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SYPCR = 0xc0;
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/* Start watchdog timer with 512 cycles timeout. Don't service it. */
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/* We need a reset method that works in all cases. Calling system_reboot()
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doesn't work when we're called from the debug interrupt, because then
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the CPU is in emulator mode and the only ways leaving it are exexcuting
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an rte instruction or performing a reset. Even disabling the breakpoint
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logic and performing special rte magic doesn't make system_reboot()
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reliable. The system restarts, but boot often fails with ata error -42. */
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}
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}
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/* reset vectors are handled in crt0.S */
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void (* const vbr[]) (void) __attribute__ ((section (".vectors"))) =
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{
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UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,TIMER0,TIMER1,UIE,UIE,UIE,
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/* lvl 3 lvl 4 */
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TRAP0,TRAP1,TRAP2,TRAP3,TRAP4,TRAP5,TRAP6,TRAP7,
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TRAP8,TRAP9,TRAP10,TRAP11,TRAP12,TRAP13,TRAP14,TRAP15,
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SWT,UIE,UIE,I2C,UART1,UART2,DMA0,DMA1,
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DMA2,DMA3,QSPI,UIE,UIE,UIE,UIE,UIE,
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PDIR1FULL,PDIR2FULL,EBUTXEMPTY,IIS2TXEMPTY,
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IIS1TXEMPTY,PDIR3FULL,PDIR3RESYN,UQ2CHANERR,
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AUDIOTICK,PDIR2RESYN,PDIR2UNOV,PDIR1RESYN,
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PDIR1UNOV,UQ1CHANERR,IEC2BUFATTEN,IEC2PARERR,
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IEC2VALNOGOOD,IEC2CNEW,IEC1BUFATTEN,UCHANTXNF,
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UCHANTXUNDER,UCHANTXEMPTY,PDIR3UNOV,IEC1PARERR,
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IEC1VALNOGOOD,IEC1CNEW,EBUTXRESYN,EBUTXUNOV,
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IIS2TXRESYN,IIS2TXUNOV,IIS1TXRESYN,IIS1TXUNOV,
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GPI0,GPI1,GPI2,GPI3,GPI4,GPI5,GPI6,GPI7,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,SOFTINT0,
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SOFTINT1,SOFTINT2,SOFTINT3,UIE,
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UIE,CDROMCRCERR,CDROMNOSYNC,CDROMILSYNC,
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CDROMNEWBLK,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE
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};
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void system_init(void)
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{
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/* Clear the accumulators. From here on it's the responsibility of
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whoever uses them to clear them after use (use movclr instruction). */
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asm volatile ("movclr.l %%acc0, %%d0\n\t"
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"movclr.l %%acc1, %%d0\n\t"
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"movclr.l %%acc2, %%d0\n\t"
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"movclr.l %%acc3, %%d0\n\t"
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: : : "d0");
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/* Set EMAC unit to saturating and rounding fractional mode, since that's
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what'll be the most useful for most things which the main thread
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will do. */
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coldfire_set_macsr(EMAC_FRACTIONAL | EMAC_SATURATE | EMAC_ROUND);
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/* Set INTBASE and SPURVEC */
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INTBASE = 64;
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SPURVEC = 24;
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}
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void system_reboot (void)
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{
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set_cpu_frequency(0);
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asm(" move.w #0x2700,%sr");
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/* Reset the cookie for the crt0 crash check */
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asm(" move.l #0,%d0");
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asm(" move.l %d0,0x10017ffc");
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asm(" movec.l %d0,%vbr");
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asm(" move.l 0,%sp");
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asm(" move.l 4,%a0");
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asm(" jmp (%a0)");
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}
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||||
|
||||
/* Utilise the breakpoint hardware to catch invalid memory accesses. */
|
||||
int system_memory_guard(int newmode)
|
||||
{
|
||||
static const unsigned long modes[MAXMEMGUARD][8] = {
|
||||
{ /* catch nothing */
|
||||
0x2C870000, 0x00000000, /* TDR = 0x00000000 */
|
||||
0x2C8D0000, 0x00000000, /* ABLR = 0x00000000 */
|
||||
0x2C8C0000, 0x00000000, /* ABHR = 0x00000000 */
|
||||
0x2C860000, 0x00050000, /* AATR = 0x0005 */
|
||||
},
|
||||
{ /* catch flash ROM writes */
|
||||
0x2C8D0000, 0x00000000, /* ABLR = 0x00000000 */
|
||||
0x2C8C0FFF, 0xFFFF0000, /* ABHR = 0x0FFFFFFF */
|
||||
0x2C860000, 0x6F050000, /* AATR = 0x6F05 */
|
||||
0x2C878000, 0x20080000, /* TDR = 0x80002008 */
|
||||
},
|
||||
{ /* catch all accesses to zero area */
|
||||
0x2C8D0000, 0x00000000, /* ABLR = 0x00000000 */
|
||||
0x2C8C0FFF, 0xFFFF0000, /* ABHR = 0x0FFFFFFF */
|
||||
0x2C860000, 0xEF050000, /* AATR = 0xEF05 */
|
||||
0x2C878000, 0x20080000, /* TDR = 0x80002008 */
|
||||
}
|
||||
/* Note: CPU space accesses (movec instruction), interrupt acknowledges
|
||||
and emulator mode accesses are never caught. */
|
||||
};
|
||||
static int cur_mode = MEMGUARD_NONE;
|
||||
|
||||
int oldmode = cur_mode;
|
||||
const unsigned long *ptr;
|
||||
int i;
|
||||
|
||||
if (newmode == MEMGUARD_KEEP)
|
||||
newmode = oldmode;
|
||||
|
||||
/* Always set the new mode, we don't know the old settings
|
||||
as we cannot read back */
|
||||
ptr = modes[newmode];
|
||||
for (i = 0; i < 4; i++)
|
||||
{
|
||||
asm ( "wdebug (%0) \n" : : "a"(ptr));
|
||||
ptr += 2;
|
||||
}
|
||||
cur_mode = newmode;
|
||||
|
||||
return oldmode;
|
||||
}
|
||||
|
||||
/* void set_cpu_frequency(long frequency) is in
|
||||
target tree for all 3 coldfire targets */
|
||||
|
||||
/* system code is in target tree for all coldfire targets */
|
||||
#elif CONFIG_CPU == SH7034
|
||||
#include "led.h"
|
||||
#include "system.h"
|
||||
|
|
|
|||
296
firmware/target/coldfire/system-coldfire.c
Normal file
296
firmware/target/coldfire/system-coldfire.c
Normal file
|
|
@ -0,0 +1,296 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id$
|
||||
*
|
||||
* Copyright (C) 2002 by Alan Korr
|
||||
*
|
||||
* All files in this archive are subject to the GNU General Public License.
|
||||
* See the file COPYING in the source tree root for full license agreement.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
#include <stdio.h>
|
||||
#include "config.h"
|
||||
#include "system.h"
|
||||
#include "lcd.h"
|
||||
#include "font.h"
|
||||
|
||||
#define default_interrupt(name) \
|
||||
extern __attribute__((weak,alias("UIE"))) void name (void)
|
||||
|
||||
static const char* const irqname[] = {
|
||||
"", "", "AccessErr","AddrErr","IllInstr", "", "","",
|
||||
"PrivVio","Trace","Line-A", "Line-F","Debug","","FormErr","Uninit",
|
||||
"","","","","","","","",
|
||||
"Spurious","Level1","Level2","Level3","Level4","Level5","Level6","Level7",
|
||||
"Trap0","Trap1","Trap2","Trap3","Trap4","Trap5","Trap6","Trap7",
|
||||
"Trap8","Trap9","Trap10","Trap11","Trap12","Trap13","Trap14","Trap15",
|
||||
"SWT","Timer0","Timer1","I2C","UART1","UART2","DMA0","DMA1",
|
||||
"DMA2","DMA3","QSPI","","","","","",
|
||||
"PDIR1FULL","PDIR2FULL","EBUTXEMPTY","IIS2TXEMPTY",
|
||||
"IIS1TXEMPTY","PDIR3FULL","PDIR3RESYN","UQ2CHANERR",
|
||||
"AUDIOTICK","PDIR2RESYN","PDIR2UNOV","PDIR1RESYN",
|
||||
"PDIR1UNOV","UQ1CHANERR","IEC2BUFATTEN","IEC2PARERR",
|
||||
"IEC2VALNOGOOD","IEC2CNEW","IEC1BUFATTEN","UCHANTXNF",
|
||||
"UCHANTXUNDER","UCHANTXEMPTY","PDIR3UNOV","IEC1PARERR",
|
||||
"IEC1VALNOGOOD","IEC1CNEW","EBUTXRESYN","EBUTXUNOV",
|
||||
"IIS2TXRESYN","IIS2TXUNOV","IIS1TXRESYN","IIS1TXUNOV",
|
||||
"GPI0","GPI1","GPI2","GPI3","GPI4","GPI5","GPI6","GPI7",
|
||||
"","","","","","","","SOFTINT0",
|
||||
"SOFTINT1","SOFTINT2","SOFTINT3","",
|
||||
"","CDROMCRCERR","CDROMNOSYNC","CDROMILSYNC",
|
||||
"CDROMNEWBLK","","","","","","","",
|
||||
"","","","","","","","",
|
||||
"","","","","","","","",
|
||||
"","","","","","","","",
|
||||
"","","","","","","","",
|
||||
"","","","","","","","",
|
||||
"","","","","","","","",
|
||||
"","","","","","","","",
|
||||
"","","","","","","",""
|
||||
};
|
||||
|
||||
default_interrupt (TRAP0); /* Trap #0 */
|
||||
default_interrupt (TRAP1); /* Trap #1 */
|
||||
default_interrupt (TRAP2); /* Trap #2 */
|
||||
default_interrupt (TRAP3); /* Trap #3 */
|
||||
default_interrupt (TRAP4); /* Trap #4 */
|
||||
default_interrupt (TRAP5); /* Trap #5 */
|
||||
default_interrupt (TRAP6); /* Trap #6 */
|
||||
default_interrupt (TRAP7); /* Trap #7 */
|
||||
default_interrupt (TRAP8); /* Trap #8 */
|
||||
default_interrupt (TRAP9); /* Trap #9 */
|
||||
default_interrupt (TRAP10); /* Trap #10 */
|
||||
default_interrupt (TRAP11); /* Trap #11 */
|
||||
default_interrupt (TRAP12); /* Trap #12 */
|
||||
default_interrupt (TRAP13); /* Trap #13 */
|
||||
default_interrupt (TRAP14); /* Trap #14 */
|
||||
default_interrupt (TRAP15); /* Trap #15 */
|
||||
default_interrupt (SWT); /* Software Watchdog Timer */
|
||||
default_interrupt (TIMER0); /* Timer 0 */
|
||||
default_interrupt (TIMER1); /* Timer 1 */
|
||||
default_interrupt (I2C); /* I2C */
|
||||
default_interrupt (UART1); /* UART 1 */
|
||||
default_interrupt (UART2); /* UART 2 */
|
||||
default_interrupt (DMA0); /* DMA 0 */
|
||||
default_interrupt (DMA1); /* DMA 1 */
|
||||
default_interrupt (DMA2); /* DMA 2 */
|
||||
default_interrupt (DMA3); /* DMA 3 */
|
||||
default_interrupt (QSPI); /* QSPI */
|
||||
|
||||
default_interrupt (PDIR1FULL); /* Processor data in 1 full */
|
||||
default_interrupt (PDIR2FULL); /* Processor data in 2 full */
|
||||
default_interrupt (EBUTXEMPTY); /* EBU transmit FIFO empty */
|
||||
default_interrupt (IIS2TXEMPTY); /* IIS2 transmit FIFO empty */
|
||||
default_interrupt (IIS1TXEMPTY); /* IIS1 transmit FIFO empty */
|
||||
default_interrupt (PDIR3FULL); /* Processor data in 3 full */
|
||||
default_interrupt (PDIR3RESYN); /* Processor data in 3 resync */
|
||||
default_interrupt (UQ2CHANERR); /* IEC958-2 Rx U/Q channel error */
|
||||
default_interrupt (AUDIOTICK); /* "tick" interrupt */
|
||||
default_interrupt (PDIR2RESYN); /* Processor data in 2 resync */
|
||||
default_interrupt (PDIR2UNOV); /* Processor data in 2 under/overrun */
|
||||
default_interrupt (PDIR1RESYN); /* Processor data in 1 resync */
|
||||
default_interrupt (PDIR1UNOV); /* Processor data in 1 under/overrun */
|
||||
default_interrupt (UQ1CHANERR); /* IEC958-1 Rx U/Q channel error */
|
||||
default_interrupt (IEC2BUFATTEN);/* IEC958-2 channel buffer full */
|
||||
default_interrupt (IEC2PARERR); /* IEC958-2 Rx parity or symbol error */
|
||||
default_interrupt (IEC2VALNOGOOD);/* IEC958-2 flag not good */
|
||||
default_interrupt (IEC2CNEW); /* IEC958-2 New C-channel received */
|
||||
default_interrupt (IEC1BUFATTEN);/* IEC958-1 channel buffer full */
|
||||
default_interrupt (UCHANTXNF); /* U channel Tx reg next byte is first */
|
||||
default_interrupt (UCHANTXUNDER);/* U channel Tx reg underrun */
|
||||
default_interrupt (UCHANTXEMPTY);/* U channel Tx reg is empty */
|
||||
default_interrupt (PDIR3UNOV); /* Processor data in 3 under/overrun */
|
||||
default_interrupt (IEC1PARERR); /* IEC958-1 Rx parity or symbol error */
|
||||
default_interrupt (IEC1VALNOGOOD);/* IEC958-1 flag not good */
|
||||
default_interrupt (IEC1CNEW); /* IEC958-1 New C-channel received */
|
||||
default_interrupt (EBUTXRESYN); /* EBU Tx FIFO resync */
|
||||
default_interrupt (EBUTXUNOV); /* EBU Tx FIFO under/overrun */
|
||||
default_interrupt (IIS2TXRESYN); /* IIS2 Tx FIFO resync */
|
||||
default_interrupt (IIS2TXUNOV); /* IIS2 Tx FIFO under/overrun */
|
||||
default_interrupt (IIS1TXRESYN); /* IIS1 Tx FIFO resync */
|
||||
default_interrupt (IIS1TXUNOV); /* IIS1 Tx FIFO under/overrun */
|
||||
default_interrupt (GPI0); /* GPIO interrupt 0 */
|
||||
default_interrupt (GPI1); /* GPIO interrupt 1 */
|
||||
default_interrupt (GPI2); /* GPIO interrupt 2 */
|
||||
default_interrupt (GPI3); /* GPIO interrupt 3 */
|
||||
default_interrupt (GPI4); /* GPIO interrupt 4 */
|
||||
default_interrupt (GPI5); /* GPIO interrupt 5 */
|
||||
default_interrupt (GPI6); /* GPIO interrupt 6 */
|
||||
default_interrupt (GPI7); /* GPIO interrupt 7 */
|
||||
|
||||
default_interrupt (SOFTINT0); /* Software interrupt 0 */
|
||||
default_interrupt (SOFTINT1); /* Software interrupt 1 */
|
||||
default_interrupt (SOFTINT2); /* Software interrupt 2 */
|
||||
default_interrupt (SOFTINT3); /* Software interrupt 3 */
|
||||
|
||||
default_interrupt (CDROMCRCERR); /* CD-ROM CRC error */
|
||||
default_interrupt (CDROMNOSYNC); /* CD-ROM No sync */
|
||||
default_interrupt (CDROMILSYNC); /* CD-ROM Illegal sync */
|
||||
default_interrupt (CDROMNEWBLK); /* CD-ROM New block */
|
||||
|
||||
void UIE (void) /* Unexpected Interrupt or Exception */
|
||||
{
|
||||
unsigned int format_vector, pc;
|
||||
int vector;
|
||||
char str[32];
|
||||
|
||||
asm volatile ("move.l (52,%%sp),%0": "=r"(format_vector));
|
||||
asm volatile ("move.l (56,%%sp),%0": "=r"(pc));
|
||||
|
||||
vector = (format_vector >> 18) & 0xff;
|
||||
|
||||
/* clear screen */
|
||||
lcd_clear_display ();
|
||||
lcd_setfont(FONT_SYSFIXED);
|
||||
|
||||
snprintf(str,sizeof(str),"I%02x:%s",vector,irqname[vector]);
|
||||
lcd_puts(0,0,str);
|
||||
snprintf(str,sizeof(str),"at %08x",pc);
|
||||
lcd_puts(0,1,str);
|
||||
lcd_update();
|
||||
|
||||
/* set cpu frequency to 11mhz (to prevent overheating) */
|
||||
DCR = (DCR & ~0x01ff) | 1;
|
||||
PLLCR = 0x10800000;
|
||||
|
||||
while (1)
|
||||
{
|
||||
/* check for the ON button (and !hold) */
|
||||
if ((GPIO1_READ & 0x22) == 0)
|
||||
SYPCR = 0xc0;
|
||||
/* Start watchdog timer with 512 cycles timeout. Don't service it. */
|
||||
|
||||
/* We need a reset method that works in all cases. Calling system_reboot()
|
||||
doesn't work when we're called from the debug interrupt, because then
|
||||
the CPU is in emulator mode and the only ways leaving it are exexcuting
|
||||
an rte instruction or performing a reset. Even disabling the breakpoint
|
||||
logic and performing special rte magic doesn't make system_reboot()
|
||||
reliable. The system restarts, but boot often fails with ata error -42. */
|
||||
}
|
||||
}
|
||||
|
||||
/* reset vectors are handled in crt0.S */
|
||||
void (* const vbr[]) (void) __attribute__ ((section (".vectors"))) =
|
||||
{
|
||||
UIE,UIE,UIE,UIE,UIE,UIE,
|
||||
UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
|
||||
UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
|
||||
UIE,UIE,UIE,TIMER0,TIMER1,UIE,UIE,UIE,
|
||||
/* lvl 3 lvl 4 */
|
||||
|
||||
TRAP0,TRAP1,TRAP2,TRAP3,TRAP4,TRAP5,TRAP6,TRAP7,
|
||||
TRAP8,TRAP9,TRAP10,TRAP11,TRAP12,TRAP13,TRAP14,TRAP15,
|
||||
|
||||
SWT,UIE,UIE,I2C,UART1,UART2,DMA0,DMA1,
|
||||
DMA2,DMA3,QSPI,UIE,UIE,UIE,UIE,UIE,
|
||||
PDIR1FULL,PDIR2FULL,EBUTXEMPTY,IIS2TXEMPTY,
|
||||
IIS1TXEMPTY,PDIR3FULL,PDIR3RESYN,UQ2CHANERR,
|
||||
AUDIOTICK,PDIR2RESYN,PDIR2UNOV,PDIR1RESYN,
|
||||
PDIR1UNOV,UQ1CHANERR,IEC2BUFATTEN,IEC2PARERR,
|
||||
IEC2VALNOGOOD,IEC2CNEW,IEC1BUFATTEN,UCHANTXNF,
|
||||
UCHANTXUNDER,UCHANTXEMPTY,PDIR3UNOV,IEC1PARERR,
|
||||
IEC1VALNOGOOD,IEC1CNEW,EBUTXRESYN,EBUTXUNOV,
|
||||
IIS2TXRESYN,IIS2TXUNOV,IIS1TXRESYN,IIS1TXUNOV,
|
||||
GPI0,GPI1,GPI2,GPI3,GPI4,GPI5,GPI6,GPI7,
|
||||
UIE,UIE,UIE,UIE,UIE,UIE,UIE,SOFTINT0,
|
||||
SOFTINT1,SOFTINT2,SOFTINT3,UIE,
|
||||
UIE,CDROMCRCERR,CDROMNOSYNC,CDROMILSYNC,
|
||||
CDROMNEWBLK,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
|
||||
|
||||
UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
|
||||
UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
|
||||
UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
|
||||
UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
|
||||
UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
|
||||
UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
|
||||
UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
|
||||
UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE
|
||||
};
|
||||
|
||||
void system_init(void)
|
||||
{
|
||||
/* Clear the accumulators. From here on it's the responsibility of
|
||||
whoever uses them to clear them after use (use movclr instruction). */
|
||||
asm volatile ("movclr.l %%acc0, %%d0\n\t"
|
||||
"movclr.l %%acc1, %%d0\n\t"
|
||||
"movclr.l %%acc2, %%d0\n\t"
|
||||
"movclr.l %%acc3, %%d0\n\t"
|
||||
: : : "d0");
|
||||
/* Set EMAC unit to saturating and rounding fractional mode, since that's
|
||||
what'll be the most useful for most things which the main thread
|
||||
will do. */
|
||||
coldfire_set_macsr(EMAC_FRACTIONAL | EMAC_SATURATE | EMAC_ROUND);
|
||||
|
||||
/* Set INTBASE and SPURVEC */
|
||||
INTBASE = 64;
|
||||
SPURVEC = 24;
|
||||
}
|
||||
|
||||
void system_reboot (void)
|
||||
{
|
||||
set_cpu_frequency(0);
|
||||
|
||||
asm(" move.w #0x2700,%sr");
|
||||
/* Reset the cookie for the crt0 crash check */
|
||||
asm(" move.l #0,%d0");
|
||||
asm(" move.l %d0,0x10017ffc");
|
||||
asm(" movec.l %d0,%vbr");
|
||||
asm(" move.l 0,%sp");
|
||||
asm(" move.l 4,%a0");
|
||||
asm(" jmp (%a0)");
|
||||
}
|
||||
|
||||
/* Utilise the breakpoint hardware to catch invalid memory accesses. */
|
||||
int system_memory_guard(int newmode)
|
||||
{
|
||||
static const unsigned long modes[MAXMEMGUARD][8] = {
|
||||
{ /* catch nothing */
|
||||
0x2C870000, 0x00000000, /* TDR = 0x00000000 */
|
||||
0x2C8D0000, 0x00000000, /* ABLR = 0x00000000 */
|
||||
0x2C8C0000, 0x00000000, /* ABHR = 0x00000000 */
|
||||
0x2C860000, 0x00050000, /* AATR = 0x0005 */
|
||||
},
|
||||
{ /* catch flash ROM writes */
|
||||
0x2C8D0000, 0x00000000, /* ABLR = 0x00000000 */
|
||||
0x2C8C0FFF, 0xFFFF0000, /* ABHR = 0x0FFFFFFF */
|
||||
0x2C860000, 0x6F050000, /* AATR = 0x6F05 */
|
||||
0x2C878000, 0x20080000, /* TDR = 0x80002008 */
|
||||
},
|
||||
{ /* catch all accesses to zero area */
|
||||
0x2C8D0000, 0x00000000, /* ABLR = 0x00000000 */
|
||||
0x2C8C0FFF, 0xFFFF0000, /* ABHR = 0x0FFFFFFF */
|
||||
0x2C860000, 0xEF050000, /* AATR = 0xEF05 */
|
||||
0x2C878000, 0x20080000, /* TDR = 0x80002008 */
|
||||
}
|
||||
/* Note: CPU space accesses (movec instruction), interrupt acknowledges
|
||||
and emulator mode accesses are never caught. */
|
||||
};
|
||||
static int cur_mode = MEMGUARD_NONE;
|
||||
|
||||
int oldmode = cur_mode;
|
||||
const unsigned long *ptr;
|
||||
int i;
|
||||
|
||||
if (newmode == MEMGUARD_KEEP)
|
||||
newmode = oldmode;
|
||||
|
||||
/* Always set the new mode, we don't know the old settings
|
||||
as we cannot read back */
|
||||
ptr = modes[newmode];
|
||||
for (i = 0; i < 4; i++)
|
||||
{
|
||||
asm ( "wdebug (%0) \n" : : "a"(ptr));
|
||||
ptr += 2;
|
||||
}
|
||||
cur_mode = newmode;
|
||||
|
||||
return oldmode;
|
||||
}
|
||||
131
firmware/target/coldfire/system-target.h
Normal file
131
firmware/target/coldfire/system-target.h
Normal file
|
|
@ -0,0 +1,131 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id$
|
||||
*
|
||||
* Copyright (C) 2002 by Alan Korr
|
||||
*
|
||||
* All files in this archive are subject to the GNU General Public License.
|
||||
* See the file COPYING in the source tree root for full license agreement.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
#ifndef SYSTEM_TARGET_H
|
||||
#define SYSTEM_TARGET_H
|
||||
|
||||
#define or_l(mask, address) \
|
||||
asm \
|
||||
("or.l %0,(%1)" \
|
||||
: \
|
||||
: /* %0 */ "d"(mask), \
|
||||
/* %1 */ "a"(address))
|
||||
|
||||
#define and_l(mask, address) \
|
||||
asm \
|
||||
("and.l %0,(%1)" \
|
||||
: \
|
||||
: /* %0 */ "d"(mask), \
|
||||
/* %1 */ "a"(address))
|
||||
|
||||
#define eor_l(mask, address) \
|
||||
asm \
|
||||
("eor.l %0,(%1)" \
|
||||
: \
|
||||
: /* %0 */ "d"(mask), \
|
||||
/* %1 */ "a"(address))
|
||||
|
||||
#define EMAC_ROUND 0x10
|
||||
#define EMAC_FRACTIONAL 0x20
|
||||
#define EMAC_SATURATE 0x80
|
||||
|
||||
static inline void coldfire_set_macsr(unsigned long flags)
|
||||
{
|
||||
asm volatile ("move.l %0, %%macsr" : : "i,r" (flags));
|
||||
}
|
||||
|
||||
static inline unsigned long coldfire_get_macsr(void)
|
||||
{
|
||||
unsigned long m;
|
||||
|
||||
asm volatile ("move.l %%macsr, %0" : "=r" (m));
|
||||
return m;
|
||||
}
|
||||
|
||||
#define HIGHEST_IRQ_LEVEL (7<<8)
|
||||
static inline int set_irq_level(int level)
|
||||
{
|
||||
int oldlevel;
|
||||
/* Read the old level and set the new one */
|
||||
asm volatile ("move.w %%sr,%0\n"
|
||||
"or.l #0x2000,%1\n"
|
||||
"move.w %1,%%sr\n" : "=d" (oldlevel), "+d" (level) : );
|
||||
return oldlevel;
|
||||
}
|
||||
|
||||
static inline unsigned short swap16(unsigned short value)
|
||||
/*
|
||||
result[15..8] = value[ 7..0];
|
||||
result[ 7..0] = value[15..8];
|
||||
*/
|
||||
{
|
||||
return (value >> 8) | (value << 8);
|
||||
}
|
||||
|
||||
static inline unsigned long SWAW32(unsigned long value)
|
||||
/*
|
||||
result[31..16] = value[15.. 0];
|
||||
result[15.. 0] = value[31..16];
|
||||
*/
|
||||
{
|
||||
asm ("swap %%0" : "+r"(value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static inline unsigned long swap32(unsigned long value)
|
||||
/*
|
||||
result[31..24] = value[ 7.. 0];
|
||||
result[23..16] = value[15.. 8];
|
||||
result[15.. 8] = value[23..16];
|
||||
result[ 7.. 0] = value[31..24];
|
||||
*/
|
||||
{
|
||||
unsigned long mask = 0x00FF00FF;
|
||||
asm ( /* val = ABCD */
|
||||
"and.l %[val],%[mask] \n" /* mask = .B.D */
|
||||
"eor.l %[mask],%[val] \n" /* val = A.C. */
|
||||
"lsl.l #8,%[mask] \n" /* mask = B.D. */
|
||||
"lsr.l #8,%[val] \n" /* val = .A.C */
|
||||
"or.l %[mask],%[val] \n" /* val = BADC */
|
||||
"swap %[val] \n" /* val = DCBA */
|
||||
: /* outputs */
|
||||
[val] "+d"(value),
|
||||
[mask]"+d"(mask)
|
||||
);
|
||||
return value;
|
||||
}
|
||||
|
||||
static inline void invalidate_icache(void)
|
||||
{
|
||||
asm volatile ("move.l #0x01000000,%d0\n"
|
||||
"movec.l %d0,%cacr\n"
|
||||
"move.l #0x80000000,%d0\n"
|
||||
"movec.l %d0,%cacr");
|
||||
}
|
||||
|
||||
/* 11.2896 MHz */
|
||||
#define CPUFREQ_DEFAULT_MULT 1
|
||||
#define CPUFREQ_DEFAULT (CPUFREQ_DEFAULT_MULT * CPU_FREQ)
|
||||
/* 45.1584 MHz */
|
||||
#define CPUFREQ_NORMAL_MULT 4
|
||||
#define CPUFREQ_NORMAL (CPUFREQ_NORMAL_MULT * CPU_FREQ)
|
||||
/* 124.1856 MHz */
|
||||
#define CPUFREQ_MAX_MULT 11
|
||||
#define CPUFREQ_MAX (CPUFREQ_MAX_MULT * CPU_FREQ)
|
||||
|
||||
#endif /* SYSTEM_TARGET_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue