forked from len0rd/rockbox
H300: Optimised PCF50606 driver, significantly reduces CPU power drain from the button tick (with both main & remote buttons: 50%->13% at 11MHz, 12%->6% at 45MHz): * Delay is adapted to the current CPU clock, aiming at constant 400kHz i2c clock. * Reduced number of port accesses (accessing GPIO is very slow, especially with the atomic boolean instructions) by implementing an open-collector-like behaviour. * Time-critical functions implemented in assembler.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@9693 a1c6a512-1295-4272-9138-f99709370657
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3 changed files with 344 additions and 83 deletions
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@ -594,6 +594,13 @@ int system_memory_guard(int newmode)
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#define DEFAULT_REFRESH_TIMER 1
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#endif
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#ifdef IRIVER_H300_SERIES
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#define RECALC_DELAYS(f) \
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pcf50606_i2c_recalc_delay(f)
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#else
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#define RECALC_DELAYS(f)
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#endif
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void set_cpu_frequency (long) __attribute__ ((section (".icode")));
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void set_cpu_frequency(long frequency)
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{
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@ -604,6 +611,7 @@ void set_cpu_frequency(long frequency)
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/* Refresh timer for bypass frequency */
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PLLCR &= ~1; /* Bypass mode */
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timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
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RECALC_DELAYS(CPUFREQ_MAX);
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PLLCR = 0x11c56005;
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CSCR0 = 0x00001180; /* Flash: 4 wait states */
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CSCR1 = 0x00000980; /* LCD: 2 wait states */
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@ -615,12 +623,13 @@ void set_cpu_frequency(long frequency)
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IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
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IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */
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break;
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case CPUFREQ_NORMAL:
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DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER;
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/* Refresh timer for bypass frequency */
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PLLCR &= ~1; /* Bypass mode */
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timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
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RECALC_DELAYS(CPUFREQ_NORMAL);
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PLLCR = 0x13c5e005;
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CSCR0 = 0x00000580; /* Flash: 1 wait state */
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CSCR1 = 0x00000180; /* LCD: 0 wait states */
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@ -637,6 +646,7 @@ void set_cpu_frequency(long frequency)
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/* Refresh timer for bypass frequency */
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PLLCR &= ~1; /* Bypass mode */
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timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true);
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RECALC_DELAYS(CPUFREQ_DEFAULT);
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PLLCR = 0x10c00200; /* Power down PLL, but keep CLSEL and CRSEL */
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CSCR0 = 0x00000180; /* Flash: 0 wait states */
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CSCR1 = 0x00000180; /* LCD: 0 wait states */
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