Disable clocks for most modules in the imx31l on startup, individual drivers handle enabling/disabling clocks for used modules

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17417 a1c6a512-1295-4272-9138-f99709370657

firmware/export/imx31l.h

@@ -365,6 +365,11 @@
 #define SW_PAD_CTL_FLD_1(x)                         ((x) << 10)
 #define SW_PAD_CTL_FLD_2(x)                         ((x) << 20)
 
+/* RNGA */
+#define RNGA_CONTROL            (*(REG32_PTR_T)(RNGA_BASE_ADDR+0x00))
+
+#define RNGA_CONTROL_SLEEP                          (1 << 4)
+
 /* IPU */
 #define IPU_CONF                (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x00))
 #define IPU_CHA_BUF0_RDY        (*(REG32_PTR_T)(IPU_CTRL_BASE_ADDR+0x04))
@@ -1033,6 +1038,13 @@
 #define KPP_KPSR_KPKR           (1 << 1)
 #define KPP_KPSR_KPKD           (1 << 0)
 
+/* SDHC */
+#define SDHC1_CLOCK_CONTROL     (*(REG32_PTR_T)(MMC_SDHC1_BASE_ADDR+0x00))
+#define SDHC2_CLOCK_CONTROL     (*(REG32_PTR_T)(MMC_SDHC2_BASE_ADDR+0x00))
+
+/* SDHC bits */
+#define STOP_CLK                (1 << 0)
+
 /* ROMPATCH and AVIC */
 #define ROMPATCH_BASE_ADDR      0x60000000
 
@@ -1380,6 +1392,11 @@
 #define USR2_1                          (*(REG32_PTR_T)(UART1_BASE_ADDR+0x98))
 #define UTS1                            (*(REG32_PTR_T)(UART1_BASE_ADDR+0xB4))
 
+#define UCR1_2                          (*(REG32_PTR_T)(UART2_BASE_ADDR+0x80))
+#define UCR1_3                          (*(REG32_PTR_T)(UART3_BASE_ADDR+0x80))
+#define UCR1_4                          (*(REG32_PTR_T)(UART4_BASE_ADDR+0x80))
+#define UCR1_5                          (*(REG32_PTR_T)(UART5_BASE_ADDR+0x80))
+
 /*
  * UART Control Register 0 Bit Fields.
  */

firmware/target/arm/imx31/gigabeat-s/button-imx31.c

@@ -25,6 +25,7 @@
 #include "system.h"
 #include "backlight-target.h"
 #include "avic-imx31.h"
+#include "clkctl-imx31.h"
 
 /* Most code in here is taken from the Linux BSP provided by Freescale
  * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. */
@@ -119,7 +120,7 @@ static __attribute__((interrupt("IRQ"))) void KPP_HANDLER(void)
 void button_init_device(void)
 {
     /* Enable keypad clock */
-    CLKCTL_CGR1 |= (3 << 2*10);
+    imx31_clkctl_module_clock_gating(CG_KPP, CGM_ON_ALL);
 
     /* 1. Enable number of rows in keypad (KPCR[4:0])
      *

firmware/target/arm/imx31/gigabeat-s/system-imx31.c

@@ -8,6 +8,7 @@
 #include "lcd.h"
 #include "serial-imx31.h"
 #include "debug.h"
+#include "clkctl-imx31.h"
 
 int system_memory_guard(int newmode)
 {
@@ -21,8 +22,63 @@ void system_reboot(void)
 
 void system_init(void)
 {
+    static const int disable_clocks[] =
+    {
+        /* CGR0 */
+        CG_SD_MMC1,
+        CG_SD_MMC2,
+        CG_IIM,
+        CG_CSPI3,
+        CG_RNG,
+        CG_UART1,
+        CG_UART2,
+        CG_SSI1,
+        CG_I2C1,
+        CG_I2C2,
+        CG_I2C3,
+
+        /* CGR1 */
+        CG_HANTRO,
+        CG_MEMSTICK1,
+        CG_MEMSTICK2,
+        CG_CSI,
+        CG_PWM,
+        CG_WDOG,
+        CG_SIM,
+        CG_ECT,
+        CG_USBOTG,
+        CG_KPP,
+        CG_UART3,
+        CG_UART4,
+        CG_UART5,
+        CG_1_WIRE,
+
+        /* CGR2 */
+        CG_SSI2,
+        CG_CSPI1,
+        CG_CSPI2,
+        CG_GACC,
+        CG_RTIC,
+        CG_FIR
+    };
+
+    unsigned int i;
+
     /* MCR WFI enables wait mode */
     CLKCTL_CCMR &= ~(3 << 14);
+
+    imx31_regmod32(&SDHC1_CLOCK_CONTROL, STOP_CLK, STOP_CLK);
+    imx31_regmod32(&SDHC2_CLOCK_CONTROL, STOP_CLK, STOP_CLK);
+    imx31_regmod32(&RNGA_CONTROL, RNGA_CONTROL_SLEEP, RNGA_CONTROL_SLEEP);
+    imx31_regmod32(&UCR1_1, 0, EUARTUCR1_UARTEN);
+    imx31_regmod32(&UCR1_2, 0, EUARTUCR1_UARTEN);
+    imx31_regmod32(&UCR1_3, 0, EUARTUCR1_UARTEN);
+    imx31_regmod32(&UCR1_4, 0, EUARTUCR1_UARTEN);
+    imx31_regmod32(&UCR1_5, 0, EUARTUCR1_UARTEN);
+
+    for (i = 0; i < ARRAYLEN(disable_clocks); i++)
+        imx31_clkctl_module_clock_gating(disable_clocks[i], CGM_OFF);
+
     avic_init();
     gpio_init();
 }