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CPP substitution isn't made inside " ", but we need " " when using , in a gas macro argument

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Modify HIGH_REGS macro to store/load only one range of registers
When the range isn't contigous (in MC_put_x_8*), shift registers to make
it contigous (r4 and r5 are now unused by these functions)

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26759 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rafaël Carré 2010-06-11 05:15:17 +00:00
parent 95ef367854
commit e3263b70c3
1 changed files with 33 additions and 33 deletions
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66
apps/plugins/mpegplayer/motion_comp_arm_s.S
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@ -183,9 +183,9 @@ MC_put_o_8_align3:
.endm .endm
#if ARM_ARCH >= 6 #if ARM_ARCH >= 6
#define HIGH_REGS r9 #define HIGHEST_REG r9
#else #else
#define HIGH_REGS r9-r11 #define HIGHEST_REG r11
#endif #endif
.align .align
@ -193,7 +193,7 @@ MC_put_o_8_align3:
MC_put_x_16: MC_put_x_16:
@@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height) @@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
@@ pld [r1] @@ pld [r1]
stmfd sp!, {r4-r8, HIGH_REGS, lr} @ R14 is also called LR stmfd sp!, {r4-HIGHEST_REG, lr} @ R14 is also called LR
and r4, r1, #3 and r4, r1, #3
ldr r12, 2f ldr r12, 2f
#if ARM_ARCH < 6 #if ARM_ARCH < 6
@ -218,7 +218,7 @@ MC_put_x_16_align0:
subs r3, r3, #1 subs r3, r3, #1
add r0, r0, r2 add r0, r0, r2
bne MC_put_x_16_align0 bne MC_put_x_16_align0
ldmpc regs="r4-r8, HIGH_REGS" @@ update PC with LR content. ldmpc regs=r4-HIGHEST_REG @@ update PC with LR content.
MC_put_x_16_align1: MC_put_x_16_align1:
and r1, r1, #0xFFFFFFFC and r1, r1, #0xFFFFFFFC
@ -234,7 +234,7 @@ MC_put_x_16_align1:
subs r3, r3, #1 subs r3, r3, #1
add r0, r0, r2 add r0, r0, r2
bne 1b bne 1b
ldmpc regs="r4-r8, HIGH_REGS" @@ update PC with LR content. ldmpc regs=r4-HIGHEST_REG @@ update PC with LR content.
MC_put_x_16_align2: MC_put_x_16_align2:
and r1, r1, #0xFFFFFFFC and r1, r1, #0xFFFFFFFC
@ -250,7 +250,7 @@ MC_put_x_16_align2:
subs r3, r3, #1 subs r3, r3, #1
add r0, r0, r2 add r0, r0, r2
bne 1b bne 1b
ldmpc regs="r4-r8, HIGH_REGS" @@ update PC with LR content. ldmpc regs=r4-HIGHEST_REG @@ update PC with LR content.
MC_put_x_16_align3: MC_put_x_16_align3:
and r1, r1, #0xFFFFFFFC and r1, r1, #0xFFFFFFFC
@ -266,7 +266,7 @@ MC_put_x_16_align3:
subs r3, r3, #1 subs r3, r3, #1
add r0, r0, r2 add r0, r0, r2
bne 1b bne 1b
ldmpc regs="r4-r8, HIGH_REGS" @@ update PC with LR content. ldmpc regs=r4-HIGHEST_REG @@ update PC with LR content.
@ ---------------------------------------------------------------- @ ----------------------------------------------------------------
.align .align
@ -274,13 +274,13 @@ MC_put_x_16_align3:
MC_put_x_8: MC_put_x_8:
@@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height) @@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
@@ pld [r1] @@ pld [r1]
stmfd sp!, {r4-r6, HIGH_REGS, lr} @ R14 is also called LR stmfd sp!, {r6-HIGHEST_REG, lr} @ R14 is also called LR
and r4, r1, #3 and r6, r1, #3
ldr r12, 2f ldr r12, 2f
#if ARM_ARCH < 6 #if ARM_ARCH < 6
mvn r11, r12 mvn r11, r12
#endif #endif
ldr pc, [pc, r4, lsl #2] ldr pc, [pc, r6, lsl #2]
2: .word 0x01010101 2: .word 0x01010101
.word MC_put_x_8_align0 .word MC_put_x_8_align0
.word MC_put_x_8_align1 .word MC_put_x_8_align1
@ -288,55 +288,55 @@ MC_put_x_8:
.word MC_put_x_8_align3 .word MC_put_x_8_align3
MC_put_x_8_align0: MC_put_x_8_align0:
ldmia r1, {r4-r6} ldmia r1, {r6-r8}
add r1, r1, r2 add r1, r1, r2
@@ pld [r1] @@ pld [r1]
AVG_PW r5, r6 AVG_PW r7, r8
AVG_PW r4, r5 AVG_PW r6, r7
stmia r0, {r5-r6} stmia r0, {r7-r8}
subs r3, r3, #1 subs r3, r3, #1
add r0, r0, r2 add r0, r0, r2
bne MC_put_x_8_align0 bne MC_put_x_8_align0
ldmpc regs="r4-r6, HIGH_REGS" @@ update PC with LR content. ldmpc regs=r6-HIGHEST_REG @@ update PC with LR content.
MC_put_x_8_align1: MC_put_x_8_align1:
and r1, r1, #0xFFFFFFFC and r1, r1, #0xFFFFFFFC
1: ldmia r1, {r4-r6} 1: ldmia r1, {r6-r8}
add r1, r1, r2 add r1, r1, r2
@@ pld [r1] @@ pld [r1]
ADJ_ALIGN_DW 8, r4, r5, r6 ADJ_ALIGN_DW 8, r6, r7, r8
AVG_PW r5, r6 AVG_PW r7, r8
AVG_PW r4, r5 AVG_PW r6, r7
stmia r0, {r5-r6} stmia r0, {r7-r8}
subs r3, r3, #1 subs r3, r3, #1
add r0, r0, r2 add r0, r0, r2
bne 1b bne 1b
ldmpc regs="r4-r6, HIGH_REGS" @@ update PC with LR content. ldmpc regs=r6-HIGHEST_REG @@ update PC with LR content.
MC_put_x_8_align2: MC_put_x_8_align2:
and r1, r1, #0xFFFFFFFC and r1, r1, #0xFFFFFFFC
1: ldmia r1, {r4-r6} 1: ldmia r1, {r6-r8}
add r1, r1, r2 add r1, r1, r2
@@ pld [r1] @@ pld [r1]
ADJ_ALIGN_DW 16, r4, r5, r6 ADJ_ALIGN_DW 16, r6, r7, r8
AVG_PW r5, r6 AVG_PW r7, r8
AVG_PW r4, r5 AVG_PW r6, r7
stmia r0, {r5-r6} stmia r0, {r7-r8}
subs r3, r3, #1 subs r3, r3, #1
add r0, r0, r2 add r0, r0, r2
bne 1b bne 1b
ldmpc regs="r4-r6, HIGH_REGS" @@ update PC with LR content. ldmpc regs=r6-HIGHEST_REG @@ update PC with LR content.
MC_put_x_8_align3: MC_put_x_8_align3:
and r1, r1, #0xFFFFFFFC and r1, r1, #0xFFFFFFFC
1: ldmia r1, {r4-r6} 1: ldmia r1, {r6-r8}
add r1, r1, r2 add r1, r1, r2
@@ pld [r1] @@ pld [r1]
ADJ_ALIGN_DW 24, r4, r5, r6 ADJ_ALIGN_DW 24, r6, r7, r8
AVG_PW r5, r6 AVG_PW r7, r8
AVG_PW r4, r5 AVG_PW r6, r7
stmia r0, {r5-r6} stmia r0, {r7-r8}
subs r3, r3, #1 subs r3, r3, #1
add r0, r0, r2 add r0, r0, r2
bne 1b bne 1b
ldmpc regs="r4-r6, HIGH_REGS @@ update PC with LR content. ldmpc regs=r6-HIGHEST_REG @@ update PC with LR content.