forked from len0rd/rockbox
CPP substitution isn't made inside " ", but we need " " when using , in a gas macro argument
Modify HIGH_REGS macro to store/load only one range of registers When the range isn't contigous (in MC_put_x_8*), shift registers to make it contigous (r4 and r5 are now unused by these functions) git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26759 a1c6a512-1295-4272-9138-f99709370657
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95ef367854
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1 changed files with 33 additions and 33 deletions
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@ -183,9 +183,9 @@ MC_put_o_8_align3:
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.endm
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#if ARM_ARCH >= 6
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#define HIGH_REGS r9
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#define HIGHEST_REG r9
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#else
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#define HIGH_REGS r9-r11
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#define HIGHEST_REG r11
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#endif
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.align
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@ -193,7 +193,7 @@ MC_put_o_8_align3:
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MC_put_x_16:
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@@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
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@@ pld [r1]
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stmfd sp!, {r4-r8, HIGH_REGS, lr} @ R14 is also called LR
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stmfd sp!, {r4-HIGHEST_REG, lr} @ R14 is also called LR
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and r4, r1, #3
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ldr r12, 2f
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#if ARM_ARCH < 6
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@ -218,7 +218,7 @@ MC_put_x_16_align0:
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subs r3, r3, #1
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add r0, r0, r2
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bne MC_put_x_16_align0
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ldmpc regs="r4-r8, HIGH_REGS" @@ update PC with LR content.
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ldmpc regs=r4-HIGHEST_REG @@ update PC with LR content.
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MC_put_x_16_align1:
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and r1, r1, #0xFFFFFFFC
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@ -234,7 +234,7 @@ MC_put_x_16_align1:
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmpc regs="r4-r8, HIGH_REGS" @@ update PC with LR content.
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ldmpc regs=r4-HIGHEST_REG @@ update PC with LR content.
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MC_put_x_16_align2:
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and r1, r1, #0xFFFFFFFC
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@ -250,7 +250,7 @@ MC_put_x_16_align2:
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmpc regs="r4-r8, HIGH_REGS" @@ update PC with LR content.
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ldmpc regs=r4-HIGHEST_REG @@ update PC with LR content.
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MC_put_x_16_align3:
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and r1, r1, #0xFFFFFFFC
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@ -266,7 +266,7 @@ MC_put_x_16_align3:
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmpc regs="r4-r8, HIGH_REGS" @@ update PC with LR content.
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ldmpc regs=r4-HIGHEST_REG @@ update PC with LR content.
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@ ----------------------------------------------------------------
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.align
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@ -274,13 +274,13 @@ MC_put_x_16_align3:
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MC_put_x_8:
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@@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
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@@ pld [r1]
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stmfd sp!, {r4-r6, HIGH_REGS, lr} @ R14 is also called LR
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and r4, r1, #3
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stmfd sp!, {r6-HIGHEST_REG, lr} @ R14 is also called LR
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and r6, r1, #3
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ldr r12, 2f
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#if ARM_ARCH < 6
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mvn r11, r12
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#endif
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ldr pc, [pc, r4, lsl #2]
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ldr pc, [pc, r6, lsl #2]
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2: .word 0x01010101
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.word MC_put_x_8_align0
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.word MC_put_x_8_align1
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@ -288,55 +288,55 @@ MC_put_x_8:
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.word MC_put_x_8_align3
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MC_put_x_8_align0:
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ldmia r1, {r4-r6}
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ldmia r1, {r6-r8}
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add r1, r1, r2
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@@ pld [r1]
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AVG_PW r5, r6
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AVG_PW r4, r5
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stmia r0, {r5-r6}
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AVG_PW r7, r8
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AVG_PW r6, r7
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stmia r0, {r7-r8}
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subs r3, r3, #1
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add r0, r0, r2
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bne MC_put_x_8_align0
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ldmpc regs="r4-r6, HIGH_REGS" @@ update PC with LR content.
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ldmpc regs=r6-HIGHEST_REG @@ update PC with LR content.
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MC_put_x_8_align1:
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and r1, r1, #0xFFFFFFFC
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1: ldmia r1, {r4-r6}
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1: ldmia r1, {r6-r8}
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add r1, r1, r2
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@@ pld [r1]
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ADJ_ALIGN_DW 8, r4, r5, r6
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AVG_PW r5, r6
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AVG_PW r4, r5
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stmia r0, {r5-r6}
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ADJ_ALIGN_DW 8, r6, r7, r8
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AVG_PW r7, r8
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AVG_PW r6, r7
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stmia r0, {r7-r8}
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmpc regs="r4-r6, HIGH_REGS" @@ update PC with LR content.
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ldmpc regs=r6-HIGHEST_REG @@ update PC with LR content.
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MC_put_x_8_align2:
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and r1, r1, #0xFFFFFFFC
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1: ldmia r1, {r4-r6}
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1: ldmia r1, {r6-r8}
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add r1, r1, r2
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@@ pld [r1]
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ADJ_ALIGN_DW 16, r4, r5, r6
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AVG_PW r5, r6
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AVG_PW r4, r5
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stmia r0, {r5-r6}
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ADJ_ALIGN_DW 16, r6, r7, r8
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AVG_PW r7, r8
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AVG_PW r6, r7
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stmia r0, {r7-r8}
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmpc regs="r4-r6, HIGH_REGS" @@ update PC with LR content.
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ldmpc regs=r6-HIGHEST_REG @@ update PC with LR content.
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MC_put_x_8_align3:
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and r1, r1, #0xFFFFFFFC
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1: ldmia r1, {r4-r6}
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1: ldmia r1, {r6-r8}
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add r1, r1, r2
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@@ pld [r1]
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ADJ_ALIGN_DW 24, r4, r5, r6
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AVG_PW r5, r6
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AVG_PW r4, r5
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stmia r0, {r5-r6}
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ADJ_ALIGN_DW 24, r6, r7, r8
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AVG_PW r7, r8
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AVG_PW r6, r7
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stmia r0, {r7-r8}
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmpc regs="r4-r6, HIGH_REGS @@ update PC with LR content.
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ldmpc regs=r6-HIGHEST_REG @@ update PC with LR content.
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