forked from len0rd/rockbox
added .vectors section for ARM
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@8442 a1c6a512-1295-4272-9138-f99709370657
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parent
27c616fd46
commit
e0bb10420d
2 changed files with 41 additions and 13 deletions
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@ -128,8 +128,8 @@ _pluginbuf = 0;
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#define IRAMSIZE 0xc000
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#elif CONFIG_CPU==PNX0101
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#define DRAMORIG 0x24000000 + STUBOFFSET
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#define IRAMORIG 0x400100
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#define IRAMSIZE 0x7f00
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#define IRAMORIG 0x400000
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#define IRAMSIZE 0x8000
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#else
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#define DRAMORIG 0x09000000 + STUBOFFSET
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#define IRAMORIG 0x0f000000
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@ -150,6 +150,7 @@ MEMORY
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SECTIONS
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{
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#ifndef CPU_ARM
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.vectors :
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{
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loadaddress = .;
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@ -162,6 +163,12 @@ SECTIONS
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.text :
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{
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#else
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.text :
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{
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loadaddress = .;
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_loadaddress = .;
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#endif
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. = ALIGN(0x200);
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*(.init.text)
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*(.text*)
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@ -193,7 +200,6 @@ SECTIONS
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*(.data*)
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. = ALIGN(0x4);
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_dataend = .;
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_iramcopy = .;
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} > DRAM
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/DISCARD/ :
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@ -201,14 +207,31 @@ SECTIONS
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*(.eh_frame)
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}
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.iram IRAMORIG : AT ( _iramcopy)
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#ifdef CPU_ARM
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.vectors 0x0 :
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{
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_vectorsstart = .;
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*(.vectors);
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_vectorsend = .;
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} AT> DRAM
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_vectorscopy = LOADADDR(.vectors);
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#endif
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#if CONFIG_CPU==PNX0101
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.iram IRAMORIG + SIZEOF(.vectors) :
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#else
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.iram IRAMORIG :
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#endif
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{
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_iramstart = .;
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*(.icode)
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*(.irodata)
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*(.idata)
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_iramend = .;
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} > IRAM
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} > IRAM AT> DRAM
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_iramcopy = LOADADDR(.iram);
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.ibss (NOLOAD) :
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{
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@ -238,8 +261,10 @@ SECTIONS
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} > DRAM
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#endif
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#if defined(CPU_COLDFIRE) || defined(CPU_ARM)
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#if defined(CPU_COLDFIRE)
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.bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram):
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#elif defined(CPU_ARM)
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.bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors):
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#else
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.bss :
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#endif
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@ -84,13 +84,13 @@ remap_end:
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#endif /* PP specific */
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/* Copy exception handler code to address 0 */
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ldr r2, =ecode
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ldr r3, =ecodeend
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mov r4, #0
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ldr r2, =_vectorsstart
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ldr r3, =_vectorsend
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ldr r4, =_vectorscopy
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1:
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cmp r3, r2
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ldrhi r5, [r2], #4
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strhi r5, [r4], #4
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ldrhi r5, [r4], #4
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strhi r5, [r2], #4
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bhi 1b
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/* Zero out IBSS */
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@ -259,7 +259,7 @@ boot_table:
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/* main() should never return */
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/* Exception handlers. Will be copied to address 0 after memory remapping */
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ecode:
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.section .vectors,"aw"
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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@ -270,6 +270,8 @@ ecode:
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ldr pc, [pc, #24]
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/* Exception vectors */
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.global vectors
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vectors:
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.word start
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.word undef_instr_handler
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.word software_int_handler
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@ -278,7 +280,8 @@ ecode:
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.word reserved_handler
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.word irq_handler
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.word fiq_handler
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ecodeend:
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.text
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.global irq
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.global UIE
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