forked from len0rd/rockbox
FS#6096. Recording on PortalPlayer targets (H10, iPod Video, iPod 4g, iPod Color, iPod Nano).
* Fix failed compile of enc_config.c when HAVE_MPEG2_SAMPR is not defined. * Fix bug in AIFF encoder header creation on little endian targets. * Add recording screen keymaps for H10 and iPod. * Move pcm_playback PP specific code to target tree. * Add recording code to wmcodec drivers. * Add pcm_record code. Some problems still remain: * Playback doesn't work after recording until Rockbox is restarted. * Gain control not implemented. * Only 16-bit/44KHz for now. The hardware should be capable of up to 24-bit/96KHz. * Line-in recording not tested on H10. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11794 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Barry Wardell
parent
440353a9aa
commit
df0dc2262e
24 changed files with 961 additions and 369 deletions
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@ -98,326 +98,6 @@ size_t pcm_get_bytes_waiting(void)
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return 0;
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}
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#elif defined(HAVE_WM8975) || defined(HAVE_WM8758) \
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|| defined(HAVE_WM8731) || defined(HAVE_WM8721) \
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|| defined(HAVE_PP5024_CODEC)
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/* We need to unify this code with the uda1380 code as much as possible, but
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we will keep it separate during early development.
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*/
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#if CONFIG_CPU == PP5020
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#define FIFO_FREE_COUNT ((IISFIFO_CFG & 0x3f0000) >> 16)
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#elif CONFIG_CPU == PP5002
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#define FIFO_FREE_COUNT ((IISFIFO_CFG & 0x7800000) >> 23)
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#elif CONFIG_CPU == PP5024
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#define FIFO_FREE_COUNT 4 /* TODO: make this sensible */
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#endif
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static int pcm_freq = HW_SAMPR_DEFAULT; /* 44.1 is default */
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/* NOTE: The order of these two variables is important if you use the iPod
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assembler optimised fiq handler, so don't change it. */
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unsigned short* p IBSS_ATTR;
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size_t p_size IBSS_ATTR;
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void pcm_play_dma_start(const void *addr, size_t size)
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{
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p=(unsigned short*)addr;
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p_size=size;
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pcm_playing = true;
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#if CONFIG_CPU == PP5020
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/* setup I2S interrupt for FIQ */
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outl(inl(0x6000402c) | I2S_MASK, 0x6000402c);
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outl(I2S_MASK, 0x60004024);
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#elif CONFIG_CPU == PP5024
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#else
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/* setup I2S interrupt for FIQ */
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outl(inl(0xcf00102c) | DMA_OUT_MASK, 0xcf00102c);
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outl(DMA_OUT_MASK, 0xcf001024);
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#endif
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/* Clear the FIQ disable bit in cpsr_c */
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enable_fiq();
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/* Enable playback FIFO */
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#if CONFIG_CPU == PP5020
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IISCONFIG |= 0x20000000;
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#elif CONFIG_CPU == PP5002
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IISCONFIG |= 0x4;
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#endif
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/* Fill the FIFO - we assume there are enough bytes in the pcm buffer to
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fill the 32-byte FIFO. */
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while (p_size > 0) {
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if (FIFO_FREE_COUNT < 2) {
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/* Enable interrupt */
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#if CONFIG_CPU == PP5020
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IISCONFIG |= 0x2;
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#elif CONFIG_CPU == PP5002
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IISFIFO_CFG |= (1<<9);
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#endif
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return;
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}
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IISFIFO_WR = (*(p++))<<16;
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IISFIFO_WR = (*(p++))<<16;
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p_size-=4;
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}
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}
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/* Stops the DMA transfer and interrupt */
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void pcm_play_dma_stop(void)
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{
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pcm_playing = false;
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#if CONFIG_CPU == PP5020
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/* Disable playback FIFO */
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IISCONFIG &= ~0x20000000;
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/* Disable the interrupt */
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IISCONFIG &= ~0x2;
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#elif CONFIG_CPU == PP5002
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/* Disable playback FIFO */
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IISCONFIG &= ~0x4;
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/* Disable the interrupt */
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IISFIFO_CFG &= ~(1<<9);
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#endif
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disable_fiq();
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}
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void pcm_play_pause_pause(void)
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{
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#if CONFIG_CPU == PP5020
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/* Disable the interrupt */
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IISCONFIG &= ~0x2;
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/* Disable playback FIFO */
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IISCONFIG &= ~0x20000000;
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#elif CONFIG_CPU == PP5002
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/* Disable the interrupt */
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IISFIFO_CFG &= ~(1<<9);
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/* Disable playback FIFO */
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IISCONFIG &= ~0x4;
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#endif
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disable_fiq();
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}
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void pcm_play_pause_unpause(void)
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{
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/* Enable the FIFO and fill it */
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enable_fiq();
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/* Enable playback FIFO */
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#if CONFIG_CPU == PP5020
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IISCONFIG |= 0x20000000;
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#elif CONFIG_CPU == PP5002
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IISCONFIG |= 0x4;
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#endif
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/* Fill the FIFO - we assume there are enough bytes in the
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pcm buffer to fill the 32-byte FIFO. */
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while (p_size > 0) {
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if (FIFO_FREE_COUNT < 2) {
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/* Enable interrupt */
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#if CONFIG_CPU == PP5020
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IISCONFIG |= 0x2;
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#elif CONFIG_CPU == PP5002
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IISFIFO_CFG |= (1<<9);
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#endif
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return;
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}
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IISFIFO_WR = (*(p++))<<16;
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IISFIFO_WR = (*(p++))<<16;
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p_size-=4;
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}
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}
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void pcm_set_frequency(unsigned int frequency)
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{
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(void)frequency;
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pcm_freq = HW_SAMPR_DEFAULT;
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}
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size_t pcm_get_bytes_waiting(void)
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{
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return p_size;
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}
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/* ASM optimised FIQ handler. GCC fails to make use of the fact that FIQ mode
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has registers r8-r14 banked, and so does not need to be saved. This routine
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uses only these registers, and so will never touch the stack unless it
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actually needs to do so when calling pcm_callback_for_more. C version is
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still included below for reference.
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*/
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#if CONFIG_CPU == PP5020 || CONFIG_CPU == PP5002
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void fiq(void) ICODE_ATTR __attribute__((naked));
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void fiq(void)
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{
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/* r12 contains IISCONFIG address (set in crt0.S to minimise code in actual
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* FIQ handler. r11 contains address of p (also set in crt0.S). Most other
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* addresses we need are generated by using offsets with these two.
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* r12 + 0x40 is IISFIFO_WR, and r12 + 0x0c is IISFIFO_CFG.
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* r8 and r9 contains local copies of p_size and p respectively.
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* r10 is a working register.
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*/
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asm volatile (
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#if CONFIG_CPU == PP5002
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"ldr r10, =0xcf001040 \n\t" /* Some magic from iPodLinux */
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"ldr r10, [r10] \n\t"
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"ldr r10, [r12, #0x1c]\n\t"
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"bic r10, r10, #0x200 \n\t" /* clear interrupt */
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"str r10, [r12, #0x1c]\n\t"
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#else
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"ldr r10, [r12] \n\t"
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"bic r10, r10, #0x2 \n\t" /* clear interrupt */
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"str r10, [r12] \n\t"
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#endif
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"ldr r8, [r11, #4] \n\t" /* r8 = p_size */
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"ldr r9, [r11] \n\t" /* r9 = p */
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".loop: \n\t"
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"cmp r8, #0 \n\t" /* is p_size 0? */
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"beq .more_data \n\t" /* if so, ask pcmbuf for more data */
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".fifo_loop: \n\t"
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#if CONFIG_CPU == PP5002
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"ldr r10, [r12, #0x1c]\n\t" /* read IISFIFO_CFG to check FIFO status */
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"and r10, r10, #0x7800000\n\t"
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"cmp r10, #0x800000 \n\t"
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#else
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"ldr r10, [r12, #0x0c]\n\t" /* read IISFIFO_CFG to check FIFO status */
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"and r10, r10, #0x3f0000\n\t"
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"cmp r10, #0x10000 \n\t"
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#endif
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"bls .fifo_full \n\t" /* FIFO full, exit */
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"ldr r10, [r9], #4 \n\t" /* load two samples */
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"mov r10, r10, ror #16\n\t" /* put left sample at the top bits */
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"str r10, [r12, #0x40]\n\t" /* write top sample, lower sample ignored */
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"mov r10, r10, lsl #16\n\t" /* shift lower sample up */
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"str r10, [r12, #0x40]\n\t" /* then write it */
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"subs r8, r8, #4 \n\t" /* check if we have more samples */
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"bne .fifo_loop \n\t" /* yes, continue */
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".more_data: \n\t"
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"stmdb sp!, { r0-r3, r12, lr}\n\t" /* stack scratch regs and lr */
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"mov r0, r11 \n\t" /* r0 = &p */
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"add r1, r11, #4 \n\t" /* r1 = &p_size */
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"str r9, [r0] \n\t" /* save internal copies of variables back */
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"str r8, [r1] \n\t"
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"ldr r2, =pcm_callback_for_more\n\t"
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"ldr r2, [r2] \n\t" /* get callback address */
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"cmp r2, #0 \n\t" /* check for null pointer */
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"movne lr, pc \n\t" /* call pcm_callback_for_more */
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"bxne r2 \n\t"
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"ldmia sp!, { r0-r3, r12, lr}\n\t"
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"ldr r8, [r11, #4] \n\t" /* reload p_size and p */
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"ldr r9, [r11] \n\t"
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"cmp r8, #0 \n\t" /* did we actually get more data? */
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"bne .loop \n\t" /* yes, continue to try feeding FIFO */
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".dma_stop: \n\t" /* no more data, do dma_stop() and exit */
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"ldr r10, =pcm_playing\n\t"
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"strb r8, [r10] \n\t" /* pcm_playing = false (r8=0, look above) */
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"ldr r10, [r12] \n\t"
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#if CONFIG_CPU == PP5002
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"bic r10, r10, #0x4\n\t" /* disable playback FIFO */
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"str r10, [r12] \n\t"
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"ldr r10, [r12, #0x1c] \n\t"
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"bic r10, r10, #0x200 \n\t" /* clear interrupt */
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"str r10, [r12, #0x1c] \n\t"
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#else
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"bic r10, r10, #0x20000002\n\t" /* disable playback FIFO and IRQ */
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"str r10, [r12] \n\t"
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#endif
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"mrs r10, cpsr \n\t"
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"orr r10, r10, #0x40 \n\t" /* disable FIQ */
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"msr cpsr_c, r10 \n\t"
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".exit: \n\t"
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"str r8, [r11, #4] \n\t"
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"str r9, [r11] \n\t"
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"subs pc, lr, #4 \n\t" /* FIQ specific return sequence */
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".fifo_full: \n\t" /* enable IRQ and exit */
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#if CONFIG_CPU == PP5002
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"ldr r10, [r12, #0x1c]\n\t"
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"orr r10, r10, #0x200 \n\t" /* set interrupt */
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"str r10, [r12, #0x1c]\n\t"
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#else
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"ldr r10, [r12] \n\t"
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"orr r10, r10, #0x2 \n\t" /* set interrupt */
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"str r10, [r12] \n\t"
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#endif
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"b .exit \n\t"
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);
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}
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#else /* !(CONFIG_CPU == PP5020 || CONFIG_CPU == PP5002) */
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void fiq(void) ICODE_ATTR __attribute__ ((interrupt ("FIQ")));
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void fiq(void)
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{
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/* Clear interrupt */
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#if CONFIG_CPU == PP5020
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IISCONFIG &= ~0x2;
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#elif CONFIG_CPU == PP5002
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inl(0xcf001040);
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IISFIFO_CFG &= ~(1<<9);
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#endif
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do {
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while (p_size) {
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if (FIFO_FREE_COUNT < 2) {
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/* Enable interrupt */
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#if CONFIG_CPU == PP5020
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IISCONFIG |= 0x2;
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#elif CONFIG_CPU == PP5002
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IISFIFO_CFG |= (1<<9);
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#endif
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return;
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}
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IISFIFO_WR = (*(p++))<<16;
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IISFIFO_WR = (*(p++))<<16;
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p_size-=4;
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}
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/* p is empty, get some more data */
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if (pcm_callback_for_more) {
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pcm_callback_for_more((unsigned char**)&p,&p_size);
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}
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} while (p_size);
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/* No more data, so disable the FIFO/FIQ */
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pcm_play_dma_stop();
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}
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#endif /* CONFIG_CPU == PP5020 || CONFIG_CPU == PP5002 */
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#ifdef HAVE_PP5024_CODEC
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void pcm_init(void)
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{
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}
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#else
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void pcm_init(void)
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{
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pcm_playing = false;
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pcm_paused = false;
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pcm_callback_for_more = NULL;
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/* Initialize default register values. */
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audiohw_init();
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/* Power on */
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audiohw_enable_output(true);
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/* Unmute the master channel (DAC should be at zero point now). */
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audiohw_mute(false);
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/* Call pcm_play_dma_stop to initialize everything. */
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pcm_play_dma_stop();
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}
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#endif /* HAVE_PP5024_CODEC */
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#elif (CONFIG_CPU == PNX0101)
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#define DMA_BUF_SAMPLES 0x100
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@ -608,7 +288,7 @@ void pcm_mute(bool mute)
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if (mute)
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sleep(HZ/16);
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}
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#if !defined(CPU_PP)
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/*
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* This function goes directly into the DMA buffer to calculate the left and
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* right peak values. To avoid missing peaks it tries to look forward two full
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@ -632,9 +312,7 @@ void pcm_calculate_peaks(int *left, int *right)
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short *addr;
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short *end;
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{
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#if defined(HAVE_WM8975) || defined(HAVE_WM8758) \
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|| defined(HAVE_WM8731) || defined(HAVE_WM8721) \
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|| (CONFIG_CPU == PNX0101) || defined(HAVE_PP5024_CODEC)
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#if CONFIG_CPU == PNX0101
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size_t samples = p_size / 4;
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addr = p;
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#endif
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@ -690,7 +368,7 @@ void pcm_calculate_peaks(int *left, int *right)
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}
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#endif
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}
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#endif
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#endif /* CPU_COLDFIRE */
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/****************************************************************************
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