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gigabeat S: Set the tick speed correctly (calced from clocking regdump). Use bit #defines instead as well. Throw a header in the file.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16928 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2008-04-02 05:17:05 +00:00
parent 404a204e58
commit dd88663fe0
1 changed files with 41 additions and 20 deletions
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61
firmware/target/arm/imx31/gigabeat-s/kernel-imx31.c
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@ -1,9 +1,26 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id$
*
* Copyright (C) 2007 by Michael Sevakis
*
* All files in this archive are subject to the GNU General Public License.
* See the file COPYING in the source tree root for full license agreement.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#include "config.h"
#include "system.h"
#include "avic-imx31.h"
#include "kernel.h"
#include "thread.h"
#include <stdio.h>
extern void (*tick_funcs[MAX_NUM_TICK_TASKS])(void);
@ -11,7 +28,7 @@ static __attribute__((interrupt("IRQ"))) void EPIT1_HANDLER(void)
{
int i;
EPITSR1 = 1; /* Clear the pending status */
EPITSR1 = EPITSR_OCIF; /* Clear the pending status */
/* Run through the list of tick tasks */
for(i = 0;i < MAX_NUM_TICK_TASKS;i++)
@ -25,31 +42,35 @@ static __attribute__((interrupt("IRQ"))) void EPIT1_HANDLER(void)
void tick_start(unsigned int interval_in_ms)
{
CLKCTL_CGR0 |= (3 << 6); /* EPIT1 module clock ON - before writing regs! */
EPITCR1 &= ~((1 << 2) | (1 << 0)); /* Disable the counter */
CLKCTL_WIMR0 &= ~(1 << 23); /* Clear wakeup mask */
CLKCTL_CGR0 |= CGR0_EPIT1(CG_ON_ALL); /* EPIT1 module clock ON -
before writing regs! */
EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable the counter */
CLKCTL_WIMR0 &= ~(1 << 23); /* Clear wakeup mask */
/* NOTE: This isn't really accurate yet but it's close enough to work
* with for the moment */
/* CLKSRC=32KHz, EPIT Output Disconnected, Enabled
* prescale 1/32, Reload from modulus register, Compare interrupt enabled,
/* mcu_main_clk = 528MHz = 27MHz * 2 * ((9 + 7/9) / 1)
* CLKSRC = ipg_clk = 528MHz / 4 / 2 = 66MHz,
* EPIT Output Disconnected,
* Enabled in wait mode
* Prescale 1/2640 for 25KHz
* Reload from modulus register,
* Compare interrupt enabled,
* Count from load value */
EPITCR1 = (3 << 24) | (1 << 19) | (32 << 4) |
(1 << 3) | (1 << 2) | (1 << 1);
EPITLR1 = interval_in_ms; /* Count down from interval */
EPITCMPR1 = 0; /* Event when counter reaches 0 */
EPITSR1 = 1; /* Clear any pending interrupt */
EPITCR1 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW |
EPITCR_PRESCALER(2640-1) | EPITCR_RLD | EPITCR_OCIEN |
EPITCR_ENMOD;
EPITLR1 = interval_in_ms*25; /* Count down from interval */
EPITCMPR1 = 0; /* Event when counter reaches 0 */
EPITSR1 = EPITSR_OCIF; /* Clear any pending interrupt */
avic_enable_int(EPIT1, IRQ, 7, EPIT1_HANDLER);
EPITCR1 |= (1 << 0); /* Enable the counter */
EPITCR1 |= EPITCR_EN; /* Enable the counter */
}
#ifdef BOOTLOADER
void tick_stop(void)
{
avic_disable_int(EPIT1); /* Disable insterrupt */
EPITCR1 &= ~((1 << 2) | (1 << 0)); /* Disable counter */
CLKCTL_CGR0 &= ~(3 << 6); /* EPIT1 module clock OFF */
avic_disable_int(EPIT1); /* Disable insterrupt */
EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable counter */
CLKCTL_CGR0 &= ~CGR0_EPIT1(CG_MASK); /* EPIT1 module clock OFF */
}
#endif