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iriver: Moved the I2C prescaler setting to i2c_init(), and removed it from set_cpu_frequency(). The Coldfire I2C controller can't handle on-the-fly prescaler changes. Also removed the unnecessary slave address setting in i2c_init.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7304 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Linus Nielsen Feltzing 2005-08-11 19:00:55 +00:00
parent 5a8eac1a5a
commit dc4a6b828e
2 changed files with 4 additions and 11 deletions
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6
firmware/drivers/i2c-coldfire.c
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@ -37,15 +37,17 @@ static volatile unsigned char *i2c_get_addr(int device);
void i2c_init(void) void i2c_init(void)
{ {
/* I2C Clock divisor = 576 => 119.952 MHz / 2 / 576 = 104.125 kHz */
MFDR = 0x14;
MFDR2 = 0x14;
#if (CONFIG_KEYPAD == IRIVER_H100_PAD) || (CONFIG_KEYPAD == IRIVER_H300_PAD) #if (CONFIG_KEYPAD == IRIVER_H100_PAD) || (CONFIG_KEYPAD == IRIVER_H300_PAD)
/* Audio Codec */ /* Audio Codec */
MADR = 0x6c; /* iRiver firmware uses this addr */
MBDR = 0; /* iRiver firmware does this */ MBDR = 0; /* iRiver firmware does this */
MBCR = IEN; /* Enable interface */ MBCR = IEN; /* Enable interface */
#if 0 #if 0
/* FM Tuner */ /* FM Tuner */
MADR2 = 0x6c;
MBDR2 = 0; MBDR2 = 0;
MBCR2 = IEN; MBCR2 = IEN;
#endif #endif

9
firmware/system.c
View file

@ -529,9 +529,6 @@ void set_cpu_frequency(long frequency)
tick_start(1000/HZ); tick_start(1000/HZ);
IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */ IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */
/* I2C Clock divisor = 576 => 119.952 MHz / 2 / 576 = 104.125 kHz */
MFDR = 0x14;
MFDR2 = 0x14;
break; break;
case CPUFREQ_NORMAL: case CPUFREQ_NORMAL:
@ -548,9 +545,6 @@ void set_cpu_frequency(long frequency)
tick_start(1000/HZ); tick_start(1000/HZ);
IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
/* I2C Clock divisor = 240 => 47.9808 MHz / 2 / 240 = 99.96 kHz */
MFDR = 0x0f;
MFDR2 = 0x0f;
break; break;
default: default:
DCR = (DCR & ~0x01ff) | 1; /* Refresh timer for bypass DCR = (DCR & ~0x01ff) | 1; /* Refresh timer for bypass
@ -562,9 +556,6 @@ void set_cpu_frequency(long frequency)
tick_start(1000/HZ); tick_start(1000/HZ);
IDECONFIG1 = 0x106000 | (1 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ IDECONFIG1 = 0x106000 | (1 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
/* I2C Clock divisor = 56 => 11.2896 MHz / 56 = 100.8 kHz */
MFDR = 0x06;
MFDR2 = 0x06;
break; break;
} }
} }