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Serial DMA works

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@483 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Linus Nielsen Feltzing 2002-05-06 19:25:40 +00:00
parent 1e0323a1bd
commit dba731f4b5
2 changed files with 120 additions and 127 deletions
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8
firmware/test/i2c/Makefile
View file

@ -10,8 +10,8 @@ CFLAGS = -g -Wall -m1 -nostdlib -Wstrict-prototypes -fschedule-insns -fno-builti
AFLAGS += -small -relax AFLAGS += -small -relax
OBJS= ../../crt0.o main.o ../../drivers/i2c.o ../../drivers/mas.o \ OBJS= ../../crt0.o main.o ../../drivers/i2c.o ../../drivers/mas.o \
../../debug.o ../../kernel.o ../../thread.o ../../common/sprintf.o \ ../../debug.o ../../kernel.o thread.o ../../common/sprintf.o \
../../panic.o mp3data.o ../../panic.o ../../system.o ../../drivers/led.o mp3data.o
%.o: %.S %.o: %.S
$(CC) -o $@ $(CFLAGS) $(INCLUDES) $(DEFS) -c $< $(CC) -o $@ $(CFLAGS) $(INCLUDES) $(DEFS) -c $<
@ -44,3 +44,7 @@ clean:
install: install:
mount /mnt/archos; cp archos.mod /mnt/archos; umount /mnt/archos mount /mnt/archos; cp archos.mod /mnt/archos; umount /mnt/archos
thread.o: ../../thread.c
$(CC) -O $(CFLAGS) -c $<

239
firmware/test/i2c/main.c
View file

@ -16,10 +16,12 @@
* KIND, either express or implied. * KIND, either express or implied.
* *
****************************************************************************/ ****************************************************************************/
#include "types.h"
#include "i2c.h" #include "i2c.h"
#include "mas.h" #include "mas.h"
#include "sh7034.h" #include "sh7034.h"
#include "debug.h" #include "debug.h"
#include "kernel.h"
unsigned char fliptable[] = unsigned char fliptable[] =
{ {
@ -59,10 +61,14 @@ unsigned char fliptable[] =
extern unsigned char mp3data[]; extern unsigned char mp3data[];
extern int mp3datalen; extern int mp3datalen;
unsigned char *mp3dataptr;
int mp3_transmitted;
bool dma_on;
void setup_sci0(void) void setup_sci0(void)
{ {
PBCR1 = (PBCR1 & 0xccff) | 0x0200; PBCR1 = (PBCR1 & 0xccff) | 0x1200;
/* set PB12 to output */ /* set PB12 to output */
PBIOR |= 0x1000; PBIOR |= 0x1000;
@ -86,19 +92,20 @@ void setup_sci0(void)
IPRD &= 0x0ff0; IPRD &= 0x0ff0;
/* set IRQ6 and IRQ7 to edge detect */ /* set IRQ6 and IRQ7 to edge detect */
// ICR |= 0x03; ICR |= 0x03;
/* set PB15 and PB14 to inputs */ /* set PB15 and PB14 to inputs */
PBIOR &= 0x7fff; PBIOR &= 0x7fff;
PBIOR &= 0xbfff; PBIOR &= 0xbfff;
/* set IRQ6 prio 8 and IRQ7 prio 0 */ /* set IRQ6 prio 8 and IRQ7 prio 0 */
// IPRB = ( IPRB & 0xff00 ) | 0x80; IPRB = ( IPRB & 0xff00 ) | 0x0080;
IPRB = 0; /* Enable End of DMA interrupt at prio 8 */
IPRC = (IPRC & 0xf0ff) | 0x0800;
/* Enable Tx (only!) */ /* Enable Tx (only!) */
SCR0 |= 0xa0; // SCR0 |= 0xa0;
} }
int mas_tx_ready(void) int mas_tx_ready(void)
@ -109,160 +116,142 @@ int mas_tx_ready(void)
void init_dma(void) void init_dma(void)
{ {
SAR3 = (unsigned int) mp3data; SAR3 = (unsigned int) mp3data;
DAR3 = 0xFFFFEC3; DAR3 = 0x5FFFEC3;
CHCR3 = 0x1500; /* Single address destination, TXI0 */ CHCR3 &= ~0x0002; /* Clear interrupt */
CHCR3 = 0x1504; /* Single address destination, TXI0, IE=1 */
DTCR3 = 64000; DTCR3 = 64000;
DMAOR = 0x0001; /* Enable DMA */ DMAOR = 0x0001; /* Enable DMA */
} }
void start_dma(void) void start_dma(void)
{ {
CHCR3 |= 1; SCR0 |= 0x80;
dma_on = TRUE;
} }
void stop_dma(void) void stop_dma(void)
{ {
CHCR3 &= ~1; SCR0 &= 0x7f;
dma_on = FALSE;
} }
void dma_tick(void)
{
if(!dma_on)
{
if(PBDR & 0x4000)
{
if(!(SCR0 & 0x80))
start_dma();
}
}
}
int main(void) int main(void)
{ {
char buf[40]; char buf[40];
char str[32]; char str[32];
int i=0; int i=0;
int dma_on = 0;
/* Clear it all! */ /* Clear it all! */
SSR1 &= ~(SCI_RDRF | SCI_ORER | SCI_PER | SCI_FER); SSR1 &= ~(SCI_RDRF | SCI_ORER | SCI_PER | SCI_FER);
/* This enables the serial Rx interrupt, to be able to exit into the /* This enables the serial Rx interrupt, to be able to exit into the
debugger when you hit CTRL-C */ debugger when you hit CTRL-C */
SCR1 |= 0x40; SCR1 |= 0x40;
SCR1 &= ~0x80; SCR1 &= ~0x80;
asm ("ldc\t%0,sr" : : "r"(0<<4));
debugf("Olle: %d\n", 7); i2c_init();
dma_on = TRUE;
i2c_init(); kernel_init();
debugf("I2C Init done\n"); tick_add_task(dma_tick);
i=mas_readmem(MAS_BANK_D1,0xff6,(unsigned long*)buf,2);
if (i) {
debugf("Error - mas_readmem() returned %d\n", i);
while(1);
}
i = buf[0] | buf[1] << 8; set_irq_level(0);
debugf("MAS version: %x\n", i);
i = buf[4] | buf[5] << 8;
debugf("MAS revision: %x\n", i);
i=mas_readmem(MAS_BANK_D1,0xff9,(unsigned long*)buf,7); setup_sci0();
if (i) {
debugf("Error - mas_readmem() returned %d\n", i);
while(1);
}
for(i = 0;i < 7;i++) i=mas_readmem(MAS_BANK_D1,0xff6,(unsigned long*)buf,2);
{ if (i) {
str[i*2+1] = buf[i*4]; debugf("Error - mas_readmem() returned %d\n", i);
str[i*2] = buf[i*4+1]; while(1);
} }
str[i*2] = 0;
debugf("Description: %s\n", str);
i=mas_readreg(0xe6); i = buf[0] | buf[1] << 8;
if (i < 0) { debugf("MAS version: %x\n", i);
debugf("Error - mas_readreg() returned %d\n", i); i = buf[4] | buf[5] << 8;
while(1); debugf("MAS revision: %x\n", i);
}
debugf("Register 0xe6: %x\n", i); i=mas_readmem(MAS_BANK_D1,0xff9,(unsigned long*)buf,7);
if (i) {
debugf("Error - mas_readmem() returned %d\n", i);
while(1);
}
debugf("Writing register 0xaa\n"); for(i = 0;i < 7;i++)
{
i=mas_writereg(0xaa, 0x1); str[i*2+1] = buf[i*4];
if (i < 0) { str[i*2] = buf[i*4+1];
debugf("Error - mas_writereg() returned %d\n", i); }
while(1); str[i*2] = 0;
} debugf("Description: %s\n", str);
i=mas_readreg(0xaa); i=mas_writereg(0x3b, 0x20);
if (i < 0) { if (i < 0) {
debugf("Error - mas_readreg() returned %d\n", i); debugf("Error - mas_writereg() returned %d\n", i);
while(1); while(1);
} }
debugf("Register 0xaa: %x\n", i); i = mas_run(1);
if (i < 0) {
debugf("Writing register 0xaa again\n"); debugf("Error - mas_run() returned %d\n", i);
while(1);
i=mas_writereg(0xaa, 0); }
if (i < 0) {
debugf("Error - mas_writereg() returned %d\n", i);
while(1);
}
i=mas_readreg(0xaa);
if (i < 0) {
debugf("Error - mas_readreg() returned %d\n", i);
while(1);
}
debugf("Register 0xaa: %x\n", i);
i=mas_readreg(0xed);
if (i < 0) {
debugf("Error - mas_readreg(ed) returned %d\n", i);
while(1);
}
debugf("Register 0xed: %x\n", i);
i=mas_writereg(0x3b, 0x20);
if (i < 0) {
debugf("Error - mas_writereg() returned %d\n", i);
while(1);
}
i = mas_run(1);
if (i < 0) {
debugf("Error - mas_run() returned %d\n", i);
while(1);
}
setup_sci0(); for(i = 0;i < mp3datalen;i++)
{
mp3data[i] = fliptable[mp3data[i]];
}
i = 0; while(1)
{
debugf("let's play...\n");
init_dma();
mp3dataptr = mp3data;
mp3_transmitted = 0;
dma_on = TRUE;
/* Enable Tx (only!) */
SCR0 |= 0xa0;
CHCR3 |= 1;
init_dma(); debugf("sleeping...\n");
sleep(10000);
while(1) }
{ }
/* Demand pin high? */
if(PBDR & 0x4000) #pragma interrupt
{ void IRQ6(void)
start_dma(); {
#if 0 stop_dma();
/* More data to write? */ }
if(i < mp3datalen)
{ #pragma interrupt
/* Transmitter ready? */ void DEI3(void)
while(!mas_tx_ready()){}; {
mp3_transmitted += 64000;
/* Write data into TDR and clear TDRE */ if(mp3_transmitted < mp3datalen)
TDR0 = fliptable[mp3data[i++]]; {
SSR0 &= ~SCI_TDRE; DTCR3 = 64000;
} CHCR3 &= ~0x0002;
#endif }
} else
else {
{ CHCR3 = 0;
stop_dma(); }
}
}
while(1);
} }