forked from len0rd/rockbox
jz4760b/regtools: fix/rename some register fields, add clock analyzer to qeditor
Change-Id: I196414d6e4fc18c00b77903e334b7e6adfb7debc
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51cce81cd4
commit
d91d9f6851
3 changed files with 87 additions and 6 deletions
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@ -1017,14 +1017,14 @@
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</instance>
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<register>
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<field>
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<name>SRC_SEL</name>
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<name>OUT_SEL</name>
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<position>30</position>
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<enum>
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<name>EXCLK</name>
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<name>LCD_PANEL</name>
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<value>0x0</value>
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</enum>
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<enum>
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<name>PLL</name>
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<name>TV_ENC</name>
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<value>0x1</value>
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</enum>
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</field>
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@ -1427,7 +1427,7 @@
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<node>
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<name>COUNTH_BUF</name>
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<instance>
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<name>OSTCNTH_BUF</name>
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<name>COUNTH_BUF</name>
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<address>0xfc</address>
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</instance>
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<register/>
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@ -2222,7 +2222,7 @@
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<name>TRIGGER</name>
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<title>Trigger</title>
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<instance>
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<name>TRG</name>
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<name>TRIGGER</name>
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<range>
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<first>0</first>
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<count>6</count>
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@ -84,7 +84,10 @@ QWidget *ClockAnalyser::GetWidget()
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bool ClockAnalyser::SupportSoc(const QString& soc_name)
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{
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return (soc_name == "imx233" || soc_name == "rk27xx" || soc_name == "atj213x");
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return soc_name == "imx233"
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|| soc_name == "rk27xx"
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|| soc_name == "atj213x"
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|| soc_name == "jz4760b";
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}
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QString ClockAnalyser::GetFreq(unsigned freq)
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@ -137,10 +140,87 @@ void ClockAnalyser::FillTree()
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if(m_soc.get()->name == "imx233") FillTreeIMX233();
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else if(m_soc.get()->name == "rk27xx") FillTreeRK27XX();
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else if(m_soc.get()->name == "atj213x") FillTreeATJ213X();
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else if(m_soc.get()->name == "jz4760b") FillTreeJZ4760B();
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m_tree_widget->expandAll();
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m_tree_widget->resizeColumnToContents(0);
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}
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void ClockAnalyser::FillTreeJZ4760B()
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{
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AddClock(0, "RTCLK", 32768);
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// assume EXCLK is 12MHz, we have no way to knowing for sure but this is the
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// recommended value anyway
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QTreeWidgetItem *exclk = AddClock(0, "EXCLK", 12000000);
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// PLL0
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soc_word_t pllm, plln, pllod, pllbypass;
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QTreeWidgetItem *pll0 = 0;
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if(ReadFieldOld("CPM", "PLLCTRL0", "FEED_DIV", pllm) &&
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ReadFieldOld("CPM", "PLLCTRL0", "IN_DIV", plln) &&
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ReadFieldOld("CPM", "PLLCTRL0", "OUT_DIV", pllod) &&
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ReadFieldOld("CPM", "PLLCTRL0", "BYPASS", pllbypass))
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{
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pll0 = AddClock(exclk, "PLL0", FROM_PARENT, pllbypass ? 1 : 2 * pllm,
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pllbypass ? 1 : plln * (1 << pllod));
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}
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else
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pll0 = AddClock(exclk, "PLL0", INVALID);
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// PLL1
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soc_word_t plldiv, src_sel;
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QTreeWidgetItem *pll1 = 0;
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if(ReadFieldOld("CPM", "PLLCTRL1", "FEED_DIV", pllm) &&
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ReadFieldOld("CPM", "PLLCTRL1", "IN_DIV", plln) &&
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ReadFieldOld("CPM", "PLLCTRL1", "OUT_DIV", pllod) &&
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ReadFieldOld("CPM", "PLLCTRL1", "SRC_SEL", src_sel) &&
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ReadFieldOld("CPM", "PLLCTRL1", "PLL0_DIV", plldiv))
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{
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pll1 = AddClock(src_sel ? pll0 : exclk, "PLL1", FROM_PARENT, 2 * pllm,
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plln * (1 << pllod) * (src_sel ? plldiv : 1));
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}
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else
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pll1 = AddClock(exclk, "PLL1", INVALID);
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// system clocks
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const int NR_SYSCLK = 6;
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const char *sysclk[NR_SYSCLK] = { "CCLK", "SCLK", "PCLK", "HCLK", "H2CLK", "MCLK"};
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for(int i = 0; i < NR_SYSCLK; i++)
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{
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soc_word_t div = 0;
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std::string field = std::string(sysclk[i]) + "_DIV";
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if(ReadFieldOld("CPM", "SYSCLK", field.c_str(), div))
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{
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switch(div)
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{
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case 0: div = 1; break;
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case 1: div = 2; break;
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case 2: div = 3; break;
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case 3: div = 4; break;
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case 4: div = 6; break;
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case 5: div = 8; break;
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default: div = 0; break;
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}
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}
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if(div != 0)
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AddClock(pll0, sysclk[i], FROM_PARENT, 1, div);
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else
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AddClock(pll0, sysclk[i], INVALID);
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}
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// common to msc, i2s, lcd, uhc, otg, ssi, pcm, gpu, gps
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soc_word_t pll_div;
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if(ReadFieldOld("CPM", "SYSCLK", "PLL_DIV", pll_div))
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pll_div = pll_div ? 1 : 2;
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else
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pll_div = 1; // error
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// lcd
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soc_word_t pll_sel, div;
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if(ReadFieldOld("CPM", "LCDCLK", "DIV", div) &&
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ReadFieldOld("CPM", "LCDCLK", "PLL_SEL", pll_sel))
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{
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AddClock(pll_sel ? pll1 : pll0, "LCDCLK",
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FROM_PARENT, 1, pll_div * (div + 1));
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}
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else
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AddClock(exclk, "LCDCLK", INVALID);
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}
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void ClockAnalyser::FillTreeATJ213X()
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{
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soc_word_t pllbypass, pllclk, en, coreclks, tmp0, tmp1, tmp2, tmp3;
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@ -77,6 +77,7 @@ private:
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void FillTreeIMX233();
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void FillTreeRK27XX();
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void FillTreeATJ213X();
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void FillTreeJZ4760B();
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private:
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QGroupBox *m_group;
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