forked from len0rd/rockbox
* Move some more stuff to the general SD driver
* Ingenic SD driver: cleanup DMA part a bit (not working yet) git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21606 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
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90d7a8c4fc
commit
ccbd8f4f31
4 changed files with 49 additions and 81 deletions
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@ -62,3 +62,16 @@ void sd_parse_csd(tCardInfo *card)
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card->r2w_factor = card_extract_bits(card->csd, 28, 3);
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card->r2w_factor = card_extract_bits(card->csd, 28, 3);
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}
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}
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void sd_sleep(void)
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{
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}
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void sd_spin(void)
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{
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}
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void sd_spindown(int seconds)
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{
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(void)seconds;
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}
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@ -790,19 +790,6 @@ int sd_write_sectors(IF_MV2(int drive,) unsigned long start, int count,
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}
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}
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#ifndef BOOTLOADER
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#ifndef BOOTLOADER
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void sd_sleep(void)
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{
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}
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void sd_spin(void)
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{
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}
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void sd_spindown(int seconds)
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{
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(void)seconds;
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}
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long sd_last_disk_activity(void)
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long sd_last_disk_activity(void)
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{
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{
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return last_disk_activity;
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return last_disk_activity;
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@ -1372,16 +1372,3 @@ bool sd_present(IF_MV_NONVOID(int drive))
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return (card_info[drive].initialized && card_info[drive].numblocks > 0);
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return (card_info[drive].initialized && card_info[drive].numblocks > 0);
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}
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}
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#endif
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#endif
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void sd_sleep(void)
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{
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}
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void sd_spin(void)
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{
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}
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void sd_spindown(int seconds)
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{
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(void)seconds;
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}
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@ -732,80 +732,76 @@ static void jz_sd_get_response(struct sd_request *request)
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}
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}
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#ifdef SD_DMA_ENABLE
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#ifdef SD_DMA_ENABLE
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static int jz_sd_receive_data_dma(struct sd_request *req)
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static void jz_sd_receive_data_dma(struct sd_request *req)
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{
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{
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int ch = RX_DMA_CHANNEL;
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unsigned int size = req->block_len * req->nob;
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unsigned int size = req->block_len * req->nob;
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#if MMC_DMA_INTERRUPT
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unsigned char err = 0;
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unsigned char err = 0;
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#endif
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/* flush dcache */
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/* flush dcache */
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dma_cache_wback_inv((unsigned long) req->buffer, size);
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//dma_cache_wback_inv((unsigned long) req->buffer, size);
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/* setup dma channel */
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/* setup dma channel */
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REG_DMAC_DSAR(ch) = PHYSADDR(MSC_RXFIFO); /* DMA source addr */
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REG_DMAC_DSAR(DMA_SD_RX_CHANNEL) = PHYSADDR(MSC_RXFIFO); /* DMA source addr */
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REG_DMAC_DTAR(ch) = PHYSADDR((unsigned long) req->buffer); /* DMA dest addr */
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REG_DMAC_DTAR(DMA_SD_RX_CHANNEL) = PHYSADDR((unsigned long) req->buffer); /* DMA dest addr */
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REG_DMAC_DTCR(ch) = (size + 3) / 4; /* DMA transfer count */
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REG_DMAC_DTCR(DMA_SD_RX_CHANNEL) = (size + 3) / 4; /* DMA transfer count */
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REG_DMAC_DRSR(ch) = DMAC_DRSR_RS_MSCIN; /* DMA request type */
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REG_DMAC_DRSR(DMA_SD_RX_CHANNEL) = DMAC_DRSR_RS_MSCIN; /* DMA request type */
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#if SD_DMA_INTERRUPT
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#if SD_DMA_INTERRUPT
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REG_DMAC_DCMD(ch) =
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REG_DMAC_DCMD(DMA_SD_RX_CHANNEL) =
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DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
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DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
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DMAC_DCMD_DS_32BIT | DMAC_DCMD_TIE;
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DMAC_DCMD_DS_32BIT | DMAC_DCMD_TIE;
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REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
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REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
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OSSemPend(sd_dma_rx_sem, 100, &err);
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OSSemPend(sd_dma_rx_sem, 100, &err);
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#else
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#else
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REG_DMAC_DCMD(ch) =
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REG_DMAC_DCMD(DMA_SD_RX_CHANNEL) =
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DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
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DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
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DMAC_DCMD_DS_32BIT;
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DMAC_DCMD_DS_32BIT;
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REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
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REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
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while (REG_DMAC_DTCR(ch));
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#endif
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//while (REG_DMAC_DTCR(DMA_SD_RX_CHANNEL));
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/* clear status and disable channel */
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while( !(REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) & DMAC_DCCSR_TT) );
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REG_DMAC_DCCSR(ch) = 0;
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#if SD_DMA_INTERRUPT
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return (err == OS_NO_ERR);
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#else
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return 0;
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#endif
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#endif
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/* clear status and disable channel */
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REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) = 0;
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}
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}
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static int jz_sd_transmit_data_dma(struct sd_request *req)
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static void jz_mmc_transmit_data_dma(struct mmc_request *req)
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{
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{
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int ch = TX_DMA_CHANNEL;
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unsigned int size = req->block_len * req->nob;
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unsigned int size = req->block_len * req->nob;
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#if SD_DMA_INTERRUPT
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unsigned char err = 0;
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unsigned char err = 0;
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#endif
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/* flush dcache */
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/* flush dcache */
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dma_cache_wback_inv((unsigned long) req->buffer, size);
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//dma_cache_wback_inv((unsigned long) req->buffer, size);
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/* setup dma channel */
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/* setup dma channel */
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REG_DMAC_DSAR(ch) = PHYSADDR((unsigned long) req->buffer); /* DMA source addr */
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REG_DMAC_DSAR(DMA_SD_TX_CHANNEL) = PHYSADDR((unsigned long) req->buffer); /* DMA source addr */
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REG_DMAC_DTAR(ch) = PHYSADDR(MSC_TXFIFO); /* DMA dest addr */
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REG_DMAC_DTAR(DMA_SD_TX_CHANNEL) = PHYSADDR(MSC_TXFIFO); /* DMA dest addr */
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REG_DMAC_DTCR(ch) = (size + 3) / 4; /* DMA transfer count */
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REG_DMAC_DTCR(DMA_SD_TX_CHANNEL) = (size + 3) / 4; /* DMA transfer count */
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REG_DMAC_DRSR(ch) = DMAC_DRSR_RS_MSCOUT; /* DMA request type */
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REG_DMAC_DRSR(DMA_SD_TX_CHANNEL) = DMAC_DRSR_RS_MSCOUT; /* DMA request type */
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#if SD_DMA_INTERRUPT
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#if SD_DMA_INTERRUPT
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REG_DMAC_DCMD(ch) =
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REG_DMAC_DCMD(DMA_SD_TX_CHANNEL) =
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DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
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DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
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DMAC_DCMD_DS_32BIT | DMAC_DCMD_TIE;
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DMAC_DCMD_DS_32BIT | DMAC_DCMD_TIE;
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REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
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REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
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OSSemPend(sd_dma_tx_sem, 100, &err);
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OSSemPend(sd_dma_tx_sem, 100, &err);
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#else
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#else
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REG_DMAC_DCMD(ch) =
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REG_DMAC_DCMD(DMA_SD_TX_CHANNEL) =
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DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
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DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 |
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DMAC_DCMD_DS_32BIT;
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DMAC_DCMD_DS_32BIT;
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REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
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REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
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/* wait for dma completion */
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/* wait for dma completion */
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while (REG_DMAC_DTCR(ch));
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while( !(REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) & DMAC_DCCSR_TT) );
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#endif
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#endif
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/* clear status and disable channel */
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/* clear status and disable channel */
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REG_DMAC_DCCSR(ch) = 0;
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#if SD_DMA_INTERRUPT
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REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) = 0;
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return (err == OS_NO_ERR);
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#else
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return 0;
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#endif
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}
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}
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#endif /* SD_DMA_ENABLE */
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#else /* SD_DMA_ENABLE */
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static int jz_sd_receive_data(struct sd_request *req)
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static int jz_sd_receive_data(struct sd_request *req)
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{
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{
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@ -830,10 +826,9 @@ static int jz_sd_receive_data(struct sd_request *req)
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else if (stat & MSC_STAT_CRC_READ_ERROR)
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else if (stat & MSC_STAT_CRC_READ_ERROR)
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return SD_ERROR_CRC;
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return SD_ERROR_CRC;
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else if (!(stat & MSC_STAT_DATA_FIFO_EMPTY)
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else if (!(stat & MSC_STAT_DATA_FIFO_EMPTY)
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|| (stat & MSC_STAT_DATA_FIFO_AFULL)) {
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|| (stat & MSC_STAT_DATA_FIFO_AFULL))
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/* Ready to read data */
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/* Ready to read data */
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break;
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break;
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}
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udelay(1);
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udelay(1);
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}
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}
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@ -889,10 +884,8 @@ static int jz_sd_transmit_data(struct sd_request *req)
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MSC_STAT_CRC_WRITE_ERROR_NOSTS))
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MSC_STAT_CRC_WRITE_ERROR_NOSTS))
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return SD_ERROR_CRC;
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return SD_ERROR_CRC;
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else if (!(stat & MSC_STAT_DATA_FIFO_FULL))
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else if (!(stat & MSC_STAT_DATA_FIFO_FULL))
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{
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/* Ready to write data */
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/* Ready to write data */
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break;
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break;
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}
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udelay(1);
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udelay(1);
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}
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}
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@ -923,6 +916,7 @@ static int jz_sd_transmit_data(struct sd_request *req)
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return SD_NO_ERROR;
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return SD_NO_ERROR;
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}
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}
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#endif
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static inline unsigned int jz_sd_calc_clkrt(int is_sd, unsigned int rate)
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static inline unsigned int jz_sd_calc_clkrt(int is_sd, unsigned int rate)
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{
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{
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@ -1726,24 +1720,11 @@ int sd_write_sectors(IF_MV2(int drive,) unsigned long start, int count, const vo
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return retval;
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return retval;
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}
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}
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void sd_sleep(void)
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{
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}
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void sd_spin(void)
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{
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}
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long sd_last_disk_activity(void)
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long sd_last_disk_activity(void)
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{
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{
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return last_disk_activity;
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return last_disk_activity;
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}
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}
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void sd_spindown(int seconds)
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{
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(void)seconds;
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}
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#ifdef HAVE_HOTSWAP
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#ifdef HAVE_HOTSWAP
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bool sd_removable(IF_MV_NONVOID(int drive))
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bool sd_removable(IF_MV_NONVOID(int drive))
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{
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{
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