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x1000: support 2nd device ID byte for NAND flash

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Some components have additional ID bytes. Add support for an
optional 2nd device ID byte during the identification routine.

Change-Id: I5bbad73fb57004067c6f13f223f7bf4d43ff7849
This commit is contained in:
Aidan MacDonald 2022-06-07 17:35:40 +01:00
parent 131566b8f8
commit cc017f211a
2 changed files with 16 additions and 9 deletions
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17
firmware/target/mips/ingenic_x1000/nand-x1000.c
View file

@ -98,22 +98,25 @@ static bool identify_chip(nand_drv* drv)
* - 1 byte address, no dummy byte * - 1 byte address, no dummy byte
* - no address byte, 1 byte dummy * - no address byte, 1 byte dummy
* *
* Right now there is only a need for the 2nd variation, as that is * Currently we use the 2nd method, aka. address read ID.
* the method used by the ATO25D1GA.
*
* Some chips also output more than 2 ID bytes.
*/ */
sfc_exec(NANDCMD_READID(1, 0), 0, drv->scratch_buf, 2|SFC_READ); sfc_exec(NANDCMD_READID(1, 0), 0, drv->scratch_buf, 4|SFC_READ);
drv->mf_id = drv->scratch_buf[0]; drv->mf_id = drv->scratch_buf[0];
drv->dev_id = drv->scratch_buf[1]; drv->dev_id = drv->scratch_buf[1];
drv->dev_id2 = drv->scratch_buf[2];
for(size_t i = 0; i < nr_supported_nand_chips; ++i) { for(size_t i = 0; i < nr_supported_nand_chips; ++i) {
const nand_chip* chip = &supported_nand_chips[i]; const nand_chip* chip = &supported_nand_chips[i];
if(chip->mf_id == drv->mf_id && chip->dev_id == drv->dev_id) { if(chip->mf_id != drv->mf_id || chip->dev_id != drv->dev_id)
continue;
if((chip->flags & NAND_CHIPFLAG_HAS_DEVID2) &&
chip->dev_id2 != drv->dev_id2)
continue;
drv->chip = chip; drv->chip = chip;
return true; return true;
} }
}
return false; return false;
} }

4
firmware/target/mips/ingenic_x1000/nand-x1000.h
View file

@ -41,6 +41,8 @@
#define NAND_CHIPFLAG_QUAD 0x0001 #define NAND_CHIPFLAG_QUAD 0x0001
/* Chip requires QE bit set to enable quad I/O mode */ /* Chip requires QE bit set to enable quad I/O mode */
#define NAND_CHIPFLAG_HAS_QE_BIT 0x0002 #define NAND_CHIPFLAG_HAS_QE_BIT 0x0002
/* Chip has 2nd device ID byte */
#define NAND_CHIPFLAG_HAS_DEVID2 0x0004
/* cmd mode a d phase format has data */ /* cmd mode a d phase format has data */
#define NANDCMD_RESET SFC_CMD(0xff, SFC_TMODE_1_1_1, 0, 0, SFC_PFMT_ADDR_FIRST, 0) #define NANDCMD_RESET SFC_CMD(0xff, SFC_TMODE_1_1_1, 0, 0, SFC_PFMT_ADDR_FIRST, 0)
@ -97,6 +99,7 @@ typedef struct nand_chip {
/* Manufacturer and device ID bytes */ /* Manufacturer and device ID bytes */
uint8_t mf_id; uint8_t mf_id;
uint8_t dev_id; uint8_t dev_id;
uint8_t dev_id2;
/* Row/column address width */ /* Row/column address width */
uint8_t row_cycles; uint8_t row_cycles;
@ -158,6 +161,7 @@ typedef struct nand_drv {
/* Probed mf_id / dev_id for debugging, in case identification fails. */ /* Probed mf_id / dev_id for debugging, in case identification fails. */
uint8_t mf_id; uint8_t mf_id;
uint8_t dev_id; uint8_t dev_id;
uint8_t dev_id2;
/* SFC commands used for I/O, these are set based on chip data */ /* SFC commands used for I/O, these are set based on chip data */
uint32_t cmd_page_read; uint32_t cmd_page_read;